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ZTEX |
/*%
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memfifo -- Connects the bi-directional high speed interface of default firmware to a FIFO built of on-board SDRAM or on-chip BRAM
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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Copyright and related rights are licensed under the Solderpad Hardware
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License, Version 0.51 (the "License"); you may not use this file except
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in compliance with the License. You may obtain a copy of the License at
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http://solderpad.org/licenses/SHL-0.51.
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Unless required by applicable law or agreed to in writing, software, hardware
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and materials distributed under this License is distributed on an "AS IS"
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BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing permissions
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and limitations under the License.
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%*/
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/*
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Top level module: glues everything together.
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*/
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module memfifo (
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input fxclk_in,
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input ifclk_in,
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input reset,
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inout [3:0] gpio_n,
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// debug
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output led,
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output [9:0] led1,
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output [19:0] led2,
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input SW10,
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// ddr3
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inout [15:0] ddr3_dq,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_p,
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output [13:0] ddr3_addr,
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output [2:0] ddr3_ba,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_reset_n,
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output [0:0] ddr3_ck_p,
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output [0:0] ddr3_ck_n,
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output [0:0] ddr3_cke,
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output [1:0] ddr3_dm,
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output [0:0] ddr3_odt,
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// ez-usb
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inout [15:0] fd,
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output SLWR, SLRD,
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output SLOE, PKTEND,
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input EMPTY_FLAG, FULL_FLAG
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);
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wire reset_mem, reset_usb;
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wire ifclk;
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reg reset_ifclk;
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wire [24:0] mem_free;
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wire [9:0] status;
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wire [6:0] if_status;
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wire [3:0] gpio_in;
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// input fifo
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reg [127:0] DI;
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wire FULL, WRERR, USB_DO_valid;
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reg WREN, wrerr_buf, USB_DO_ready, FULL_buf1, FULL_buf2;
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wire [15:0] USB_DO;
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reg [127:0] in_data;
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reg [2:0] wr_cnt;
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reg [6:0] test_cnt0, test_cnt1;
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reg [13:0] test_cs;
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wire [13:0] test_cs_w;
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reg in_valid;
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reg [3:0] clk_div;
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reg DI_run;
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// output fifo
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wire [127:0] DO;
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wire EMPTY, RDERR, USB_DI_ready;
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reg RDEN, rderr_buf, USB_DI_valid;
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reg [127:0] rd_buf;
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reg [2:0] rd_cnt;
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dram_fifo #(
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.FIRST_WORD_FALL_THROUGH("TRUE"), // Sets the FIFO FWFT to FALSE, TRUE
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.ALMOST_EMPTY_OFFSET2(13'h0008)
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) dram_fifo_inst (
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.fxclk_in(fxclk_in), // 26 MHz input clock pin
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.reset(reset || reset_usb),
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.reset_out(reset_mem), // reset output
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.clkout2(), // PLL clock outputs not used for memory interface
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.clkout3(),
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.clkout4(),
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.clkout5(),
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// Memory interface ports
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.ddr3_dq(ddr3_dq),
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.ddr3_dqs_n(ddr3_dqs_n),
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.ddr3_dqs_p(ddr3_dqs_p),
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.ddr3_addr(ddr3_addr),
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.ddr3_ba(ddr3_ba),
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.ddr3_ras_n(ddr3_ras_n),
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.ddr3_cas_n(ddr3_cas_n),
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.ddr3_we_n(ddr3_we_n),
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.ddr3_reset_n(ddr3_reset_n),
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.ddr3_ck_p(ddr3_ck_p),
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.ddr3_ck_n(ddr3_ck_n),
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.ddr3_cke(ddr3_cke),
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.ddr3_dm(ddr3_dm),
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.ddr3_odt(ddr3_odt),
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// input fifo interface, see "7 Series Memory Resources" user guide (ug743)
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.DI(DI),
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.FULL(FULL), // 1-bit output: Full flag
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.ALMOSTFULL1(), // 1-bit output: Almost full flag
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.ALMOSTFULL2(), // 1-bit output: Almost full flag
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.WRERR(WRERR), // 1-bit output: Write error
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.WREN(WREN), // 1-bit input: Write enable
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.WRCLK(ifclk), // 1-bit input: Rising edge write clock.
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// output fifo interface, see "7 Series Memory Resources" user guide (ug743)
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.DO(DO),
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.EMPTY(EMPTY), // 1-bit output: Empty flag
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.ALMOSTEMPTY1(), // 1-bit output: Almost empty flag
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.ALMOSTEMPTY2(), // 1-bit output: Almost empty flag
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.RDERR(RDERR), // 1-bit output: Read error
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.RDCLK(ifclk), // 1-bit input: Read clock
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.RDEN(RDEN), // 1-bit input: Read enable
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// free memory
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.mem_free_out(mem_free),
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// for debugging
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.status(status)
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);
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ezusb_io ezusb_io_inst (
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.ifclk(ifclk),
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.reset(reset), // asynchronous reset input
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.reset_out(reset_usb), // synchronous reset output
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// pins
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.ifclk_in(ifclk_in),
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.fd(fd),
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.SLWR(SLWR),
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.SLRD(SLRD),
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.SLOE(SLOE),
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.PKTEND(PKTEND),
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.EMPTY_FLAG(EMPTY_FLAG),
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.FULL_FLAG(FULL_FLAG),
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// signals for FPGA -> EZ-USB transfer
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.DI(rd_buf[15:0]), // data written to EZ-USB
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.DI_valid(USB_DI_valid), // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
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.DI_ready(USB_DI_ready), // 1 if new data are accepted
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.DI_enable(1'b1), // setting to 0 disables FPGA -> EZ-USB transfers
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.pktend_arm(gpio_in[2]), // 0->1 transition enables the manual PKTEND mechanism:
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// PKTEND is asserted as soon output becomes idle
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// recommended procedure for accurate packet transfers:
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// * DI_validgoes low after last data of package
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// * monitor PKTEND and hold DI_valid until PKTEND is asserted (PKTEND = 0)
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.pktend_timeout(16'd793), // automatic PKTEN assertation after pktend_timeout*65536 (approx. 0.5s) clocks of no
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// output data. Setting to 0 disables this feature.
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// .pktend_timeout(16'd0),
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// signals for EZ-USB -> FPGA transfer
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.DO(USB_DO), // data read from EZ-USB
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.DO_valid(USB_DO_valid), // 1 indicated valid data
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.DO_ready(USB_DO_ready), // setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
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// debug output
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.status(if_status)
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);
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ezusb_gpio ezusb_gpio_inst (
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.clk(ifclk),
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.gpio_n(gpio_n),
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.in(gpio_in),
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.out(4'd0)
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);
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/* BUFR ifclkin_buf (
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.I(ifclk_in),
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.O(ifclk)
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); */
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// assign ifclk = ifclk_in;
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// FPGA Board led
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assign led = !if_status[6]; // led is inverted
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// debug board LEDs
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assign led1 = SW10 ? status : { EMPTY, FULL, wrerr_buf, rderr_buf, if_status[5:0] };
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assign led2[0] = mem_free != { 1'b1, 24'd0 };
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assign led2[1] = mem_free[23:19] < 5'd30;
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assign led2[2] = mem_free[23:19] < 5'd29;
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assign led2[3] = mem_free[23:19] < 5'd27;
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assign led2[4] = mem_free[23:19] < 5'd25;
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assign led2[5] = mem_free[23:19] < 5'd24;
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assign led2[6] = mem_free[23:19] < 5'd22;
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assign led2[7] = mem_free[23:19] < 5'd20;
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assign led2[8] = mem_free[23:19] < 5'd19;
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assign led2[9] = mem_free[23:19] < 5'd17;
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assign led2[10] = mem_free[23:19] < 5'd15;
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assign led2[11] = mem_free[23:19] < 5'd13;
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assign led2[12] = mem_free[23:19] < 5'd12;
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assign led2[13] = mem_free[23:19] < 5'd10;
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assign led2[14] = mem_free[23:19] < 5'd8;
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assign led2[15] = mem_free[23:19] < 5'd7;
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assign led2[16] = mem_free[23:19] < 5'd5;
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assign led2[17] = mem_free[23:19] < 5'd3;
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assign led2[18] = mem_free[23:19] < 5'd2;
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assign led2[19] = mem_free == 25'd0;
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assign test_cs_w = test_cs + {1'b1, test_cnt0};
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always @ (posedge ifclk)
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begin
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reset_ifclk <= reset || reset_usb || reset_mem;
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if ( reset_ifclk )
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begin
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rderr_buf <= 1'b0;
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wrerr_buf <= 1'b0;
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end else
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begin
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rderr_buf <= rderr_buf || RDERR;
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wrerr_buf <= wrerr_buf || WRERR;
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end
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// FPGA -> EZ-USB FIFO
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DI_run <= !gpio_in[2];
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if ( reset_ifclk )
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begin
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rd_cnt <= 3'd0;
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USB_DI_valid <= 1'd0;
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end else if ( USB_DI_ready )
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begin
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USB_DI_valid <= !EMPTY && DI_run;
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if ( !EMPTY && DI_run )
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begin
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if ( rd_cnt == 3'd0 )
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begin
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rd_buf <= DO;
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end else
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begin
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rd_buf[111:0] <= rd_buf[127:16];
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end
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rd_cnt <= rd_cnt+1;
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end
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end
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RDEN <= !reset_ifclk && USB_DI_ready && !EMPTY && (rd_cnt==3'd0) && DI_run;
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// data source
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USB_DO_ready = !reset_ifclk && ((gpio_in[1:0]==2'd0 && !FULL) || (gpio_in[1:0]==2'd3));
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FULL_buf1 <= FULL;
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FULL_buf2 <= FULL_buf1;
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if ( reset_ifclk )
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begin
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in_data <= 128'd0;
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in_valid <= 1'b0;
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wr_cnt <= 3'd0;
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test_cnt0 <= 7'd0;
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test_cnt1 <= 7'd111;
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test_cs <= 12'd47;
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WREN <= 1'b0;
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clk_div <= 4'd15;
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end else if ( !FULL_buf2 ) // FULL can be processed delayed because data is buffered
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begin
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if ( in_valid ) DI <= in_data;
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if ( gpio_in[1:0] == 2'd0 ) // input from USB
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begin
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if ( USB_DO_valid )
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begin
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in_data <= { USB_DO, in_data[127:16] };
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in_valid <= wr_cnt == 3'd7;
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wr_cnt <= wr_cnt + 1;
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end else
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begin
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in_valid <= 1'b0;
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end
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end else if ( clk_div == 2'd0 ) // test data generator
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begin
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if ( wr_cnt == 3'd7 )
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begin
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in_data[127:112] <= { 1'b1, test_cs_w[6:0] ^ test_cs_w[13:7], 1'b1, test_cnt0 };
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test_cnt0 <= test_cnt1;
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test_cnt1 <= test_cnt1 + 7'd111;
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test_cs <= 14'd47;
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in_valid <= 1'b1;
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end else
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begin
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test_cnt0 <= test_cnt0 + 7'd94; // (111*2) & 127
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test_cnt1 <= test_cnt1 + 7'd94; // (111*2) & 127
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test_cs <= test_cs + { 1'b1, test_cnt1 } + { 1'b0, test_cnt0 };
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in_data[127:112] <= { 1'b1, test_cnt1, 1'b0, test_cnt0 };
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in_valid <= 1'b0;
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end
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in_data[111:0] <= in_data[127:16];
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wr_cnt <= wr_cnt + 1;
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end else
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begin
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in_valid <= 1'b0;
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end
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// mode 3 is a debug mode: dummy read from USB, write test data
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if ( gpio_in[0]==1'd1 )
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// if ( gpio_in[1:0]==2'd1 )
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begin
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clk_div <= 4'd0; // data rate: 208 MByte/s
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end else
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begin
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clk_div <= clk_div + 1; // data rate: 13 MByte/s
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end
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end
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WREN <= !reset_ifclk && in_valid && !FULL;
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end
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endmodule
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