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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ecc_merge_enc.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ecc_merge_enc
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#(
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parameter TCQ = 100,
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parameter PAYLOAD_WIDTH = 64,
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parameter CODE_WIDTH = 72,
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parameter DATA_BUF_ADDR_WIDTH = 4,
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parameter DATA_BUF_OFFSET_WIDTH = 1,
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parameter DATA_WIDTH = 64,
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parameter DQ_WIDTH = 72,
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parameter ECC_WIDTH = 8,
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parameter nCK_PER_CLK = 4
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)
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(
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/*AUTOARG*/
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// Outputs
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mc_wrdata, mc_wrdata_mask,
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// Inputs
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clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
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);
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input clk;
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input rst;
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input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
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input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
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input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
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reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
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reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
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reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
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always @(posedge clk) wr_data_r <= #TCQ wr_data;
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always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
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always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
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// Merge new data with memory read data.
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wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
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genvar h;
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genvar i;
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generate
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for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
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for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
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assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
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wr_data_mask[h*DATA_WIDTH/8+i]
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? rd_merge_data[h*DATA_WIDTH+i*8+:8]
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: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
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end
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if (PAYLOAD_WIDTH > DATA_WIDTH)
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assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
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wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
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end
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endgenerate
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// Generate ECC and overlay onto mc_wrdata.
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input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
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input [2*nCK_PER_CLK-1:0] raw_not_ecc;
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reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
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always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
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output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
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reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
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genvar j;
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integer k;
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generate
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for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
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always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
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mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
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{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
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merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
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for (k=0; k<ECC_WIDTH; k=k+1)
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if (~raw_not_ecc_r[j])
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mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
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^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
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h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
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end
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end
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endgenerate
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always @(posedge clk) mc_wrdata <= mc_wrdata_c;
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// Set all DRAM masks to zero.
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output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
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assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
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endmodule
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