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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// materials, including for any direct, or any indirect,
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//
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// CRITICAL APPLICATIONS
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 2.0
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// \ \ Application : MIG
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// / / Filename : mig_7series_v2_3_axi_fi_xor.v
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// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
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// \ \ / \ Date Created : Tue Sept 21 2010
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// \___\/\___\
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//
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//*****************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1ps/1ps
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`default_nettype none
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module mig_7series_v2_3_fi_xor #
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(
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///////////////////////////////////////////////////////////////////////////////
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// Parameter Definitions
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///////////////////////////////////////////////////////////////////////////////
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// External Memory Data Width
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parameter integer DQ_WIDTH = 72,
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parameter integer DQS_WIDTH = 9,
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parameter integer nCK_PER_CLK = 4
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)
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(
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///////////////////////////////////////////////////////////////////////////////
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// Port Declarations
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///////////////////////////////////////////////////////////////////////////////
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input wire clk ,
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input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
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output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
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input wire wrdata_en ,
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input wire [DQS_WIDTH-1:0] fi_xor_we ,
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input wire [DQ_WIDTH-1:0] fi_xor_wrdata
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);
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/////////////////////////////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Local parameters
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////////////////////////////////////////////////////////////////////////////////
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localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
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////////////////////////////////////////////////////////////////////////////////
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// Wires/Reg declarations
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////////////////////////////////////////////////////////////////////////////////
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reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
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////////////////////////////////////////////////////////////////////////////////
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// BEGIN RTL
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///////////////////////////////////////////////////////////////////////////////
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// Register in the fi_xor_wrdata on a byte width basis
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generate
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begin
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genvar i;
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for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
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always @(posedge clk) begin
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if (wrdata_en) begin
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fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
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end
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else if (fi_xor_we[i]) begin
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fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
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end
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else begin
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fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
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end
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end
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end
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end
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endgenerate
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assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
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// Pass through upper bits
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assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
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endmodule
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`default_nettype wire
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