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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_ck_addr_cmd_delay.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Shift CK/Address/Commands/Controls
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay #
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(
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parameter TCQ = 100,
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parameter tCK = 3636,
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parameter DQS_CNT_WIDTH = 3,
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parameter N_CTL_LANES = 3,
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parameter SIM_CAL_OPTION = "NONE"
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)
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(
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input clk,
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input rst,
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// Start only after PO_CIRC_BUF_DELAY decremented
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input cmd_delay_start,
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// Control lane being shifted using Phaser_Out fine delay taps
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output reg [N_CTL_LANES-1:0] ctl_lane_cnt,
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// Inc/dec Phaser_Out fine delay line
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output reg po_stg2_f_incdec,
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output reg po_en_stg2_f,
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output reg po_stg2_c_incdec,
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output reg po_en_stg2_c,
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// Completed delaying CK/Address/Commands/Controls
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output po_ck_addr_cmd_delay_done
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);
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localparam TAP_CNT_LIMIT = 63;
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//Calculate the tap resolution of the PHASER based on the clock period
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localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :
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tCK > 2500 ? 2 : 1);
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localparam integer PHASER_TAP_RES = ((tCK/2)/64);
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// Determine whether 300 ps or 350 ps delay required
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localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;
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// Determine the number of Phaser_Out taps required to delay by 300 ps
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// 300 ps is the PCB trace uncertainty between CK and DQS byte groups
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// Increment control byte lanes
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localparam TAP_CNT = 0;
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//localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;
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//Decrement control byte lanes
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localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29;
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reg delay_dec_done;
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reg delay_done_r1;
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reg delay_done_r2;
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reg delay_done_r3;
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reg delay_done_r4 /* synthesis syn_maxfan = 10 */;
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reg [5:0] delay_cnt_r;
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reg [5:0] delaydec_cnt_r;
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reg po_cnt_inc;
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reg po_cnt_dec;
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reg [3:0] wait_cnt_r;
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assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;
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always @(posedge clk) begin
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if (rst || po_cnt_dec || po_cnt_inc)
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wait_cnt_r <= #TCQ 'd8;
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else if (cmd_delay_start && (wait_cnt_r > 'd0))
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wait_cnt_r <= #TCQ wait_cnt_r - 1;
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end
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always @(posedge clk) begin
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if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))
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po_cnt_inc <= #TCQ 1'b0;
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else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))
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po_cnt_inc <= #TCQ 1'b1;
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else
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po_cnt_inc <= #TCQ 1'b0;
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end
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//Tap decrement
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always @(posedge clk) begin
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if (rst || (delaydec_cnt_r == 'd0))
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po_cnt_dec <= #TCQ 1'b0;
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else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))
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po_cnt_dec <= #TCQ 1'b1;
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else
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po_cnt_dec <= #TCQ 1'b0;
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end
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//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
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//the alignment is started once the
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always @(posedge clk) begin
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if (rst) begin
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po_stg2_f_incdec <= #TCQ 1'b0;
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po_en_stg2_f <= #TCQ 1'b0;
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po_stg2_c_incdec <= #TCQ 1'b0;
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po_en_stg2_c <= #TCQ 1'b0;
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end else begin
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if (po_cnt_dec) begin
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po_stg2_f_incdec <= #TCQ 1'b0;
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po_en_stg2_f <= #TCQ 1'b1;
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end else begin
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po_stg2_f_incdec <= #TCQ 1'b0;
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po_en_stg2_f <= #TCQ 1'b0;
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end
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if (po_cnt_inc) begin
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po_stg2_c_incdec <= #TCQ 1'b1;
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po_en_stg2_c <= #TCQ 1'b1;
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end else begin
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po_stg2_c_incdec <= #TCQ 1'b0;
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po_en_stg2_c <= #TCQ 1'b0;
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end
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end
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end
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// delay counter to count 2 cycles
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// Increment coarse taps by 2 for all control byte lanes
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// to mitigate late writes
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always @(posedge clk) begin
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// load delay counter with init value
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if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL"))
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delay_cnt_r <= #TCQ 'd0;
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else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
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delay_cnt_r <= #TCQ 'd1;
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else if (po_cnt_inc && (delay_cnt_r > 6'd0))
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delay_cnt_r <= #TCQ delay_cnt_r - 1;
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end
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// delay counter to count TAP_DEC cycles
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always @(posedge clk) begin
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// load delay counter with init value of TAP_DEC
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if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
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delaydec_cnt_r <= #TCQ TAP_DEC;
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else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))
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delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;
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end
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//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
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//This ensures all ctrl byte lanes have had their output phase shifted.
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always @(posedge clk) begin
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if (rst || ~cmd_delay_start )
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ctl_lane_cnt <= #TCQ 6'b0;
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else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))
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ctl_lane_cnt <= #TCQ ctl_lane_cnt;
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else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))
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ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
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end
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// All control lanes have decremented to 31 fine taps from 46
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always @(posedge clk) begin
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if (rst || ~cmd_delay_start) begin
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delay_dec_done <= #TCQ 1'b0;
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end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||
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((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin
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delay_dec_done <= #TCQ 1'b1;
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end
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end
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always @(posedge clk) begin
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delay_done_r1 <= #TCQ delay_dec_done;
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delay_done_r2 <= #TCQ delay_done_r1;
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delay_done_r3 <= #TCQ delay_done_r2;
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delay_done_r4 <= #TCQ delay_done_r3;
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end
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endmodule
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