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//*****************************************************************************
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// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_init.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
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// \ \ / \ Date Created:
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose:
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// Memory initialization and overall master state control during
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// initialization and calibration. Specifically, the following functions
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// are performed:
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// 1. Memory initialization (initial AR, mode register programming, etc.)
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// 2. Initiating write leveling
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// 3. Generate training pattern writes for read leveling. Generate
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// memory readback for read leveling.
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// This module has an interface for providing control/address and write
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// data to the PHY Control Block during initialization/calibration.
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// Once initialization and calibration are complete, control is passed to the MC.
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//
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//Reference:
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//Revision History:
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//
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//*****************************************************************************
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/******************************************************************************
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**$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
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**$Date: 2011/06/02 08:35:09 $
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**$Author: mishra $
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**$Revision: 1.1 $
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**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $
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******************************************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_init #
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(
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parameter tCK = 1500, // DDRx SDRAM clock period
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parameter TCQ = 100,
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parameter nCK_PER_CLK = 4, // # of memory clocks per CLK
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parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps)
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parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
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// 1 - ODT output from FPGA
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parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3
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// 150 - 1.50 V
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// 135 - 1.35 V
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// 125 - 1.25 V
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parameter VREF = "EXTERNAL", // Internal or external Vref
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parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH
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parameter BANK_WIDTH = 2,
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parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
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parameter COL_WIDTH = 10,
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parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for
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// component I/F with CS_WIDTH=1,
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// nCS_PER_RANK=# of components
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parameter DQ_WIDTH = 64,
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parameter DQS_WIDTH = 8,
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parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
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parameter ROW_WIDTH = 14,
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parameter CS_WIDTH = 1,
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parameter RANKS = 1, // # of memory ranks in the interface
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parameter CKE_WIDTH = 1, // # of cke outputs
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parameter DRAM_TYPE = "DDR3",
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parameter REG_CTRL = "ON",
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parameter ADDR_CMD_MODE= "1T",
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// calibration Address
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parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
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parameter CALIB_COL_ADD = 12'h000, // Calibration column address
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parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
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// DRAM mode settings
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parameter AL = "0", // Additive Latency option
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parameter BURST_MODE = "8", // Burst length
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parameter BURST_TYPE = "SEQ", // Burst type
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// parameter nAL = 0, // Additive latency (in clk cyc)
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parameter nCL = 5, // Read CAS latency (in clk cyc)
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parameter nCWL = 5, // Write CAS latency (in clk cyc)
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parameter tRFC = 110000, // Refresh-to-command delay (in ps)
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parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes
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parameter REFRESH_TIMER_WIDTH = 8,
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parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
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parameter RTT_NOM = "60", // Nominal ODT termination value
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parameter RTT_WR = "60", // Write ODT termination value
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parameter WRLVL = "ON", // Enable write leveling
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// parameter PHASE_DETECT = "ON", // Enable read phase detector
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parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
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parameter nSLOTS = 1, // Number of DIMM SLOTs in the system
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parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT"
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parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL"
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parameter CKE_ODT_AUX = "FALSE",
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parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration
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parameter TEST_AL = "0", // Internal use for ICM verification
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parameter FIXED_VICTIM = "TRUE",
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parameter BYPASS_COMPLEX_OCAL = "FALSE"
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)
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(
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input clk,
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input rst,
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input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o,
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input delay_incdec_done,
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input ck_addr_cmd_delay_done,
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input pi_phase_locked_all,
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input pi_dqs_found_done,
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input dqsfound_retry,
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input dqs_found_prech_req,
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output reg pi_phaselock_start,
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output pi_phase_locked_err,
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output pi_calib_done,
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input phy_if_empty,
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// Read/write calibration interface
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input wrlvl_done,
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input wrlvl_rank_done,
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input wrlvl_byte_done,
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input wrlvl_byte_redo,
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input wrlvl_final,
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output reg wrlvl_final_if_rst,
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input oclkdelay_calib_done,
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input oclk_prech_req,
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input oclk_calib_resume,
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input lim_done,
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input lim_wr_req,
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output reg oclkdelay_calib_start,
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//complex oclkdelay calibration
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input complex_oclkdelay_calib_done,
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input complex_oclk_prech_req,
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input complex_oclk_calib_resume,
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output reg complex_oclkdelay_calib_start,
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input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt
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output reg complex_ocal_num_samples_inc,
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input complex_ocal_num_samples_done_r,
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input [2:0] complex_ocal_rd_victim_sel,
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output reg complex_ocal_reset_rd_addr,
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input complex_ocal_ref_req,
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output reg complex_ocal_ref_done,
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input done_dqs_tap_inc,
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input [5:0] rd_data_offset_0,
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input [5:0] rd_data_offset_1,
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input [5:0] rd_data_offset_2,
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input [6*RANKS-1:0] rd_data_offset_ranks_0,
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input [6*RANKS-1:0] rd_data_offset_ranks_1,
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input [6*RANKS-1:0] rd_data_offset_ranks_2,
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input pi_dqs_found_rank_done,
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input wrcal_done,
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input wrcal_prech_req,
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input wrcal_read_req,
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input wrcal_act_req,
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input temp_wrcal_done,
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input [7:0] slot_0_present,
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input [7:0] slot_1_present,
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output reg wl_sm_start,
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output reg wr_lvl_start,
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output reg wrcal_start,
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output reg wrcal_rd_wait,
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output reg wrcal_sanity_chk,
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output reg tg_timer_done,
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output reg no_rst_tg_mc,
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input rdlvl_stg1_done,
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input rdlvl_stg1_rank_done,
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output reg rdlvl_stg1_start,
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output reg pi_dqs_found_start,
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output reg detect_pi_found_dqs,
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// rdlvl stage 1 precharge requested after each DQS
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input rdlvl_prech_req,
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input rdlvl_last_byte_done,
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input wrcal_resume,
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input wrcal_sanity_chk_done,
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// MPR read leveling
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input mpr_rdlvl_done,
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input mpr_rnk_done,
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input mpr_last_byte_done,
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output reg mpr_rdlvl_start,
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output reg mpr_end_if_reset,
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// PRBS Read Leveling
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input prbs_rdlvl_done,
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input prbs_last_byte_done,
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input prbs_rdlvl_prech_req,
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input complex_victim_inc,
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input [2:0] rd_victim_sel,
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input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt,
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output reg [2:0] victim_sel,
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output reg [DQS_CNT_WIDTH:0]victim_byte_cnt,
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output reg prbs_rdlvl_start,
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output reg prbs_gen_clk_en,
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output reg prbs_gen_oclk_clk_en,
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output reg complex_sample_cnt_inc,
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output reg complex_sample_cnt_inc_ocal,
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output reg complex_wr_done,
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// Signals shared btw multiple calibration stages
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output reg prech_done,
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// Data select / status
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output reg init_calib_complete,
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// Signal to mask memory model error for Invalid latching edge
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output reg calib_writes,
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// PHY address/control
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// 2 commands to PHY Control Block per div 2 clock in 2:1 mode
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// 4 commands to PHY Control Block per div 4 clock in 4:1 mode
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output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
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output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
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output reg [nCK_PER_CLK-1:0] phy_ras_n,
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output reg [nCK_PER_CLK-1:0] phy_cas_n,
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output reg [nCK_PER_CLK-1:0] phy_we_n,
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output reg phy_reset_n,
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output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
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// Hard PHY Interface signals
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input phy_ctl_ready,
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input phy_ctl_full,
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input phy_cmd_full,
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input phy_data_full,
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output reg calib_ctl_wren,
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output reg calib_cmd_wren,
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output reg [1:0] calib_seq,
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output reg write_calib,
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output reg read_calib,
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// PHY_Ctl_Wd
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output reg [2:0] calib_cmd,
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// calib_aux_out used for CKE and ODT
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output reg [3:0] calib_aux_out,
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output reg [1:0] calib_odt ,
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output reg [nCK_PER_CLK-1:0] calib_cke ,
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output [1:0] calib_rank_cnt,
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output reg [1:0] calib_cas_slot,
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output reg [5:0] calib_data_offset_0,
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output reg [5:0] calib_data_offset_1,
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output reg [5:0] calib_data_offset_2,
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// PHY OUT_FIFO
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output reg calib_wrdata_en,
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output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata,
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// PHY Read
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output phy_rddata_en,
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output phy_rddata_valid,
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output [255:0] dbg_phy_init,
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input read_pause,
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input reset_rd_addr,
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//OCAL centering calibration
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input oclkdelay_center_calib_start,
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input oclk_center_write_resume,
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input oclkdelay_center_calib_done
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);
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//*****************************************************************************
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// Assertions to be added
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//*****************************************************************************
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// The phy_ctl_full signal must never be asserted in synchronous mode of
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// operation either 4:1 or 2:1
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//
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// The RANKS parameter must never be set to '0' by the user
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// valid values: 1 to 4
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//
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//*****************************************************************************
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//***************************************************************************
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// Number of Read level stage 1 writes limited to a SDRAM row
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// The address of Read Level stage 1 reads must also be limited
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// to a single SDRAM row
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// (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128
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localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 :
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|
|
(BURST_MODE == "4") ? 8 : 4;
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
localparam ADDR_INC = (BURST_MODE == "8") ? 8 :
|
321 |
|
|
(BURST_MODE == "4") ? 4 : 8;
|
322 |
|
|
|
323 |
|
|
// In a 2 slot dual rank per system RTT_NOM values
|
324 |
|
|
// for Rank2 and Rank3 default to 40 ohms
|
325 |
|
|
localparam RTT_NOM2 = "40";
|
326 |
|
|
localparam RTT_NOM3 = "40";
|
327 |
|
|
|
328 |
|
|
localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR;
|
329 |
|
|
|
330 |
|
|
// Specifically for use with half-frequency controller (nCK_PER_CLK=2)
|
331 |
|
|
// = 1 if burst length = 4, = 0 if burst length = 8. Determines how
|
332 |
|
|
// often row command needs to be issued during read-leveling
|
333 |
|
|
// For DDR3 the burst length is fixed during calibration
|
334 |
|
|
localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 :
|
335 |
|
|
(BURST_MODE == "8") ? 1'b0 :
|
336 |
|
|
((BURST_MODE == "4") ? 1'b1 : 1'b0);
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
//***************************************************************************
|
342 |
|
|
// Counter values used to determine bus timing
|
343 |
|
|
// NOTE on all counter terminal counts - these can/should be one less than
|
344 |
|
|
// the actual delay to take into account extra clock cycle delay in
|
345 |
|
|
// generating the corresponding "done" signal
|
346 |
|
|
//***************************************************************************
|
347 |
|
|
|
348 |
|
|
localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;
|
349 |
|
|
|
350 |
|
|
// Calculate initial delay required in number of CLK clock cycles
|
351 |
|
|
// to delay initially. The counter is clocked by [CLK/1024] - which
|
352 |
|
|
// is approximately division by 1000 - note that the formulas below will
|
353 |
|
|
// result in more than the minimum wait time because of this approximation.
|
354 |
|
|
// NOTE: For DDR3 JEDEC specifies to delay reset
|
355 |
|
|
// by 200us, and CKE by an additional 500us after power-up
|
356 |
|
|
// For DDR2 CKE is delayed by 200us after power up.
|
357 |
|
|
localparam DDR3_RESET_DELAY_NS = 200000;
|
358 |
|
|
localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;
|
359 |
|
|
localparam DDR2_CKE_DELAY_NS = 200000;
|
360 |
|
|
localparam PWRON_RESET_DELAY_CNT =
|
361 |
|
|
((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);
|
362 |
|
|
localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ?
|
363 |
|
|
(((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :
|
364 |
|
|
(((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));
|
365 |
|
|
// FOR DDR2 -1 taken out. With -1 not getting 200us. The equation
|
366 |
|
|
// needs to be reworked.
|
367 |
|
|
localparam DDR2_INIT_PRE_DELAY_PS = 400000;
|
368 |
|
|
localparam DDR2_INIT_PRE_CNT =
|
369 |
|
|
((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;
|
370 |
|
|
|
371 |
|
|
// Calculate tXPR time: reset from CKE HIGH to valid command after power-up
|
372 |
|
|
// tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock
|
373 |
|
|
// cycles because this counter actually starts up before CKE is asserted
|
374 |
|
|
// to memory.
|
375 |
|
|
localparam TXPR_DELAY_CNT =
|
376 |
|
|
(5*CLK_MEM_PERIOD > tRFC+10000) ?
|
377 |
|
|
(((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 :
|
378 |
|
|
(((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11;
|
379 |
|
|
|
380 |
|
|
// tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV
|
381 |
|
|
localparam TDLLK_TZQINIT_DELAY_CNT = 255;
|
382 |
|
|
|
383 |
|
|
// TWR values in ns. Both DDR2 and DDR3 have the same value.
|
384 |
|
|
// 15000ns/tCK
|
385 |
|
|
localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?
|
386 |
|
|
(15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;
|
387 |
|
|
|
388 |
|
|
// time to wait between consecutive commands in PHY_INIT - this is a
|
389 |
|
|
// generic number, and must be large enough to account for worst case
|
390 |
|
|
// timing parameter (tRFC - refresh-to-active) across all memory speed
|
391 |
|
|
// grades and operating frequencies. Expressed in clk
|
392 |
|
|
// (Divided by 4 or Divided by 2) clock cycles.
|
393 |
|
|
localparam CNTNEXT_CMD = 7'b1111111;
|
394 |
|
|
|
395 |
|
|
// Counter values to keep track of which MR register to load during init
|
396 |
|
|
// Set value of INIT_CNT_MR_DONE to equal value of counter for last mode
|
397 |
|
|
// register configured during initialization.
|
398 |
|
|
// NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init
|
399 |
|
|
localparam INIT_CNT_MR2 = 2'b00;
|
400 |
|
|
localparam INIT_CNT_MR3 = 2'b01;
|
401 |
|
|
localparam INIT_CNT_MR1 = 2'b10;
|
402 |
|
|
localparam INIT_CNT_MR0 = 2'b11;
|
403 |
|
|
localparam INIT_CNT_MR_DONE = 2'b11;
|
404 |
|
|
|
405 |
|
|
// Register chip programmable values for DDR3
|
406 |
|
|
// The register chip for the registered DIMM needs to be programmed
|
407 |
|
|
// before the initialization of the registered DIMM.
|
408 |
|
|
// Address for the control word is in : DBA2, DA2, DA1, DA0
|
409 |
|
|
// Data for the control word is in: DBA1 DBA0, DA4, DA3
|
410 |
|
|
// The values will be stored in the local param in the following format
|
411 |
|
|
// {DBA[2:0], DA[4:0]}
|
412 |
|
|
|
413 |
|
|
// RC0 is global features control word. Address == 000
|
414 |
|
|
|
415 |
|
|
localparam REG_RC0 = 8'b00000000;
|
416 |
|
|
|
417 |
|
|
// RC1 Clock driver enable control word. Enables or disables the four
|
418 |
|
|
// output clocks in the register chip. For single rank and dual rank
|
419 |
|
|
// two clocks will be enabled and for quad rank all the four clocks
|
420 |
|
|
// will be enabled. Address == 000. Data = 0110 for single and dual rank.
|
421 |
|
|
// = 0000 for quad rank
|
422 |
|
|
localparam REG_RC1 = 8'b00000001;
|
423 |
|
|
|
424 |
|
|
// RC2 timing control word. Set in 1T timing mode
|
425 |
|
|
// Address = 010. Data = 0000
|
426 |
|
|
localparam REG_RC2 = 8'b00000010;
|
427 |
|
|
|
428 |
|
|
// RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads)
|
429 |
|
|
// This setting is specific to RDIMMs from Micron Technology
|
430 |
|
|
localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011;
|
431 |
|
|
|
432 |
|
|
// RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads)
|
433 |
|
|
// This setting is specific to RDIMMs from Micron Technology
|
434 |
|
|
localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100;
|
435 |
|
|
|
436 |
|
|
// RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads)
|
437 |
|
|
// This setting is specific to RDIMMs from Micron Technology
|
438 |
|
|
localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101;
|
439 |
|
|
|
440 |
|
|
// RC10 timing control work. Setting the data to 0000
|
441 |
|
|
localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 :
|
442 |
|
|
(tCK >= 1250 && tCK < 1500) ? 4'b0011 :
|
443 |
|
|
(tCK >= 1500 && tCK < 1875) ? 4'b0010 :
|
444 |
|
|
(tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000;
|
445 |
|
|
|
446 |
|
|
localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010};
|
447 |
|
|
|
448 |
|
|
localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0;
|
449 |
|
|
localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} :
|
450 |
|
|
(DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} :
|
451 |
|
|
{1'b0,VREF_ENCODING,2'b00} ;
|
452 |
|
|
|
453 |
|
|
localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011};
|
454 |
|
|
|
455 |
|
|
// For non-zero AL values
|
456 |
|
|
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
|
457 |
|
|
|
458 |
|
|
// Adding the register dimm latency to write latency
|
459 |
|
|
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
|
460 |
|
|
|
461 |
|
|
// Count value to generate pi_phase_locked_err signal
|
462 |
|
|
localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000;
|
463 |
|
|
|
464 |
|
|
// Timeout interval for detecting error with Traffic Generator
|
465 |
|
|
localparam [13:0] TG_TIMER_TIMEOUT
|
466 |
|
|
= (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001;
|
467 |
|
|
|
468 |
|
|
//bit num per DQS
|
469 |
|
|
localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH;
|
470 |
|
|
|
471 |
|
|
//COMPLEX_ROW_CNT_BYTE
|
472 |
|
|
localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2;
|
473 |
|
|
localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1;
|
474 |
|
|
|
475 |
|
|
// Master state machine encoding
|
476 |
|
|
localparam INIT_IDLE = 7'b0000000; //0
|
477 |
|
|
localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1
|
478 |
|
|
localparam INIT_LOAD_MR = 7'b0000010; //2
|
479 |
|
|
localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3
|
480 |
|
|
localparam INIT_ZQCL = 7'b0000100; //4
|
481 |
|
|
localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5
|
482 |
|
|
localparam INIT_WRLVL_START = 7'b0000110; //6
|
483 |
|
|
localparam INIT_WRLVL_WAIT = 7'b0000111; //7
|
484 |
|
|
localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8
|
485 |
|
|
localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9
|
486 |
|
|
localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A
|
487 |
|
|
localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B
|
488 |
|
|
localparam INIT_RDLVL_ACT = 7'b0001100; //C
|
489 |
|
|
localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D
|
490 |
|
|
localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E
|
491 |
|
|
localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F
|
492 |
|
|
localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10
|
493 |
|
|
localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11
|
494 |
|
|
localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12
|
495 |
|
|
localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13
|
496 |
|
|
localparam INIT_PRECHARGE = 7'b0010100; //14
|
497 |
|
|
localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15
|
498 |
|
|
localparam INIT_DONE = 7'b0010110; //16
|
499 |
|
|
localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17
|
500 |
|
|
localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18
|
501 |
|
|
localparam INIT_REFRESH = 7'b0011001; //19
|
502 |
|
|
localparam INIT_REFRESH_WAIT = 7'b0011010; //1A
|
503 |
|
|
localparam INIT_REG_WRITE = 7'b0011011; //1B
|
504 |
|
|
localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C
|
505 |
|
|
localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D
|
506 |
|
|
localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E
|
507 |
|
|
localparam INIT_WRCAL_ACT = 7'b0011111; //1F
|
508 |
|
|
localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20
|
509 |
|
|
localparam INIT_WRCAL_WRITE = 7'b0100001; //21
|
510 |
|
|
localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22
|
511 |
|
|
localparam INIT_WRCAL_READ = 7'b0100011; //23
|
512 |
|
|
localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24
|
513 |
|
|
localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25
|
514 |
|
|
localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26
|
515 |
|
|
localparam INIT_MPR_RDEN = 7'b0100111; //27
|
516 |
|
|
localparam INIT_MPR_WAIT = 7'b0101000; //28
|
517 |
|
|
localparam INIT_MPR_READ = 7'b0101001; //29
|
518 |
|
|
localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A
|
519 |
|
|
localparam INIT_MPR_DISABLE = 7'b0101011; //2B
|
520 |
|
|
localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C
|
521 |
|
|
localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D
|
522 |
|
|
localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E
|
523 |
|
|
localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F
|
524 |
|
|
localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30
|
525 |
|
|
localparam INIT_OCLKDELAY_READ = 7'b0110001; //31
|
526 |
|
|
localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32
|
527 |
|
|
localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33
|
528 |
|
|
localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34
|
529 |
|
|
localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35
|
530 |
|
|
localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36
|
531 |
|
|
localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37
|
532 |
|
|
localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38
|
533 |
|
|
localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39
|
534 |
|
|
localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A
|
535 |
|
|
localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B
|
536 |
|
|
localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C
|
537 |
|
|
localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D
|
538 |
|
|
localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E
|
539 |
|
|
localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F
|
540 |
|
|
localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40
|
541 |
|
|
localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41
|
542 |
|
|
localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42
|
543 |
|
|
|
544 |
|
|
integer i, j, k, l, m, n, p, q;
|
545 |
|
|
|
546 |
|
|
reg pi_dqs_found_all_r;
|
547 |
|
|
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1;
|
548 |
|
|
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2;
|
549 |
|
|
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3;
|
550 |
|
|
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4;
|
551 |
|
|
reg pi_calib_rank_done_r;
|
552 |
|
|
reg [13:0] pi_phaselock_timer;
|
553 |
|
|
reg stg1_wr_done;
|
554 |
|
|
reg rnk_ref_cnt;
|
555 |
|
|
reg pi_dqs_found_done_r1;
|
556 |
|
|
reg pi_dqs_found_rank_done_r;
|
557 |
|
|
reg read_calib_int;
|
558 |
|
|
reg read_calib_r;
|
559 |
|
|
reg pi_calib_done_r;
|
560 |
|
|
reg pi_calib_done_r1;
|
561 |
|
|
reg burst_addr_r;
|
562 |
|
|
reg [1:0] chip_cnt_r;
|
563 |
|
|
reg [6:0] cnt_cmd_r;
|
564 |
|
|
reg cnt_cmd_done_r;
|
565 |
|
|
reg cnt_cmd_done_m7_r;
|
566 |
|
|
reg [7:0] cnt_dllk_zqinit_r;
|
567 |
|
|
reg cnt_dllk_zqinit_done_r;
|
568 |
|
|
reg cnt_init_af_done_r;
|
569 |
|
|
reg [1:0] cnt_init_af_r;
|
570 |
|
|
reg [1:0] cnt_init_data_r;
|
571 |
|
|
reg [1:0] cnt_init_mr_r;
|
572 |
|
|
reg cnt_init_mr_done_r;
|
573 |
|
|
reg cnt_init_pre_wait_done_r;
|
574 |
|
|
reg [7:0] cnt_init_pre_wait_r;
|
575 |
|
|
reg [9:0] cnt_pwron_ce_r;
|
576 |
|
|
reg cnt_pwron_cke_done_r;
|
577 |
|
|
reg cnt_pwron_cke_done_r1;
|
578 |
|
|
reg [8:0] cnt_pwron_r;
|
579 |
|
|
reg cnt_pwron_reset_done_r;
|
580 |
|
|
reg cnt_txpr_done_r;
|
581 |
|
|
reg [7:0] cnt_txpr_r;
|
582 |
|
|
reg ddr2_pre_flag_r;
|
583 |
|
|
reg ddr2_refresh_flag_r;
|
584 |
|
|
reg ddr3_lm_done_r;
|
585 |
|
|
reg [4:0] enable_wrlvl_cnt;
|
586 |
|
|
reg init_complete_r;
|
587 |
|
|
reg init_complete_r1;
|
588 |
|
|
reg init_complete_r2;
|
589 |
|
|
(* keep = "true" *) reg init_complete_r_timing;
|
590 |
|
|
(* keep = "true" *) reg init_complete_r1_timing;
|
591 |
|
|
reg [6:0] init_next_state;
|
592 |
|
|
reg [6:0] init_state_r;
|
593 |
|
|
reg [6:0] init_state_r1;
|
594 |
|
|
wire [15:0] load_mr0;
|
595 |
|
|
wire [15:0] load_mr1;
|
596 |
|
|
wire [15:0] load_mr2;
|
597 |
|
|
wire [15:0] load_mr3;
|
598 |
|
|
reg mem_init_done_r;
|
599 |
|
|
reg [1:0] mr2_r [0:3];
|
600 |
|
|
reg [2:0] mr1_r [0:3];
|
601 |
|
|
reg new_burst_r;
|
602 |
|
|
reg [15:0] wrcal_start_dly_r;
|
603 |
|
|
wire wrcal_start_pre;
|
604 |
|
|
reg wrcal_resume_r;
|
605 |
|
|
// Only one ODT signal per rank in PHY Control Block
|
606 |
|
|
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r;
|
607 |
|
|
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1;
|
608 |
|
|
|
609 |
|
|
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;
|
610 |
|
|
reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n;
|
611 |
|
|
wire prech_done_pre;
|
612 |
|
|
reg [15:0] prech_done_dly_r;
|
613 |
|
|
reg prech_pending_r;
|
614 |
|
|
reg prech_req_posedge_r;
|
615 |
|
|
reg prech_req_r;
|
616 |
|
|
reg pwron_ce_r;
|
617 |
|
|
reg first_rdlvl_pat_r;
|
618 |
|
|
reg first_wrcal_pat_r;
|
619 |
|
|
reg phy_wrdata_en;
|
620 |
|
|
reg phy_wrdata_en_r1;
|
621 |
|
|
reg [1:0] wrdata_pat_cnt;
|
622 |
|
|
reg [1:0] wrcal_pat_cnt;
|
623 |
|
|
reg [ROW_WIDTH-1:0] address_w;
|
624 |
|
|
reg [BANK_WIDTH-1:0] bank_w;
|
625 |
|
|
reg rdlvl_stg1_done_r1;
|
626 |
|
|
reg rdlvl_stg1_start_int;
|
627 |
|
|
reg [15:0] rdlvl_start_dly0_r;
|
628 |
|
|
reg rdlvl_start_pre;
|
629 |
|
|
reg rdlvl_last_byte_done_r;
|
630 |
|
|
wire rdlvl_rd;
|
631 |
|
|
wire rdlvl_wr;
|
632 |
|
|
reg rdlvl_wr_r;
|
633 |
|
|
wire rdlvl_wr_rd;
|
634 |
|
|
reg [3:0] reg_ctrl_cnt_r;
|
635 |
|
|
reg [1:0] tmp_mr2_r [0:3];
|
636 |
|
|
reg [2:0] tmp_mr1_r [0:3];
|
637 |
|
|
reg wrlvl_done_r;
|
638 |
|
|
reg wrlvl_done_r1;
|
639 |
|
|
reg wrlvl_rank_done_r1;
|
640 |
|
|
reg wrlvl_rank_done_r2;
|
641 |
|
|
reg wrlvl_rank_done_r3;
|
642 |
|
|
reg wrlvl_rank_done_r4;
|
643 |
|
|
reg wrlvl_rank_done_r5;
|
644 |
|
|
reg wrlvl_rank_done_r6;
|
645 |
|
|
reg wrlvl_rank_done_r7;
|
646 |
|
|
reg [2:0] wrlvl_rank_cntr;
|
647 |
|
|
reg wrlvl_odt_ctl;
|
648 |
|
|
reg wrlvl_odt;
|
649 |
|
|
reg wrlvl_active;
|
650 |
|
|
reg wrlvl_active_r1;
|
651 |
|
|
reg [2:0] num_reads;
|
652 |
|
|
reg temp_wrcal_done_r;
|
653 |
|
|
reg temp_lmr_done;
|
654 |
|
|
reg extend_cal_pat;
|
655 |
|
|
reg [13:0] tg_timer;
|
656 |
|
|
reg tg_timer_go;
|
657 |
|
|
reg cnt_wrcal_rd;
|
658 |
|
|
reg [3:0] cnt_wait;
|
659 |
|
|
reg [7:0] wrcal_reads;
|
660 |
|
|
reg [8:0] stg1_wr_rd_cnt;
|
661 |
|
|
reg phy_data_full_r;
|
662 |
|
|
reg wr_level_dqs_asrt;
|
663 |
|
|
reg wr_level_dqs_asrt_r1;
|
664 |
|
|
reg [1:0] dqs_asrt_cnt;
|
665 |
|
|
|
666 |
|
|
|
667 |
|
|
reg [3:0] num_refresh;
|
668 |
|
|
wire oclkdelay_calib_start_pre;
|
669 |
|
|
reg [15:0] oclkdelay_start_dly_r;
|
670 |
|
|
reg [3:0] oclk_wr_cnt;
|
671 |
|
|
reg [3:0] wrcal_wr_cnt;
|
672 |
|
|
reg wrlvl_final_r;
|
673 |
|
|
|
674 |
|
|
|
675 |
|
|
reg prbs_rdlvl_done_r1;
|
676 |
|
|
reg prbs_rdlvl_done_r2;
|
677 |
|
|
reg prbs_rdlvl_done_r3;
|
678 |
|
|
reg prbs_last_byte_done_r;
|
679 |
|
|
reg phy_if_empty_r;
|
680 |
|
|
reg prbs_pat_resume_int;
|
681 |
|
|
reg complex_row0_wr_done;
|
682 |
|
|
reg complex_row1_wr_done;
|
683 |
|
|
reg complex_row0_rd_done;
|
684 |
|
|
reg complex_row1_rd_done;
|
685 |
|
|
reg complex_row0_rd_done_r1;
|
686 |
|
|
reg [3:0] complex_wait_cnt;
|
687 |
|
|
reg [3:0] complex_num_reads;
|
688 |
|
|
reg [3:0] complex_num_reads_dec;
|
689 |
|
|
reg [ROW_WIDTH-1:0] complex_address;
|
690 |
|
|
reg wr_victim_inc;
|
691 |
|
|
reg [2:0] wr_victim_sel;
|
692 |
|
|
reg [DQS_CNT_WIDTH:0] wr_byte_cnt;
|
693 |
|
|
reg [7:0] complex_row_cnt;
|
694 |
|
|
|
695 |
|
|
reg complex_sample_cnt_inc_r1;
|
696 |
|
|
reg complex_sample_cnt_inc_r2;
|
697 |
|
|
reg complex_odt_ext;
|
698 |
|
|
reg complex_ocal_odt_ext;
|
699 |
|
|
|
700 |
|
|
reg wrcal_final_chk;
|
701 |
|
|
wire prech_req;
|
702 |
|
|
|
703 |
|
|
reg read_pause_r1;
|
704 |
|
|
reg read_pause_r2;
|
705 |
|
|
wire read_pause_ext;
|
706 |
|
|
reg reset_rd_addr_r1;
|
707 |
|
|
reg complex_rdlvl_int_ref_req;
|
708 |
|
|
reg ext_int_ref_req;
|
709 |
|
|
|
710 |
|
|
//complex OCLK delay calibration
|
711 |
|
|
reg [7:0] complex_row_cnt_ocal;
|
712 |
|
|
reg [4:0] complex_num_writes;
|
713 |
|
|
reg [4:0] complex_num_writes_dec;
|
714 |
|
|
reg complex_oclkdelay_calib_start_int;
|
715 |
|
|
reg complex_oclkdelay_calib_start_r1;
|
716 |
|
|
reg complex_oclkdelay_calib_start_r2;
|
717 |
|
|
reg complex_oclkdelay_calib_done_r1;
|
718 |
|
|
// reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal;
|
719 |
|
|
reg [2:0] wr_victim_sel_ocal;
|
720 |
|
|
|
721 |
|
|
reg complex_row1_rd_done_r1; //time for switch to write
|
722 |
|
|
reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1)
|
723 |
|
|
reg complex_byte_rd_done; //read for the byte is done
|
724 |
|
|
reg complex_byte_rd_done_r1;
|
725 |
|
|
// reg complex_row_change; //every 16 rows of read, it is set to "0" for write
|
726 |
|
|
reg ocal_num_samples_inc; //1 read/write is done
|
727 |
|
|
reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen
|
728 |
|
|
|
729 |
|
|
reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining
|
730 |
|
|
reg prech_done_r1, prech_done_r2, prech_done_r3;
|
731 |
|
|
reg mask_lim_done;
|
732 |
|
|
reg complex_mask_lim_done;
|
733 |
|
|
reg oclkdelay_calib_start_int;
|
734 |
|
|
reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt;
|
735 |
|
|
reg oclkdelay_int_ref_req;
|
736 |
|
|
reg [3:0] ocal_act_wait_cnt;
|
737 |
|
|
reg oclk_calib_resume_level;
|
738 |
|
|
reg ocal_last_byte_done;
|
739 |
|
|
wire mmcm_wr; //MMCM centering write. no CS will be set
|
740 |
|
|
|
741 |
|
|
wire exit_ocal_complex_resume_wait =
|
742 |
|
|
init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume;
|
743 |
|
|
|
744 |
|
|
|
745 |
|
|
|
746 |
|
|
//***************************************************************************
|
747 |
|
|
// Debug
|
748 |
|
|
//***************************************************************************
|
749 |
|
|
|
750 |
|
|
//synthesis translate_off
|
751 |
|
|
always @(posedge mem_init_done_r) begin
|
752 |
|
|
if (!rst)
|
753 |
|
|
$display ("PHY_INIT: Memory Initialization completed at %t", $time);
|
754 |
|
|
end
|
755 |
|
|
|
756 |
|
|
always @(posedge wrlvl_done) begin
|
757 |
|
|
if (!rst && (WRLVL == "ON"))
|
758 |
|
|
$display ("PHY_INIT: Write Leveling completed at %t", $time);
|
759 |
|
|
end
|
760 |
|
|
|
761 |
|
|
always @(posedge rdlvl_stg1_done) begin
|
762 |
|
|
if (!rst)
|
763 |
|
|
$display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time);
|
764 |
|
|
end
|
765 |
|
|
|
766 |
|
|
always @(posedge mpr_rdlvl_done) begin
|
767 |
|
|
if (!rst)
|
768 |
|
|
$display ("PHY_INIT: MPR Read Leveling completed at %t", $time);
|
769 |
|
|
end
|
770 |
|
|
|
771 |
|
|
always @(posedge oclkdelay_calib_done) begin
|
772 |
|
|
if (!rst)
|
773 |
|
|
$display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time);
|
774 |
|
|
end
|
775 |
|
|
|
776 |
|
|
always @(posedge pi_calib_done_r1) begin
|
777 |
|
|
if (!rst)
|
778 |
|
|
$display ("PHY_INIT: Phaser_In Phase Locked at %t", $time);
|
779 |
|
|
end
|
780 |
|
|
|
781 |
|
|
always @(posedge pi_dqs_found_done) begin
|
782 |
|
|
if (!rst)
|
783 |
|
|
$display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time);
|
784 |
|
|
end
|
785 |
|
|
|
786 |
|
|
always @(posedge wrcal_done) begin
|
787 |
|
|
if (!rst && (WRLVL == "ON"))
|
788 |
|
|
$display ("PHY_INIT: Write Calibration completed at %t", $time);
|
789 |
|
|
end
|
790 |
|
|
|
791 |
|
|
always@(posedge prbs_rdlvl_done)begin
|
792 |
|
|
if(!rst)
|
793 |
|
|
$display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time);
|
794 |
|
|
end
|
795 |
|
|
|
796 |
|
|
|
797 |
|
|
always@(posedge complex_oclkdelay_calib_done)begin
|
798 |
|
|
if(!rst)
|
799 |
|
|
$display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time);
|
800 |
|
|
end
|
801 |
|
|
always@(posedge oclkdelay_center_calib_done)begin
|
802 |
|
|
if(!rst)
|
803 |
|
|
$display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time);
|
804 |
|
|
end
|
805 |
|
|
|
806 |
|
|
//synthesis translate_on
|
807 |
|
|
|
808 |
|
|
assign dbg_phy_init[5:0] = init_state_r;
|
809 |
|
|
assign dbg_phy_init[6+:8] = complex_row_cnt;
|
810 |
|
|
assign dbg_phy_init[14+:3] = victim_sel;
|
811 |
|
|
assign dbg_phy_init[17+:4] = victim_byte_cnt;
|
812 |
|
|
assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0];
|
813 |
|
|
assign dbg_phy_init[30+:15] = complex_address;
|
814 |
|
|
assign dbg_phy_init[(30+15)+:15] = phy_address[14:0];
|
815 |
|
|
assign dbg_phy_init[60] =prbs_rdlvl_prech_req ;
|
816 |
|
|
assign dbg_phy_init[61] =prech_req_posedge_r ;
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
//***************************************************************************
|
820 |
|
|
// DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage
|
821 |
|
|
//***************************************************************************
|
822 |
|
|
|
823 |
|
|
// assign pi_phaselock_calib_cnt = dqs_cnt_r;
|
824 |
|
|
|
825 |
|
|
assign pi_calib_done = pi_calib_done_r1;
|
826 |
|
|
|
827 |
|
|
assign read_pause_ext = read_pause | read_pause_r2;
|
828 |
|
|
|
829 |
|
|
//detect rising edge of prbs_rdlvl_done to reset all control sighals
|
830 |
|
|
always @ (posedge clk) begin
|
831 |
|
|
prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1;
|
832 |
|
|
end
|
833 |
|
|
|
834 |
|
|
always @ (posedge clk) begin
|
835 |
|
|
read_pause_r1 <= #TCQ read_pause;
|
836 |
|
|
read_pause_r2 <= #TCQ read_pause_r1;
|
837 |
|
|
end
|
838 |
|
|
|
839 |
|
|
always @(posedge clk) begin
|
840 |
|
|
if (rst)
|
841 |
|
|
wrcal_final_chk <= #TCQ 1'b0;
|
842 |
|
|
else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done &&
|
843 |
|
|
(DRAM_TYPE == "DDR3"))
|
844 |
|
|
wrcal_final_chk <= #TCQ 1'b1;
|
845 |
|
|
end
|
846 |
|
|
|
847 |
|
|
always @(posedge clk) begin
|
848 |
|
|
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
|
849 |
|
|
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
|
850 |
|
|
prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1;
|
851 |
|
|
prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2;
|
852 |
|
|
wrcal_resume_r <= #TCQ wrcal_resume;
|
853 |
|
|
wrcal_sanity_chk <= #TCQ wrcal_final_chk;
|
854 |
|
|
end
|
855 |
|
|
|
856 |
|
|
always @(posedge clk) begin
|
857 |
|
|
if (rst)
|
858 |
|
|
mpr_end_if_reset <= #TCQ 1'b0;
|
859 |
|
|
else if (mpr_last_byte_done && (num_refresh != 'd0))
|
860 |
|
|
mpr_end_if_reset <= #TCQ 1'b1;
|
861 |
|
|
else
|
862 |
|
|
mpr_end_if_reset <= #TCQ 1'b0;
|
863 |
|
|
end
|
864 |
|
|
|
865 |
|
|
// Siganl to mask memory model error for Invalid latching edge
|
866 |
|
|
|
867 |
|
|
always @(posedge clk)
|
868 |
|
|
if (rst)
|
869 |
|
|
calib_writes <= #TCQ 1'b0;
|
870 |
|
|
else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||
|
871 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
872 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
873 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
|
874 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
875 |
|
|
(init_state_r == INIT_WRCAL_WRITE_READ))
|
876 |
|
|
calib_writes <= #TCQ 1'b1;
|
877 |
|
|
else
|
878 |
|
|
calib_writes <= #TCQ 1'b0;
|
879 |
|
|
|
880 |
|
|
always @(posedge clk)
|
881 |
|
|
if (rst)
|
882 |
|
|
wrcal_rd_wait <= #TCQ 1'b0;
|
883 |
|
|
else if (init_state_r == INIT_WRCAL_READ_WAIT)
|
884 |
|
|
wrcal_rd_wait <= #TCQ 1'b1;
|
885 |
|
|
else
|
886 |
|
|
wrcal_rd_wait <= #TCQ 1'b0;
|
887 |
|
|
|
888 |
|
|
//***************************************************************************
|
889 |
|
|
// Signal PHY completion when calibration is finished
|
890 |
|
|
// Signal assertion is delayed by four clock cycles to account for the
|
891 |
|
|
// multi cycle path constraint to (phy_init_data_sel) signal.
|
892 |
|
|
//***************************************************************************
|
893 |
|
|
|
894 |
|
|
always @(posedge clk)
|
895 |
|
|
if (rst) begin
|
896 |
|
|
init_complete_r <= #TCQ 1'b0;
|
897 |
|
|
init_complete_r_timing <= #TCQ 1'b0;
|
898 |
|
|
init_complete_r1 <= #TCQ 1'b0;
|
899 |
|
|
init_complete_r1_timing <= #TCQ 1'b0;
|
900 |
|
|
init_complete_r2 <= #TCQ 1'b0;
|
901 |
|
|
init_calib_complete <= #TCQ 1'b0;
|
902 |
|
|
end else begin
|
903 |
|
|
if (init_state_r == INIT_DONE) begin
|
904 |
|
|
init_complete_r <= #TCQ 1'b1;
|
905 |
|
|
init_complete_r_timing <= #TCQ 1'b1;
|
906 |
|
|
end
|
907 |
|
|
init_complete_r1 <= #TCQ init_complete_r;
|
908 |
|
|
init_complete_r1_timing <= #TCQ init_complete_r_timing;
|
909 |
|
|
init_complete_r2 <= #TCQ init_complete_r1;
|
910 |
|
|
init_calib_complete <= #TCQ init_complete_r2;
|
911 |
|
|
end
|
912 |
|
|
|
913 |
|
|
always @ (posedge clk)
|
914 |
|
|
if (rst)
|
915 |
|
|
complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0;
|
916 |
|
|
else
|
917 |
|
|
complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done;
|
918 |
|
|
|
919 |
|
|
//reset read address for starting complex ocaldealy calib
|
920 |
|
|
always @ (posedge clk) begin
|
921 |
|
|
complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r);
|
922 |
|
|
|
923 |
|
|
end
|
924 |
|
|
|
925 |
|
|
//first write for complex oclkdealy calib
|
926 |
|
|
always @ (posedge clk) begin
|
927 |
|
|
if (rst)
|
928 |
|
|
complex_ocal_wr_start <= #TCQ 'b0;
|
929 |
|
|
else
|
930 |
|
|
complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start;
|
931 |
|
|
end
|
932 |
|
|
|
933 |
|
|
//ocal stg3 centering start
|
934 |
|
|
// always @ (posedge clk)
|
935 |
|
|
// if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0;
|
936 |
|
|
// else
|
937 |
|
|
// oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start;
|
938 |
|
|
|
939 |
|
|
//***************************************************************************
|
940 |
|
|
// Instantiate FF for the phy_init_data_sel signal. A multi cycle path
|
941 |
|
|
// constraint will be assigned to this signal. This signal will only be
|
942 |
|
|
// used within the PHY
|
943 |
|
|
//***************************************************************************
|
944 |
|
|
|
945 |
|
|
// FDRSE u_ff_phy_init_data_sel
|
946 |
|
|
// (
|
947 |
|
|
// .Q (phy_init_data_sel),
|
948 |
|
|
// .C (clk),
|
949 |
|
|
// .CE (1'b1),
|
950 |
|
|
// .D (init_complete_r),
|
951 |
|
|
// .R (1'b0),
|
952 |
|
|
// .S (1'b0)
|
953 |
|
|
// ) /* synthesis syn_preserve=1 */
|
954 |
|
|
// /* synthesis syn_replicate = 0 */;
|
955 |
|
|
|
956 |
|
|
|
957 |
|
|
//***************************************************************************
|
958 |
|
|
// Mode register programming
|
959 |
|
|
//***************************************************************************
|
960 |
|
|
|
961 |
|
|
//*****************************************************************
|
962 |
|
|
// DDR3 Load mode reg0
|
963 |
|
|
// Mode Register (MR0):
|
964 |
|
|
// [15:13] - unused - 000
|
965 |
|
|
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
|
966 |
|
|
// 1 (DLL maintained)
|
967 |
|
|
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
|
968 |
|
|
// [8] - DLL reset - 0 or 1
|
969 |
|
|
// [7] - Test Mode - 0 (normal)
|
970 |
|
|
// [6:4],[2] - CAS latency - CAS_LAT
|
971 |
|
|
// [3] - Burst Type - BURST_TYPE
|
972 |
|
|
// [1:0] - Burst Length - BURST_LEN
|
973 |
|
|
// DDR2 Load mode register
|
974 |
|
|
// Mode Register (MR):
|
975 |
|
|
// [15:14] - unused - 00
|
976 |
|
|
// [13] - reserved - 0
|
977 |
|
|
// [12] - Power-down mode - 0 (normal)
|
978 |
|
|
// [11:9] - write recovery - write recovery for Auto Precharge
|
979 |
|
|
// (tWR/tCK = 6)
|
980 |
|
|
// [8] - DLL reset - 0 or 1
|
981 |
|
|
// [7] - Test Mode - 0 (normal)
|
982 |
|
|
// [6:4] - CAS latency - CAS_LAT
|
983 |
|
|
// [3] - Burst Type - BURST_TYPE
|
984 |
|
|
// [2:0] - Burst Length - BURST_LEN
|
985 |
|
|
|
986 |
|
|
//*****************************************************************
|
987 |
|
|
generate
|
988 |
|
|
if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3
|
989 |
|
|
assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 :
|
990 |
|
|
(BURST_MODE == "OTF") ? 2'b01 :
|
991 |
|
|
(BURST_MODE == "4") ? 2'b10 : 2'b11;
|
992 |
|
|
assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency
|
993 |
|
|
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
|
994 |
|
|
assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 :
|
995 |
|
|
((nCL == 6) || (nCL == 14)) ? 3'b010 :
|
996 |
|
|
(nCL == 7) ? 3'b011 :
|
997 |
|
|
(nCL == 8) ? 3'b100 :
|
998 |
|
|
(nCL == 9) ? 3'b101 :
|
999 |
|
|
(nCL == 10) ? 3'b110 :
|
1000 |
|
|
(nCL == 11) ? 3'b111 :
|
1001 |
|
|
(nCL == 12) ? 3'b000 : 3'b111;
|
1002 |
|
|
assign load_mr0[7] = 1'b0;
|
1003 |
|
|
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
|
1004 |
|
|
assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :
|
1005 |
|
|
(TWR_CYC == 6) ? 3'b010 :
|
1006 |
|
|
(TWR_CYC == 7) ? 3'b011 :
|
1007 |
|
|
(TWR_CYC == 8) ? 3'b100 :
|
1008 |
|
|
(TWR_CYC == 9) ? 3'b101 :
|
1009 |
|
|
(TWR_CYC == 10) ? 3'b101 :
|
1010 |
|
|
(TWR_CYC == 11) ? 3'b110 :
|
1011 |
|
|
(TWR_CYC == 12) ? 3'b110 :
|
1012 |
|
|
(TWR_CYC == 13) ? 3'b111 :
|
1013 |
|
|
(TWR_CYC == 14) ? 3'b111 :
|
1014 |
|
|
(TWR_CYC == 15) ? 3'b000 :
|
1015 |
|
|
(TWR_CYC == 16) ? 3'b000 : 3'b010;
|
1016 |
|
|
assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'
|
1017 |
|
|
assign load_mr0[15:13] = 3'b000;
|
1018 |
|
|
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen
|
1019 |
|
|
assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 :
|
1020 |
|
|
(BURST_MODE == "4") ? 3'b010 : 3'b111;
|
1021 |
|
|
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
|
1022 |
|
|
assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :
|
1023 |
|
|
(nCL == 4) ? 3'b100 :
|
1024 |
|
|
(nCL == 5) ? 3'b101 :
|
1025 |
|
|
(nCL == 6) ? 3'b110 : 3'b111;
|
1026 |
|
|
assign load_mr0[7] = 1'b0;
|
1027 |
|
|
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
|
1028 |
|
|
assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :
|
1029 |
|
|
(TWR_CYC == 3) ? 3'b010 :
|
1030 |
|
|
(TWR_CYC == 4) ? 3'b011 :
|
1031 |
|
|
(TWR_CYC == 5) ? 3'b100 :
|
1032 |
|
|
(TWR_CYC == 6) ? 3'b101 : 3'b010;
|
1033 |
|
|
assign load_mr0[15:12]= 4'b0000; // Reserved
|
1034 |
|
|
end
|
1035 |
|
|
endgenerate
|
1036 |
|
|
|
1037 |
|
|
//*****************************************************************
|
1038 |
|
|
// DDR3 Load mode reg1
|
1039 |
|
|
// Mode Register (MR1):
|
1040 |
|
|
// [15:13] - unused - 00
|
1041 |
|
|
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
|
1042 |
|
|
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
|
1043 |
|
|
// [10] - reserved - 0 (must be '0')
|
1044 |
|
|
// [9] - RTT[2] - 0
|
1045 |
|
|
// [8] - reserved - 0 (must be '0')
|
1046 |
|
|
// [7] - write leveling - 0 (disabled), 1 (enabled)
|
1047 |
|
|
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
|
1048 |
|
|
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
|
1049 |
|
|
// [4:3] - Additive CAS - ADDITIVE_CAS
|
1050 |
|
|
// [2] - RTT[0]
|
1051 |
|
|
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
|
1052 |
|
|
// [0] - DLL enable - 0 (normal)
|
1053 |
|
|
// DDR2 ext mode register
|
1054 |
|
|
// Extended Mode Register (MR):
|
1055 |
|
|
// [15:14] - unused - 00
|
1056 |
|
|
// [13] - reserved - 0
|
1057 |
|
|
// [12] - output enable - 0 (enabled)
|
1058 |
|
|
// [11] - RDQS enable - 0 (disabled)
|
1059 |
|
|
// [10] - DQS# enable - 0 (enabled)
|
1060 |
|
|
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
|
1061 |
|
|
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
|
1062 |
|
|
// [5:3] - Additive CAS - ADDITIVE_CAS
|
1063 |
|
|
// [2] - RTT[0]
|
1064 |
|
|
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
|
1065 |
|
|
// [0] - DLL enable - 0 (normal)
|
1066 |
|
|
//*****************************************************************
|
1067 |
|
|
|
1068 |
|
|
generate
|
1069 |
|
|
if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3
|
1070 |
|
|
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
|
1071 |
|
|
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1;
|
1072 |
|
|
assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") ||
|
1073 |
|
|
(RTT_NOM_int == "60")) ? 1'b1 : 1'b0;
|
1074 |
|
|
assign load_mr1[4:3] = (AL == "0") ? 2'b00 :
|
1075 |
|
|
(AL == "CL-1") ? 2'b01 :
|
1076 |
|
|
(AL == "CL-2") ? 2'b10 : 2'b11;
|
1077 |
|
|
assign load_mr1[5] = 1'b0;
|
1078 |
|
|
assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ?
|
1079 |
|
|
1'b1 : 1'b0;
|
1080 |
|
|
assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence
|
1081 |
|
|
assign load_mr1[8] = 1'b0;
|
1082 |
|
|
assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ?
|
1083 |
|
|
1'b1 : 1'b0;
|
1084 |
|
|
assign load_mr1[10] = 1'b0;
|
1085 |
|
|
assign load_mr1[15:11] = 5'b00000;
|
1086 |
|
|
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2
|
1087 |
|
|
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
|
1088 |
|
|
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0;
|
1089 |
|
|
assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ?
|
1090 |
|
|
1'b1 : 1'b0;
|
1091 |
|
|
assign load_mr1[5:3] = (AL == "0") ? 3'b000 :
|
1092 |
|
|
(AL == "1") ? 3'b001 :
|
1093 |
|
|
(AL == "2") ? 3'b010 :
|
1094 |
|
|
(AL == "3") ? 3'b011 :
|
1095 |
|
|
(AL == "4") ? 3'b100 : 3'b111;
|
1096 |
|
|
assign load_mr1[6] = ((RTT_NOM_int == "50") ||
|
1097 |
|
|
(RTT_NOM_int == "150")) ? 1'b1 : 1'b0;
|
1098 |
|
|
assign load_mr1[9:7] = 3'b000;
|
1099 |
|
|
assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1;
|
1100 |
|
|
assign load_mr1[15:11] = 5'b00000;
|
1101 |
|
|
|
1102 |
|
|
end
|
1103 |
|
|
endgenerate
|
1104 |
|
|
|
1105 |
|
|
//*****************************************************************
|
1106 |
|
|
// DDR3 Load mode reg2
|
1107 |
|
|
// Mode Register (MR2):
|
1108 |
|
|
// [15:11] - unused - 00
|
1109 |
|
|
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
|
1110 |
|
|
// [8] - reserved - 0 (must be '0')
|
1111 |
|
|
// [7] - self-refresh temperature range -
|
1112 |
|
|
// 0 (normal), 1 (extended)
|
1113 |
|
|
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
|
1114 |
|
|
// [5:3] - CAS Write Latency (CWL) -
|
1115 |
|
|
// 000 (5 for 400 MHz device),
|
1116 |
|
|
// 001 (6 for 400 MHz to 533 MHz devices),
|
1117 |
|
|
// 010 (7 for 533 MHz to 667 MHz devices),
|
1118 |
|
|
// 011 (8 for 667 MHz to 800 MHz)
|
1119 |
|
|
// [2:0] - Partial Array Self-Refresh (Optional) -
|
1120 |
|
|
// 000 (full array)
|
1121 |
|
|
// Not used for DDR2
|
1122 |
|
|
//*****************************************************************
|
1123 |
|
|
generate
|
1124 |
|
|
if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3
|
1125 |
|
|
assign load_mr2[2:0] = 3'b000;
|
1126 |
|
|
assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :
|
1127 |
|
|
(nCWL == 6) ? 3'b001 :
|
1128 |
|
|
(nCWL == 7) ? 3'b010 :
|
1129 |
|
|
(nCWL == 8) ? 3'b011 :
|
1130 |
|
|
(nCWL == 9) ? 3'b100 :
|
1131 |
|
|
(nCWL == 10) ? 3'b101 :
|
1132 |
|
|
(nCWL == 11) ? 3'b110 : 3'b111;
|
1133 |
|
|
assign load_mr2[6] = 1'b0;
|
1134 |
|
|
assign load_mr2[7] = 1'b0;
|
1135 |
|
|
assign load_mr2[8] = 1'b0;
|
1136 |
|
|
// Dynamic ODT disabled
|
1137 |
|
|
assign load_mr2[10:9] = 2'b00;
|
1138 |
|
|
assign load_mr2[15:11] = 5'b00000;
|
1139 |
|
|
end else begin: gen_load_mr2_DDR2
|
1140 |
|
|
assign load_mr2[15:0] = 16'd0;
|
1141 |
|
|
end
|
1142 |
|
|
endgenerate
|
1143 |
|
|
|
1144 |
|
|
//*****************************************************************
|
1145 |
|
|
// DDR3 Load mode reg3
|
1146 |
|
|
// Mode Register (MR3):
|
1147 |
|
|
// [15:3] - unused - All zeros
|
1148 |
|
|
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
|
1149 |
|
|
// [1:0] - MPR location - 00 (Predefined pattern)
|
1150 |
|
|
//*****************************************************************
|
1151 |
|
|
|
1152 |
|
|
assign load_mr3[1:0] = 2'b00;
|
1153 |
|
|
assign load_mr3[2] = 1'b0;
|
1154 |
|
|
assign load_mr3[15:3] = 13'b0000000000000;
|
1155 |
|
|
|
1156 |
|
|
// For multi-rank systems the rank being accessed during writes in
|
1157 |
|
|
// Read Leveling must be sent to phy_write for the bitslip logic
|
1158 |
|
|
assign calib_rank_cnt = chip_cnt_r;
|
1159 |
|
|
|
1160 |
|
|
//***************************************************************************
|
1161 |
|
|
// Logic to begin initial calibration, and to handle precharge requests
|
1162 |
|
|
// during read-leveling (to avoid tRAS violations if individual read
|
1163 |
|
|
// levelling calibration stages take more than max{tRAS) to complete).
|
1164 |
|
|
//***************************************************************************
|
1165 |
|
|
|
1166 |
|
|
// Assert when readback for each stage of read-leveling begins. However,
|
1167 |
|
|
// note this indicates only when the read command is issued and when
|
1168 |
|
|
// Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not
|
1169 |
|
|
// indicate when the read data is present on the bus (when this happens
|
1170 |
|
|
// after the read command is issued depends on CAS LATENCY) - there will
|
1171 |
|
|
// need to be some delay before valid data is present on the bus.
|
1172 |
|
|
// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS);
|
1173 |
|
|
|
1174 |
|
|
// Assert when read back for oclkdelay calibration begins
|
1175 |
|
|
assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ);
|
1176 |
|
|
|
1177 |
|
|
// Assert when read back for write calibration begins
|
1178 |
|
|
assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS);
|
1179 |
|
|
|
1180 |
|
|
// Common precharge signal done signal - pulses only when there has been
|
1181 |
|
|
// a precharge issued as a result of a PRECH_REQ pulse. Note also a common
|
1182 |
|
|
// PRECH_DONE signal is used for all blocks
|
1183 |
|
|
assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
|
1184 |
|
|
((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) ||
|
1185 |
|
|
(dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||
|
1186 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
1187 |
|
|
((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) ||
|
1188 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
1189 |
|
|
((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) ||
|
1190 |
|
|
((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) ||
|
1191 |
|
|
((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done
|
1192 |
|
|
(wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) &&
|
1193 |
|
|
prech_pending_r &&
|
1194 |
|
|
!prech_req_posedge_r);
|
1195 |
|
|
|
1196 |
|
|
always @(posedge clk)
|
1197 |
|
|
if (rst)
|
1198 |
|
|
pi_phaselock_start <= #TCQ 1'b0;
|
1199 |
|
|
else if (init_state_r == INIT_PI_PHASELOCK_READS)
|
1200 |
|
|
pi_phaselock_start <= #TCQ 1'b1;
|
1201 |
|
|
|
1202 |
|
|
// Delay start of each calibration by 16 clock cycles to ensure that when
|
1203 |
|
|
// calibration logic begins, read data is already appearing on the bus.
|
1204 |
|
|
// Each circuit should synthesize using an SRL16. Assume that reset is
|
1205 |
|
|
// long enough to clear contents of SRL16.
|
1206 |
|
|
always @(posedge clk) begin
|
1207 |
|
|
rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done;
|
1208 |
|
|
prbs_last_byte_done_r <= #TCQ prbs_last_byte_done;
|
1209 |
|
|
rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0],
|
1210 |
|
|
rdlvl_start_pre};
|
1211 |
|
|
wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0],
|
1212 |
|
|
wrcal_start_pre};
|
1213 |
|
|
oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0],
|
1214 |
|
|
oclkdelay_calib_start_pre};
|
1215 |
|
|
prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0],
|
1216 |
|
|
prech_done_pre};
|
1217 |
|
|
end
|
1218 |
|
|
|
1219 |
|
|
always @(posedge clk)
|
1220 |
|
|
if (rst)
|
1221 |
|
|
oclkdelay_calib_start_int <= #TCQ 1'b0;
|
1222 |
|
|
else if (oclkdelay_start_dly_r[5])
|
1223 |
|
|
oclkdelay_calib_start_int <= #TCQ 1'b1;
|
1224 |
|
|
|
1225 |
|
|
always @(posedge clk) begin
|
1226 |
|
|
if (rst)
|
1227 |
|
|
ocal_last_byte_done <= #TCQ 1'b0;
|
1228 |
|
|
else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done)
|
1229 |
|
|
ocal_last_byte_done <= #TCQ 1'b1;
|
1230 |
|
|
end
|
1231 |
|
|
|
1232 |
|
|
always @(posedge clk) begin
|
1233 |
|
|
if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done)
|
1234 |
|
|
oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER;
|
1235 |
|
|
else if (oclkdelay_calib_start_int) begin
|
1236 |
|
|
if (oclkdelay_ref_cnt > 'd0)
|
1237 |
|
|
oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1;
|
1238 |
|
|
else
|
1239 |
|
|
oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER;
|
1240 |
|
|
end
|
1241 |
|
|
end
|
1242 |
|
|
|
1243 |
|
|
always @(posedge clk) begin
|
1244 |
|
|
if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done)
|
1245 |
|
|
oclkdelay_int_ref_req <= #TCQ 1'b0;
|
1246 |
|
|
else if (oclkdelay_ref_cnt == 'd1)
|
1247 |
|
|
oclkdelay_int_ref_req <= #TCQ 1'b1;
|
1248 |
|
|
end
|
1249 |
|
|
|
1250 |
|
|
always @(posedge clk) begin
|
1251 |
|
|
if (rst)
|
1252 |
|
|
ocal_act_wait_cnt <= #TCQ 'd0;
|
1253 |
|
|
else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15)
|
1254 |
|
|
ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1;
|
1255 |
|
|
else
|
1256 |
|
|
ocal_act_wait_cnt <= #TCQ 'd0;
|
1257 |
|
|
end
|
1258 |
|
|
|
1259 |
|
|
always @(posedge clk) begin
|
1260 |
|
|
if (rst || (init_state_r == INIT_OCLKDELAY_READ))
|
1261 |
|
|
oclk_calib_resume_level <= #TCQ 1'b0;
|
1262 |
|
|
else if (oclk_calib_resume)
|
1263 |
|
|
oclk_calib_resume_level <= #TCQ 1'b1;
|
1264 |
|
|
end
|
1265 |
|
|
|
1266 |
|
|
always @(posedge clk) begin
|
1267 |
|
|
if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done)
|
1268 |
|
|
complex_rdlvl_int_ref_req <= #TCQ 1'b0;
|
1269 |
|
|
else if (oclkdelay_ref_cnt == 'd1)
|
1270 |
|
|
// complex_rdlvl_int_ref_req <= #TCQ 1'b1;
|
1271 |
|
|
complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue
|
1272 |
|
|
end
|
1273 |
|
|
|
1274 |
|
|
always @(posedge clk) begin
|
1275 |
|
|
if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ))
|
1276 |
|
|
ext_int_ref_req <= #TCQ 1'b0;
|
1277 |
|
|
else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req)
|
1278 |
|
|
ext_int_ref_req <= #TCQ 1'b1;
|
1279 |
|
|
end
|
1280 |
|
|
|
1281 |
|
|
|
1282 |
|
|
always @(posedge clk) begin
|
1283 |
|
|
prech_done <= #TCQ prech_done_dly_r[15];
|
1284 |
|
|
prech_done_r1 <= #TCQ prech_done_dly_r[15];
|
1285 |
|
|
prech_done_r2 <= #TCQ prech_done_r1;
|
1286 |
|
|
prech_done_r3 <= #TCQ prech_done_r2;
|
1287 |
|
|
end
|
1288 |
|
|
|
1289 |
|
|
|
1290 |
|
|
always @(posedge clk)
|
1291 |
|
|
if (rst)
|
1292 |
|
|
mpr_rdlvl_start <= #TCQ 1'b0;
|
1293 |
|
|
else if (pi_dqs_found_done &&
|
1294 |
|
|
(init_state_r == INIT_MPR_READ))
|
1295 |
|
|
mpr_rdlvl_start <= #TCQ 1'b1;
|
1296 |
|
|
|
1297 |
|
|
always @(posedge clk)
|
1298 |
|
|
phy_if_empty_r <= #TCQ phy_if_empty;
|
1299 |
|
|
|
1300 |
|
|
always @(posedge clk)
|
1301 |
|
|
if (rst ||
|
1302 |
|
|
((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done)
|
1303 |
|
|
prbs_gen_clk_en <= #TCQ 1'b0;
|
1304 |
|
|
else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) ||
|
1305 |
|
|
((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) ||
|
1306 |
|
|
((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14))
|
1307 |
|
|
|| (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start))
|
1308 |
|
|
prbs_gen_clk_en <= #TCQ 1'b1;
|
1309 |
|
|
|
1310 |
|
|
//Enable for complex oclkdelay - used in prbs gen
|
1311 |
|
|
always @(posedge clk)
|
1312 |
|
|
if (rst ||
|
1313 |
|
|
((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done ||
|
1314 |
|
|
(complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) ||
|
1315 |
|
|
( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start ||
|
1316 |
|
|
(complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) ||
|
1317 |
|
|
(init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) ||
|
1318 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT))
|
1319 |
|
|
prbs_gen_oclk_clk_en <= #TCQ 1'b0;
|
1320 |
|
|
else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26
|
1321 |
|
|
((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) ||
|
1322 |
|
|
((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) ||
|
1323 |
|
|
exit_ocal_complex_resume_wait ||
|
1324 |
|
|
((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14))
|
1325 |
|
|
|| (init_state_r == INIT_RDLVL_COMPLEX_READ) )
|
1326 |
|
|
prbs_gen_oclk_clk_en <= #TCQ 1'b1;
|
1327 |
|
|
|
1328 |
|
|
generate
|
1329 |
|
|
if (RANKS < 2) begin
|
1330 |
|
|
always @(posedge clk)
|
1331 |
|
|
if (rst) begin
|
1332 |
|
|
rdlvl_stg1_start <= #TCQ 1'b0;
|
1333 |
|
|
rdlvl_stg1_start_int <= #TCQ 1'b0;
|
1334 |
|
|
rdlvl_start_pre <= #TCQ 1'b0;
|
1335 |
|
|
prbs_rdlvl_start <= #TCQ 1'b0;
|
1336 |
|
|
end else begin
|
1337 |
|
|
if (pi_dqs_found_done && cnt_cmd_done_r &&
|
1338 |
|
|
(init_state_r == INIT_RDLVL_ACT_WAIT))
|
1339 |
|
|
rdlvl_stg1_start_int <= #TCQ 1'b1;
|
1340 |
|
|
if (pi_dqs_found_done &&
|
1341 |
|
|
(init_state_r == INIT_RDLVL_STG1_READ))begin
|
1342 |
|
|
rdlvl_start_pre <= #TCQ 1'b1;
|
1343 |
|
|
rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];
|
1344 |
|
|
end
|
1345 |
|
|
if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done &&
|
1346 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin
|
1347 |
|
|
prbs_rdlvl_start <= #TCQ 1'b1;
|
1348 |
|
|
end
|
1349 |
|
|
end
|
1350 |
|
|
end else begin
|
1351 |
|
|
always @(posedge clk)
|
1352 |
|
|
if (rst || rdlvl_stg1_rank_done) begin
|
1353 |
|
|
rdlvl_stg1_start <= #TCQ 1'b0;
|
1354 |
|
|
rdlvl_stg1_start_int <= #TCQ 1'b0;
|
1355 |
|
|
rdlvl_start_pre <= #TCQ 1'b0;
|
1356 |
|
|
prbs_rdlvl_start <= #TCQ 1'b0;
|
1357 |
|
|
end else begin
|
1358 |
|
|
if (pi_dqs_found_done && cnt_cmd_done_r &&
|
1359 |
|
|
(init_state_r == INIT_RDLVL_ACT_WAIT))
|
1360 |
|
|
rdlvl_stg1_start_int <= #TCQ 1'b1;
|
1361 |
|
|
if (pi_dqs_found_done &&
|
1362 |
|
|
(init_state_r == INIT_RDLVL_STG1_READ))begin
|
1363 |
|
|
rdlvl_start_pre <= #TCQ 1'b1;
|
1364 |
|
|
rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];
|
1365 |
|
|
end
|
1366 |
|
|
if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done &&
|
1367 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin
|
1368 |
|
|
prbs_rdlvl_start <= #TCQ 1'b1;
|
1369 |
|
|
end
|
1370 |
|
|
end
|
1371 |
|
|
end
|
1372 |
|
|
endgenerate
|
1373 |
|
|
|
1374 |
|
|
|
1375 |
|
|
always @(posedge clk) begin
|
1376 |
|
|
if (rst || dqsfound_retry || wrlvl_byte_redo) begin
|
1377 |
|
|
pi_dqs_found_start <= #TCQ 1'b0;
|
1378 |
|
|
wrcal_start <= #TCQ 1'b0;
|
1379 |
|
|
end else begin
|
1380 |
|
|
if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ)
|
1381 |
|
|
pi_dqs_found_start <= #TCQ 1'b1;
|
1382 |
|
|
if (wrcal_start_dly_r[5])
|
1383 |
|
|
wrcal_start <= #TCQ 1'b1;
|
1384 |
|
|
end
|
1385 |
|
|
end // else: !if(rst)
|
1386 |
|
|
|
1387 |
|
|
|
1388 |
|
|
always @(posedge clk)
|
1389 |
|
|
if (rst)
|
1390 |
|
|
oclkdelay_calib_start <= #TCQ 1'b0;
|
1391 |
|
|
else if (oclkdelay_start_dly_r[5])
|
1392 |
|
|
oclkdelay_calib_start <= #TCQ 1'b1;
|
1393 |
|
|
|
1394 |
|
|
always @(posedge clk)
|
1395 |
|
|
if (rst)
|
1396 |
|
|
pi_dqs_found_done_r1 <= #TCQ 1'b0;
|
1397 |
|
|
else
|
1398 |
|
|
pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done;
|
1399 |
|
|
|
1400 |
|
|
|
1401 |
|
|
always @(posedge clk)
|
1402 |
|
|
wrlvl_final_r <= #TCQ wrlvl_final;
|
1403 |
|
|
|
1404 |
|
|
// Reset IN_FIFO after final write leveling to make sure the FIFO
|
1405 |
|
|
// pointers are initialized
|
1406 |
|
|
always @(posedge clk)
|
1407 |
|
|
if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH))
|
1408 |
|
|
wrlvl_final_if_rst <= #TCQ 1'b0;
|
1409 |
|
|
else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r &&
|
1410 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2))
|
1411 |
|
|
wrlvl_final_if_rst <= #TCQ 1'b1;
|
1412 |
|
|
|
1413 |
|
|
// Constantly enable DQS while write leveling is enabled in the memory
|
1414 |
|
|
// This is more to get rid of warnings in simulation, can later change
|
1415 |
|
|
// this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted
|
1416 |
|
|
|
1417 |
|
|
always @(posedge clk)
|
1418 |
|
|
if (rst ||
|
1419 |
|
|
((init_state_r1 != INIT_WRLVL_START) &&
|
1420 |
|
|
(init_state_r == INIT_WRLVL_START)))
|
1421 |
|
|
wrlvl_odt_ctl <= #TCQ 1'b0;
|
1422 |
|
|
else if (wrlvl_rank_done && ~wrlvl_rank_done_r1)
|
1423 |
|
|
wrlvl_odt_ctl <= #TCQ 1'b1;
|
1424 |
|
|
|
1425 |
|
|
generate
|
1426 |
|
|
if (nCK_PER_CLK == 4) begin: en_cnt_div4
|
1427 |
|
|
always @ (posedge clk)
|
1428 |
|
|
if (rst)
|
1429 |
|
|
enable_wrlvl_cnt <= #TCQ 5'd0;
|
1430 |
|
|
else if ((init_state_r == INIT_WRLVL_START) ||
|
1431 |
|
|
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
|
1432 |
|
|
enable_wrlvl_cnt <= #TCQ 5'd12;
|
1433 |
|
|
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
|
1434 |
|
|
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
|
1435 |
|
|
|
1436 |
|
|
// ODT stays asserted as long as write_calib
|
1437 |
|
|
// signal is asserted
|
1438 |
|
|
always @(posedge clk)
|
1439 |
|
|
if (rst || wrlvl_odt_ctl)
|
1440 |
|
|
wrlvl_odt <= #TCQ 1'b0;
|
1441 |
|
|
else if (enable_wrlvl_cnt == 5'd1)
|
1442 |
|
|
wrlvl_odt <= #TCQ 1'b1;
|
1443 |
|
|
|
1444 |
|
|
end else begin: en_cnt_div2
|
1445 |
|
|
always @ (posedge clk)
|
1446 |
|
|
if (rst)
|
1447 |
|
|
enable_wrlvl_cnt <= #TCQ 5'd0;
|
1448 |
|
|
else if ((init_state_r == INIT_WRLVL_START) ||
|
1449 |
|
|
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
|
1450 |
|
|
enable_wrlvl_cnt <= #TCQ 5'd21;
|
1451 |
|
|
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
|
1452 |
|
|
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
|
1453 |
|
|
|
1454 |
|
|
// ODT stays asserted as long as write_calib
|
1455 |
|
|
// signal is asserted
|
1456 |
|
|
always @(posedge clk)
|
1457 |
|
|
if (rst || wrlvl_odt_ctl)
|
1458 |
|
|
wrlvl_odt <= #TCQ 1'b0;
|
1459 |
|
|
else if (enable_wrlvl_cnt == 5'd1)
|
1460 |
|
|
wrlvl_odt <= #TCQ 1'b1;
|
1461 |
|
|
|
1462 |
|
|
end
|
1463 |
|
|
endgenerate
|
1464 |
|
|
|
1465 |
|
|
always @(posedge clk)
|
1466 |
|
|
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
|
1467 |
|
|
wrlvl_active <= #TCQ 1'b0;
|
1468 |
|
|
else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active)
|
1469 |
|
|
wrlvl_active <= #TCQ 1'b1;
|
1470 |
|
|
|
1471 |
|
|
// signal used to assert DQS for write leveling.
|
1472 |
|
|
// the DQS will be asserted once every 16 clock cycles.
|
1473 |
|
|
always @(posedge clk)begin
|
1474 |
|
|
if(rst || (enable_wrlvl_cnt != 5'd1)) begin
|
1475 |
|
|
wr_level_dqs_asrt <= #TCQ 1'd0;
|
1476 |
|
|
end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin
|
1477 |
|
|
wr_level_dqs_asrt <= #TCQ 1'd1;
|
1478 |
|
|
end
|
1479 |
|
|
end
|
1480 |
|
|
|
1481 |
|
|
always @ (posedge clk) begin
|
1482 |
|
|
if (rst || (wrlvl_done_r && ~wrlvl_done_r1))
|
1483 |
|
|
dqs_asrt_cnt <= #TCQ 2'd0;
|
1484 |
|
|
else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3)
|
1485 |
|
|
dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1);
|
1486 |
|
|
end
|
1487 |
|
|
|
1488 |
|
|
always @ (posedge clk) begin
|
1489 |
|
|
if (rst || ~wrlvl_active)
|
1490 |
|
|
wr_lvl_start <= #TCQ 1'd0;
|
1491 |
|
|
else if (dqs_asrt_cnt == 2'd3)
|
1492 |
|
|
wr_lvl_start <= #TCQ 1'd1;
|
1493 |
|
|
end
|
1494 |
|
|
|
1495 |
|
|
|
1496 |
|
|
always @(posedge clk) begin
|
1497 |
|
|
if (rst)
|
1498 |
|
|
wl_sm_start <= #TCQ 1'b0;
|
1499 |
|
|
else
|
1500 |
|
|
wl_sm_start <= #TCQ wr_level_dqs_asrt_r1;
|
1501 |
|
|
end
|
1502 |
|
|
|
1503 |
|
|
|
1504 |
|
|
always @(posedge clk) begin
|
1505 |
|
|
wrlvl_active_r1 <= #TCQ wrlvl_active;
|
1506 |
|
|
wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt;
|
1507 |
|
|
wrlvl_done_r <= #TCQ wrlvl_done;
|
1508 |
|
|
wrlvl_done_r1 <= #TCQ wrlvl_done_r;
|
1509 |
|
|
wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;
|
1510 |
|
|
wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;
|
1511 |
|
|
wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;
|
1512 |
|
|
wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3;
|
1513 |
|
|
wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4;
|
1514 |
|
|
wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5;
|
1515 |
|
|
wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6;
|
1516 |
|
|
end
|
1517 |
|
|
|
1518 |
|
|
always @ (posedge clk) begin
|
1519 |
|
|
//if (rst)
|
1520 |
|
|
wrlvl_rank_cntr <= #TCQ 3'd0;
|
1521 |
|
|
//else if (wrlvl_rank_done)
|
1522 |
|
|
// wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;
|
1523 |
|
|
end
|
1524 |
|
|
|
1525 |
|
|
//*****************************************************************
|
1526 |
|
|
// Precharge request logic - those calibration logic blocks
|
1527 |
|
|
// that require greater than tRAS(max) to finish must break up
|
1528 |
|
|
// their calibration into smaller units of time, with precharges
|
1529 |
|
|
// issued in between. This is done using the XXX_PRECH_REQ and
|
1530 |
|
|
// PRECH_DONE handshaking between PHY_INIT and those blocks
|
1531 |
|
|
//*****************************************************************
|
1532 |
|
|
|
1533 |
|
|
// Shared request from multiple sources
|
1534 |
|
|
assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req |
|
1535 |
|
|
(dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT));
|
1536 |
|
|
|
1537 |
|
|
// Handshaking logic to force precharge during read leveling, and to
|
1538 |
|
|
// notify read leveling logic when precharge has been initiated and
|
1539 |
|
|
// it's okay to proceed with leveling again
|
1540 |
|
|
always @(posedge clk)
|
1541 |
|
|
if (rst) begin
|
1542 |
|
|
prech_req_r <= #TCQ 1'b0;
|
1543 |
|
|
prech_req_posedge_r <= #TCQ 1'b0;
|
1544 |
|
|
prech_pending_r <= #TCQ 1'b0;
|
1545 |
|
|
end else begin
|
1546 |
|
|
prech_req_r <= #TCQ prech_req;
|
1547 |
|
|
prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;
|
1548 |
|
|
if (prech_req_posedge_r)
|
1549 |
|
|
prech_pending_r <= #TCQ 1'b1;
|
1550 |
|
|
// Clear after we've finished with the precharge and have
|
1551 |
|
|
// returned to issuing read leveling calibration reads
|
1552 |
|
|
else if (prech_done_pre)
|
1553 |
|
|
prech_pending_r <= #TCQ 1'b0;
|
1554 |
|
|
end
|
1555 |
|
|
|
1556 |
|
|
always @(posedge clk) begin
|
1557 |
|
|
if (rst || prech_done_r3)
|
1558 |
|
|
mask_lim_done <= #TCQ 1'b0;
|
1559 |
|
|
else if (prech_pending_r)
|
1560 |
|
|
mask_lim_done <= #TCQ 1'b1;
|
1561 |
|
|
end
|
1562 |
|
|
|
1563 |
|
|
always @(posedge clk) begin
|
1564 |
|
|
if (rst || prbs_rdlvl_done_r3)
|
1565 |
|
|
complex_mask_lim_done <= #TCQ 1'b0;
|
1566 |
|
|
else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int)
|
1567 |
|
|
complex_mask_lim_done <= #TCQ 1'b1;
|
1568 |
|
|
end
|
1569 |
|
|
|
1570 |
|
|
//Complex oclkdelay calibrration
|
1571 |
|
|
|
1572 |
|
|
//***************************************************************************
|
1573 |
|
|
// Various timing counters
|
1574 |
|
|
//***************************************************************************
|
1575 |
|
|
|
1576 |
|
|
//*****************************************************************
|
1577 |
|
|
// Generic delay for various states that require it (e.g. for turnaround
|
1578 |
|
|
// between read and write). Make this a sufficiently large number of clock
|
1579 |
|
|
// cycles to cover all possible frequencies and memory components)
|
1580 |
|
|
// Requirements for this counter:
|
1581 |
|
|
// 1. Greater than tMRD
|
1582 |
|
|
// 2. tRFC (refresh-active) for DDR2
|
1583 |
|
|
// 3. (list the other requirements, slacker...)
|
1584 |
|
|
//*****************************************************************
|
1585 |
|
|
|
1586 |
|
|
always @(posedge clk) begin
|
1587 |
|
|
case (init_state_r)
|
1588 |
|
|
INIT_LOAD_MR_WAIT,
|
1589 |
|
|
INIT_WRLVL_LOAD_MR_WAIT,
|
1590 |
|
|
INIT_WRLVL_LOAD_MR2_WAIT,
|
1591 |
|
|
INIT_MPR_WAIT,
|
1592 |
|
|
INIT_MPR_DISABLE_PREWAIT,
|
1593 |
|
|
INIT_MPR_DISABLE_WAIT,
|
1594 |
|
|
INIT_OCLKDELAY_ACT_WAIT,
|
1595 |
|
|
INIT_OCLKDELAY_WRITE_WAIT,
|
1596 |
|
|
INIT_RDLVL_ACT_WAIT,
|
1597 |
|
|
INIT_RDLVL_STG1_WRITE_READ,
|
1598 |
|
|
INIT_RDLVL_STG2_READ_WAIT,
|
1599 |
|
|
INIT_WRCAL_ACT_WAIT,
|
1600 |
|
|
INIT_WRCAL_WRITE_READ,
|
1601 |
|
|
INIT_WRCAL_READ_WAIT,
|
1602 |
|
|
INIT_PRECHARGE_PREWAIT,
|
1603 |
|
|
INIT_PRECHARGE_WAIT,
|
1604 |
|
|
INIT_DDR2_PRECHARGE_WAIT,
|
1605 |
|
|
INIT_REG_WRITE_WAIT,
|
1606 |
|
|
INIT_REFRESH_WAIT,
|
1607 |
|
|
INIT_REFRESH_RNK2_WAIT: begin
|
1608 |
|
|
if (phy_ctl_full || phy_cmd_full)
|
1609 |
|
|
cnt_cmd_r <= #TCQ cnt_cmd_r;
|
1610 |
|
|
else
|
1611 |
|
|
cnt_cmd_r <= #TCQ cnt_cmd_r + 1;
|
1612 |
|
|
end
|
1613 |
|
|
INIT_WRLVL_WAIT:
|
1614 |
|
|
cnt_cmd_r <= #TCQ 'b0;
|
1615 |
|
|
default:
|
1616 |
|
|
cnt_cmd_r <= #TCQ 'b0;
|
1617 |
|
|
endcase
|
1618 |
|
|
end
|
1619 |
|
|
|
1620 |
|
|
// pulse when count reaches terminal count
|
1621 |
|
|
always @(posedge clk)
|
1622 |
|
|
cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);
|
1623 |
|
|
|
1624 |
|
|
// For ODT deassertion - hold throughout post read/write wait stage, but
|
1625 |
|
|
// deassert before next command. The post read/write stage is very long, so
|
1626 |
|
|
// we simply address the longest case here plus some margin.
|
1627 |
|
|
always @(posedge clk)
|
1628 |
|
|
cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7));
|
1629 |
|
|
|
1630 |
|
|
//************************************************************************
|
1631 |
|
|
// Added to support PO fine delay inc when TG errors
|
1632 |
|
|
always @(posedge clk) begin
|
1633 |
|
|
case (init_state_r)
|
1634 |
|
|
INIT_WRCAL_READ_WAIT: begin
|
1635 |
|
|
if (phy_ctl_full || phy_cmd_full)
|
1636 |
|
|
cnt_wait <= #TCQ cnt_wait;
|
1637 |
|
|
else
|
1638 |
|
|
cnt_wait <= #TCQ cnt_wait + 1;
|
1639 |
|
|
end
|
1640 |
|
|
default:
|
1641 |
|
|
cnt_wait <= #TCQ 'b0;
|
1642 |
|
|
endcase
|
1643 |
|
|
end
|
1644 |
|
|
|
1645 |
|
|
always @(posedge clk)
|
1646 |
|
|
cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4);
|
1647 |
|
|
|
1648 |
|
|
always @(posedge clk) begin
|
1649 |
|
|
if (rst || ~temp_wrcal_done)
|
1650 |
|
|
temp_lmr_done <= #TCQ 1'b0;
|
1651 |
|
|
else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR))
|
1652 |
|
|
temp_lmr_done <= #TCQ 1'b1;
|
1653 |
|
|
end
|
1654 |
|
|
|
1655 |
|
|
always @(posedge clk)
|
1656 |
|
|
temp_wrcal_done_r <= #TCQ temp_wrcal_done;
|
1657 |
|
|
|
1658 |
|
|
always @(posedge clk)
|
1659 |
|
|
if (rst) begin
|
1660 |
|
|
tg_timer_go <= #TCQ 1'b0;
|
1661 |
|
|
end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done &&
|
1662 |
|
|
(init_state_r == INIT_WRCAL_READ_WAIT)) begin
|
1663 |
|
|
tg_timer_go <= #TCQ 1'b1;
|
1664 |
|
|
end else begin
|
1665 |
|
|
tg_timer_go <= #TCQ 1'b0;
|
1666 |
|
|
end
|
1667 |
|
|
|
1668 |
|
|
always @(posedge clk) begin
|
1669 |
|
|
if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) ||
|
1670 |
|
|
(init_state_r == INIT_PRECHARGE_PREWAIT))
|
1671 |
|
|
tg_timer <= #TCQ 'd0;
|
1672 |
|
|
else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) &&
|
1673 |
|
|
tg_timer_go &&
|
1674 |
|
|
(tg_timer != TG_TIMER_TIMEOUT))
|
1675 |
|
|
tg_timer <= #TCQ tg_timer + 1;
|
1676 |
|
|
end
|
1677 |
|
|
|
1678 |
|
|
always @(posedge clk) begin
|
1679 |
|
|
if (rst)
|
1680 |
|
|
tg_timer_done <= #TCQ 1'b0;
|
1681 |
|
|
else if (tg_timer == TG_TIMER_TIMEOUT)
|
1682 |
|
|
tg_timer_done <= #TCQ 1'b1;
|
1683 |
|
|
else
|
1684 |
|
|
tg_timer_done <= #TCQ 1'b0;
|
1685 |
|
|
end
|
1686 |
|
|
|
1687 |
|
|
always @(posedge clk) begin
|
1688 |
|
|
if (rst)
|
1689 |
|
|
no_rst_tg_mc <= #TCQ 1'b0;
|
1690 |
|
|
else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req)
|
1691 |
|
|
no_rst_tg_mc <= #TCQ 1'b1;
|
1692 |
|
|
else
|
1693 |
|
|
no_rst_tg_mc <= #TCQ 1'b0;
|
1694 |
|
|
end
|
1695 |
|
|
|
1696 |
|
|
//************************************************************************
|
1697 |
|
|
|
1698 |
|
|
always @(posedge clk) begin
|
1699 |
|
|
if (rst)
|
1700 |
|
|
detect_pi_found_dqs <= #TCQ 1'b0;
|
1701 |
|
|
else if ((cnt_cmd_r == 7'b0111111) &&
|
1702 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ_WAIT))
|
1703 |
|
|
detect_pi_found_dqs <= #TCQ 1'b1;
|
1704 |
|
|
else
|
1705 |
|
|
detect_pi_found_dqs <= #TCQ 1'b0;
|
1706 |
|
|
end
|
1707 |
|
|
|
1708 |
|
|
//*****************************************************************
|
1709 |
|
|
// Initial delay after power-on for RESET, CKE
|
1710 |
|
|
// NOTE: Could reduce power consumption by turning off these counters
|
1711 |
|
|
// after initial power-up (at expense of more logic)
|
1712 |
|
|
// NOTE: Likely can combine multiple counters into single counter
|
1713 |
|
|
//*****************************************************************
|
1714 |
|
|
|
1715 |
|
|
// Create divided by 1024 version of clock
|
1716 |
|
|
always @(posedge clk)
|
1717 |
|
|
if (rst) begin
|
1718 |
|
|
cnt_pwron_ce_r <= #TCQ 10'h000;
|
1719 |
|
|
pwron_ce_r <= #TCQ 1'b0;
|
1720 |
|
|
end else begin
|
1721 |
|
|
cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;
|
1722 |
|
|
pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);
|
1723 |
|
|
end
|
1724 |
|
|
|
1725 |
|
|
// "Main" power-on counter - ticks every CLKDIV/1024 cycles
|
1726 |
|
|
always @(posedge clk)
|
1727 |
|
|
if (rst)
|
1728 |
|
|
cnt_pwron_r <= #TCQ 'b0;
|
1729 |
|
|
else if (pwron_ce_r)
|
1730 |
|
|
cnt_pwron_r <= #TCQ cnt_pwron_r + 1;
|
1731 |
|
|
|
1732 |
|
|
always @(posedge clk)
|
1733 |
|
|
if (rst || ~phy_ctl_ready) begin
|
1734 |
|
|
cnt_pwron_reset_done_r <= #TCQ 1'b0;
|
1735 |
|
|
cnt_pwron_cke_done_r <= #TCQ 1'b0;
|
1736 |
|
|
end else begin
|
1737 |
|
|
// skip power-up count for simulation purposes only
|
1738 |
|
|
if ((SIM_INIT_OPTION == "SKIP_PU_DLY") ||
|
1739 |
|
|
(SIM_INIT_OPTION == "SKIP_INIT")) begin
|
1740 |
|
|
cnt_pwron_reset_done_r <= #TCQ 1'b1;
|
1741 |
|
|
cnt_pwron_cke_done_r <= #TCQ 1'b1;
|
1742 |
|
|
end else begin
|
1743 |
|
|
// otherwise, create latched version of done signal for RESET, CKE
|
1744 |
|
|
if (DRAM_TYPE == "DDR3") begin
|
1745 |
|
|
if (!cnt_pwron_reset_done_r)
|
1746 |
|
|
cnt_pwron_reset_done_r
|
1747 |
|
|
<= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);
|
1748 |
|
|
if (!cnt_pwron_cke_done_r)
|
1749 |
|
|
cnt_pwron_cke_done_r
|
1750 |
|
|
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
|
1751 |
|
|
end else begin // DDR2
|
1752 |
|
|
cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed
|
1753 |
|
|
if (!cnt_pwron_cke_done_r)
|
1754 |
|
|
cnt_pwron_cke_done_r
|
1755 |
|
|
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
|
1756 |
|
|
end
|
1757 |
|
|
end
|
1758 |
|
|
end // else: !if(rst || ~phy_ctl_ready)
|
1759 |
|
|
|
1760 |
|
|
|
1761 |
|
|
always @(posedge clk)
|
1762 |
|
|
cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r;
|
1763 |
|
|
|
1764 |
|
|
// Keep RESET asserted and CKE deasserted until after power-on delay
|
1765 |
|
|
always @(posedge clk or posedge rst) begin
|
1766 |
|
|
if (rst)
|
1767 |
|
|
phy_reset_n <= #TCQ 1'b0;
|
1768 |
|
|
else
|
1769 |
|
|
phy_reset_n <= #TCQ cnt_pwron_reset_done_r;
|
1770 |
|
|
// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
|
1771 |
|
|
end
|
1772 |
|
|
|
1773 |
|
|
//*****************************************************************
|
1774 |
|
|
// Counter for tXPR (pronouned "Tax-Payer") - wait time after
|
1775 |
|
|
// CKE deassertion before first MRS command can be asserted
|
1776 |
|
|
//*****************************************************************
|
1777 |
|
|
|
1778 |
|
|
always @(posedge clk)
|
1779 |
|
|
if (!cnt_pwron_cke_done_r) begin
|
1780 |
|
|
cnt_txpr_r <= #TCQ 'b0;
|
1781 |
|
|
cnt_txpr_done_r <= #TCQ 1'b0;
|
1782 |
|
|
end else begin
|
1783 |
|
|
cnt_txpr_r <= #TCQ cnt_txpr_r + 1;
|
1784 |
|
|
if (!cnt_txpr_done_r)
|
1785 |
|
|
cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);
|
1786 |
|
|
end
|
1787 |
|
|
|
1788 |
|
|
//*****************************************************************
|
1789 |
|
|
// Counter for the initial 400ns wait for issuing precharge all
|
1790 |
|
|
// command after CKE assertion. Only for DDR2.
|
1791 |
|
|
//*****************************************************************
|
1792 |
|
|
|
1793 |
|
|
always @(posedge clk)
|
1794 |
|
|
if (!cnt_pwron_cke_done_r) begin
|
1795 |
|
|
cnt_init_pre_wait_r <= #TCQ 'b0;
|
1796 |
|
|
cnt_init_pre_wait_done_r <= #TCQ 1'b0;
|
1797 |
|
|
end else begin
|
1798 |
|
|
cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;
|
1799 |
|
|
if (!cnt_init_pre_wait_done_r)
|
1800 |
|
|
cnt_init_pre_wait_done_r
|
1801 |
|
|
<= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);
|
1802 |
|
|
end
|
1803 |
|
|
|
1804 |
|
|
//*****************************************************************
|
1805 |
|
|
// Wait for both DLL to lock (tDLLK) and ZQ calibration to finish
|
1806 |
|
|
// (tZQINIT). Both take the same amount of time (512*tCK)
|
1807 |
|
|
//*****************************************************************
|
1808 |
|
|
|
1809 |
|
|
always @(posedge clk)
|
1810 |
|
|
if (init_state_r == INIT_ZQCL) begin
|
1811 |
|
|
cnt_dllk_zqinit_r <= #TCQ 'b0;
|
1812 |
|
|
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
|
1813 |
|
|
end else if (~(phy_ctl_full || phy_cmd_full)) begin
|
1814 |
|
|
cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;
|
1815 |
|
|
if (!cnt_dllk_zqinit_done_r)
|
1816 |
|
|
cnt_dllk_zqinit_done_r
|
1817 |
|
|
<= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);
|
1818 |
|
|
end
|
1819 |
|
|
|
1820 |
|
|
//*****************************************************************
|
1821 |
|
|
// Keep track of which MRS counter needs to be programmed during
|
1822 |
|
|
// memory initialization
|
1823 |
|
|
// The counter and the done signal are reset an additional time
|
1824 |
|
|
// for DDR2. The same signals are used for the additional DDR2
|
1825 |
|
|
// initialization sequence.
|
1826 |
|
|
//*****************************************************************
|
1827 |
|
|
|
1828 |
|
|
always @(posedge clk)
|
1829 |
|
|
if ((init_state_r == INIT_IDLE)||
|
1830 |
|
|
((init_state_r == INIT_REFRESH)
|
1831 |
|
|
&& (~mem_init_done_r))) begin
|
1832 |
|
|
cnt_init_mr_r <= #TCQ 'b0;
|
1833 |
|
|
cnt_init_mr_done_r <= #TCQ 1'b0;
|
1834 |
|
|
end else if (init_state_r == INIT_LOAD_MR) begin
|
1835 |
|
|
cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;
|
1836 |
|
|
cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);
|
1837 |
|
|
end
|
1838 |
|
|
|
1839 |
|
|
|
1840 |
|
|
//*****************************************************************
|
1841 |
|
|
// Flag to tell if the first precharge for DDR2 init sequence is
|
1842 |
|
|
// done
|
1843 |
|
|
//*****************************************************************
|
1844 |
|
|
|
1845 |
|
|
always @(posedge clk)
|
1846 |
|
|
if (init_state_r == INIT_IDLE)
|
1847 |
|
|
ddr2_pre_flag_r<= #TCQ 'b0;
|
1848 |
|
|
else if (init_state_r == INIT_LOAD_MR)
|
1849 |
|
|
ddr2_pre_flag_r<= #TCQ 1'b1;
|
1850 |
|
|
// reset the flag for multi rank case
|
1851 |
|
|
else if ((ddr2_refresh_flag_r) &&
|
1852 |
|
|
(init_state_r == INIT_LOAD_MR_WAIT)&&
|
1853 |
|
|
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
|
1854 |
|
|
ddr2_pre_flag_r <= #TCQ 'b0;
|
1855 |
|
|
|
1856 |
|
|
//*****************************************************************
|
1857 |
|
|
// Flag to tell if the refresh stat for DDR2 init sequence is
|
1858 |
|
|
// reached
|
1859 |
|
|
//*****************************************************************
|
1860 |
|
|
|
1861 |
|
|
always @(posedge clk)
|
1862 |
|
|
if (init_state_r == INIT_IDLE)
|
1863 |
|
|
ddr2_refresh_flag_r<= #TCQ 'b0;
|
1864 |
|
|
else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))
|
1865 |
|
|
// reset the flag for multi rank case
|
1866 |
|
|
ddr2_refresh_flag_r<= #TCQ 1'b1;
|
1867 |
|
|
else if ((ddr2_refresh_flag_r) &&
|
1868 |
|
|
(init_state_r == INIT_LOAD_MR_WAIT)&&
|
1869 |
|
|
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
|
1870 |
|
|
ddr2_refresh_flag_r <= #TCQ 'b0;
|
1871 |
|
|
|
1872 |
|
|
//*****************************************************************
|
1873 |
|
|
// Keep track of the number of auto refreshes for DDR2
|
1874 |
|
|
// initialization. The spec asks for a minimum of two refreshes.
|
1875 |
|
|
// Four refreshes are performed here. The two extra refreshes is to
|
1876 |
|
|
// account for the 200 clock cycle wait between step h and l.
|
1877 |
|
|
// Without the two extra refreshes we would have to have a
|
1878 |
|
|
// wait state.
|
1879 |
|
|
//*****************************************************************
|
1880 |
|
|
|
1881 |
|
|
always @(posedge clk)
|
1882 |
|
|
if (init_state_r == INIT_IDLE) begin
|
1883 |
|
|
cnt_init_af_r <= #TCQ 'b0;
|
1884 |
|
|
cnt_init_af_done_r <= #TCQ 1'b0;
|
1885 |
|
|
end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin
|
1886 |
|
|
cnt_init_af_r <= #TCQ cnt_init_af_r + 1;
|
1887 |
|
|
cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);
|
1888 |
|
|
end
|
1889 |
|
|
|
1890 |
|
|
//*****************************************************************
|
1891 |
|
|
// Keep track of the register control word programming for
|
1892 |
|
|
// DDR3 RDIMM
|
1893 |
|
|
//*****************************************************************
|
1894 |
|
|
|
1895 |
|
|
always @(posedge clk)
|
1896 |
|
|
if (init_state_r == INIT_IDLE)
|
1897 |
|
|
reg_ctrl_cnt_r <= #TCQ 'b0;
|
1898 |
|
|
else if (init_state_r == INIT_REG_WRITE)
|
1899 |
|
|
reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;
|
1900 |
|
|
|
1901 |
|
|
generate
|
1902 |
|
|
if (RANKS < 2) begin: one_rank
|
1903 |
|
|
always @(posedge clk)
|
1904 |
|
|
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done ||
|
1905 |
|
|
(complex_byte_rd_done) || prbs_rdlvl_done_pulse )
|
1906 |
|
|
stg1_wr_done <= #TCQ 1'b0;
|
1907 |
|
|
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
|
1908 |
|
|
stg1_wr_done <= #TCQ 1'b1;
|
1909 |
|
|
end else begin: two_ranks
|
1910 |
|
|
always @(posedge clk)
|
1911 |
|
|
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done ||
|
1912 |
|
|
(complex_byte_rd_done) || prbs_rdlvl_done_pulse ||
|
1913 |
|
|
(rdlvl_stg1_rank_done ))
|
1914 |
|
|
stg1_wr_done <= #TCQ 1'b0;
|
1915 |
|
|
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
|
1916 |
|
|
stg1_wr_done <= #TCQ 1'b1;
|
1917 |
|
|
end
|
1918 |
|
|
endgenerate
|
1919 |
|
|
|
1920 |
|
|
always @(posedge clk)
|
1921 |
|
|
if (rst)
|
1922 |
|
|
rnk_ref_cnt <= #TCQ 1'b0;
|
1923 |
|
|
else if (stg1_wr_done &&
|
1924 |
|
|
(init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r)
|
1925 |
|
|
rnk_ref_cnt <= #TCQ ~rnk_ref_cnt;
|
1926 |
|
|
|
1927 |
|
|
|
1928 |
|
|
always @(posedge clk)
|
1929 |
|
|
if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) ||
|
1930 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) ||
|
1931 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT))
|
1932 |
|
|
num_refresh <= #TCQ 'd0;
|
1933 |
|
|
else if ((init_state_r == INIT_REFRESH) &&
|
1934 |
|
|
(~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) ||
|
1935 |
|
|
(rdlvl_stg1_done && ~prbs_rdlvl_done) ||
|
1936 |
|
|
(prbs_rdlvl_done && ~complex_oclkdelay_calib_done) ||
|
1937 |
|
|
((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||
|
1938 |
|
|
((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)))
|
1939 |
|
|
num_refresh <= #TCQ num_refresh + 1;
|
1940 |
|
|
|
1941 |
|
|
|
1942 |
|
|
//***************************************************************************
|
1943 |
|
|
// Initialization state machine
|
1944 |
|
|
//***************************************************************************
|
1945 |
|
|
|
1946 |
|
|
//*****************************************************************
|
1947 |
|
|
// Next-state logic
|
1948 |
|
|
//*****************************************************************
|
1949 |
|
|
|
1950 |
|
|
always @(posedge clk)
|
1951 |
|
|
if (rst)begin
|
1952 |
|
|
init_state_r <= #TCQ INIT_IDLE;
|
1953 |
|
|
init_state_r1 <= #TCQ INIT_IDLE;
|
1954 |
|
|
end else begin
|
1955 |
|
|
init_state_r <= #TCQ init_next_state;
|
1956 |
|
|
init_state_r1 <= #TCQ init_state_r;
|
1957 |
|
|
end
|
1958 |
|
|
|
1959 |
|
|
always @(*) begin
|
1960 |
|
|
init_next_state = init_state_r;
|
1961 |
|
|
(* full_case, parallel_case *) case (init_state_r)
|
1962 |
|
|
|
1963 |
|
|
//*******************************************************
|
1964 |
|
|
// DRAM initialization
|
1965 |
|
|
//*******************************************************
|
1966 |
|
|
|
1967 |
|
|
// Initial state - wait for:
|
1968 |
|
|
// 1. Power-on delays to pass
|
1969 |
|
|
// 2. PHY Control Block to assert phy_ctl_ready
|
1970 |
|
|
// 3. PHY Control FIFO must not be FULL
|
1971 |
|
|
// 4. Read path initialization to finish
|
1972 |
|
|
INIT_IDLE:
|
1973 |
|
|
if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done
|
1974 |
|
|
&& ~(phy_ctl_full || phy_cmd_full) ) begin
|
1975 |
|
|
// If skipping memory initialization (simulation only)
|
1976 |
|
|
if (SIM_INIT_OPTION == "SKIP_INIT")
|
1977 |
|
|
//if (WRLVL == "ON")
|
1978 |
|
|
// Proceed to write leveling
|
1979 |
|
|
// init_next_state = INIT_WRLVL_START;
|
1980 |
|
|
//else //if (SIM_CAL_OPTION != "SKIP_CAL")
|
1981 |
|
|
// Proceed to Phaser_In phase lock
|
1982 |
|
|
init_next_state = INIT_RDLVL_ACT;
|
1983 |
|
|
// else
|
1984 |
|
|
// Skip read leveling
|
1985 |
|
|
//init_next_state = INIT_DONE;
|
1986 |
|
|
else
|
1987 |
|
|
init_next_state = INIT_WAIT_CKE_EXIT;
|
1988 |
|
|
end
|
1989 |
|
|
|
1990 |
|
|
// Wait minimum of Reset CKE exit time (tXPR = max(tXS,
|
1991 |
|
|
INIT_WAIT_CKE_EXIT:
|
1992 |
|
|
if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3")
|
1993 |
|
|
&& ~(phy_ctl_full || phy_cmd_full)) begin
|
1994 |
|
|
if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) ||
|
1995 |
|
|
(RANKS > 1)))
|
1996 |
|
|
//register write for reg dimm. Some register chips
|
1997 |
|
|
// have the register chip in a pre-programmed state
|
1998 |
|
|
// in that case the nCS_PER_RANK == 1 && RANKS == 1
|
1999 |
|
|
init_next_state = INIT_REG_WRITE;
|
2000 |
|
|
else
|
2001 |
|
|
// Load mode register - this state is repeated multiple times
|
2002 |
|
|
init_next_state = INIT_LOAD_MR;
|
2003 |
|
|
end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2")
|
2004 |
|
|
&& ~(phy_ctl_full || phy_cmd_full))
|
2005 |
|
|
// DDR2 start with a precharge all command
|
2006 |
|
|
init_next_state = INIT_DDR2_PRECHARGE;
|
2007 |
|
|
|
2008 |
|
|
INIT_REG_WRITE:
|
2009 |
|
|
init_next_state = INIT_REG_WRITE_WAIT;
|
2010 |
|
|
|
2011 |
|
|
INIT_REG_WRITE_WAIT:
|
2012 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2013 |
|
|
if(reg_ctrl_cnt_r == 4'd8)
|
2014 |
|
|
init_next_state = INIT_LOAD_MR;
|
2015 |
|
|
else
|
2016 |
|
|
init_next_state = INIT_REG_WRITE;
|
2017 |
|
|
end
|
2018 |
|
|
|
2019 |
|
|
INIT_LOAD_MR:
|
2020 |
|
|
init_next_state = INIT_LOAD_MR_WAIT;
|
2021 |
|
|
// After loading MR, wait at least tMRD
|
2022 |
|
|
|
2023 |
|
|
INIT_LOAD_MR_WAIT:
|
2024 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2025 |
|
|
// If finished loading all mode registers, proceed to next step
|
2026 |
|
|
if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done)
|
2027 |
|
|
// for ddr3 when the correct burst length is writtern at end
|
2028 |
|
|
init_next_state = INIT_PRECHARGE;
|
2029 |
|
|
else if (~wrcal_done && temp_lmr_done)
|
2030 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2031 |
|
|
else if (cnt_init_mr_done_r)begin
|
2032 |
|
|
if(DRAM_TYPE == "DDR3")
|
2033 |
|
|
init_next_state = INIT_ZQCL;
|
2034 |
|
|
else begin //DDR2
|
2035 |
|
|
if(ddr2_refresh_flag_r)begin
|
2036 |
|
|
// memory initialization per rank for multi-rank case
|
2037 |
|
|
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
|
2038 |
|
|
init_next_state = INIT_DDR2_MULTI_RANK;
|
2039 |
|
|
else
|
2040 |
|
|
init_next_state = INIT_RDLVL_ACT;
|
2041 |
|
|
// ddr2 initialization done.load mode state after refresh
|
2042 |
|
|
end else
|
2043 |
|
|
init_next_state = INIT_DDR2_PRECHARGE;
|
2044 |
|
|
end
|
2045 |
|
|
end else
|
2046 |
|
|
init_next_state = INIT_LOAD_MR;
|
2047 |
|
|
end
|
2048 |
|
|
|
2049 |
|
|
// DDR2 multi rank transition state
|
2050 |
|
|
INIT_DDR2_MULTI_RANK:
|
2051 |
|
|
init_next_state = INIT_DDR2_MULTI_RANK_WAIT;
|
2052 |
|
|
|
2053 |
|
|
INIT_DDR2_MULTI_RANK_WAIT:
|
2054 |
|
|
init_next_state = INIT_DDR2_PRECHARGE;
|
2055 |
|
|
|
2056 |
|
|
// Initial ZQ calibration
|
2057 |
|
|
INIT_ZQCL:
|
2058 |
|
|
init_next_state = INIT_WAIT_DLLK_ZQINIT;
|
2059 |
|
|
|
2060 |
|
|
// Wait until both DLL have locked, and ZQ calibration done
|
2061 |
|
|
INIT_WAIT_DLLK_ZQINIT:
|
2062 |
|
|
if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full))
|
2063 |
|
|
// memory initialization per rank for multi-rank case
|
2064 |
|
|
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
|
2065 |
|
|
init_next_state = INIT_LOAD_MR;
|
2066 |
|
|
//else if (WRLVL == "ON")
|
2067 |
|
|
// init_next_state = INIT_WRLVL_START;
|
2068 |
|
|
else
|
2069 |
|
|
// skip write-leveling (e.g. for DDR2 interface)
|
2070 |
|
|
init_next_state = INIT_RDLVL_ACT;
|
2071 |
|
|
|
2072 |
|
|
// Initial precharge for DDR2
|
2073 |
|
|
INIT_DDR2_PRECHARGE:
|
2074 |
|
|
init_next_state = INIT_DDR2_PRECHARGE_WAIT;
|
2075 |
|
|
|
2076 |
|
|
INIT_DDR2_PRECHARGE_WAIT:
|
2077 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2078 |
|
|
if (ddr2_pre_flag_r)
|
2079 |
|
|
init_next_state = INIT_REFRESH;
|
2080 |
|
|
else // from precharge state initially go to load mode
|
2081 |
|
|
init_next_state = INIT_LOAD_MR;
|
2082 |
|
|
end
|
2083 |
|
|
|
2084 |
|
|
INIT_REFRESH:
|
2085 |
|
|
if ((RANKS == 2) && (chip_cnt_r == RANKS - 1))
|
2086 |
|
|
init_next_state = INIT_REFRESH_RNK2_WAIT;
|
2087 |
|
|
else
|
2088 |
|
|
init_next_state = INIT_REFRESH_WAIT;
|
2089 |
|
|
|
2090 |
|
|
INIT_REFRESH_RNK2_WAIT:
|
2091 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
|
2092 |
|
|
init_next_state = INIT_PRECHARGE;
|
2093 |
|
|
|
2094 |
|
|
INIT_REFRESH_WAIT:
|
2095 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
|
2096 |
|
|
if(cnt_init_af_done_r && (~mem_init_done_r))
|
2097 |
|
|
// go to lm state as part of DDR2 init sequence
|
2098 |
|
|
init_next_state = INIT_LOAD_MR;
|
2099 |
|
|
// Go to state to issue back-to-back writes during limit check and centering
|
2100 |
|
|
else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin
|
2101 |
|
|
if (num_refresh == 'd8)
|
2102 |
|
|
init_next_state = INIT_OCAL_CENTER_ACT;
|
2103 |
|
|
else
|
2104 |
|
|
init_next_state = INIT_REFRESH;
|
2105 |
|
|
end else if(rdlvl_stg1_done && oclkdelay_center_calib_done &&
|
2106 |
|
|
complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON"))
|
2107 |
|
|
init_next_state = INIT_WRLVL_START;
|
2108 |
|
|
else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON"))
|
2109 |
|
|
init_next_state = INIT_WRLVL_START;
|
2110 |
|
|
else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done
|
2111 |
|
|
&& pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26
|
2112 |
|
|
&& mem_init_done_r) begin
|
2113 |
|
|
if (num_refresh == 'd8) begin
|
2114 |
|
|
if (BYPASS_COMPLEX_OCAL == "FALSE")
|
2115 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2116 |
|
|
else
|
2117 |
|
|
init_next_state = INIT_WRCAL_ACT;
|
2118 |
|
|
end else
|
2119 |
|
|
init_next_state = INIT_REFRESH;
|
2120 |
|
|
end else if (~pi_dqs_found_done ||
|
2121 |
|
|
(rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) ||
|
2122 |
|
|
((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||
|
2123 |
|
|
((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin
|
2124 |
|
|
if (num_refresh == 'd8)
|
2125 |
|
|
init_next_state = INIT_RDLVL_ACT;
|
2126 |
|
|
else
|
2127 |
|
|
init_next_state = INIT_REFRESH;
|
2128 |
|
|
end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3")
|
2129 |
|
|
&& (CLK_PERIOD/nCK_PER_CLK > 2500))
|
2130 |
|
|
init_next_state = INIT_WRLVL_LOAD_MR2;
|
2131 |
|
|
else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON"))
|
2132 |
|
|
&& mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500))
|
2133 |
|
|
init_next_state = INIT_WRCAL_ACT;
|
2134 |
|
|
else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin
|
2135 |
|
|
if (num_refresh == 'd8)
|
2136 |
|
|
init_next_state = INIT_MPR_RDEN;
|
2137 |
|
|
else
|
2138 |
|
|
init_next_state = INIT_REFRESH;
|
2139 |
|
|
end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25
|
2140 |
|
|
(~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3"))
|
2141 |
|
|
init_next_state = INIT_WRLVL_LOAD_MR2;
|
2142 |
|
|
else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500))
|
2143 |
|
|
&& pi_dqs_found_done)
|
2144 |
|
|
init_next_state = INIT_WRCAL_ACT;
|
2145 |
|
|
else if (mem_init_done_r) begin
|
2146 |
|
|
if (RANKS < 2)
|
2147 |
|
|
init_next_state = INIT_RDLVL_ACT;
|
2148 |
|
|
else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done)
|
2149 |
|
|
init_next_state = INIT_PRECHARGE;
|
2150 |
|
|
else
|
2151 |
|
|
init_next_state = INIT_RDLVL_ACT;
|
2152 |
|
|
end else // to DDR2 init state as part of DDR2 init sequence
|
2153 |
|
|
init_next_state = INIT_REFRESH;
|
2154 |
|
|
end
|
2155 |
|
|
|
2156 |
|
|
//******************************************************
|
2157 |
|
|
// Write Leveling
|
2158 |
|
|
//*******************************************************
|
2159 |
|
|
|
2160 |
|
|
// Enable write leveling in MR1 and start write leveling
|
2161 |
|
|
// for current rank
|
2162 |
|
|
INIT_WRLVL_START:
|
2163 |
|
|
init_next_state = INIT_WRLVL_WAIT;
|
2164 |
|
|
|
2165 |
|
|
// Wait for both MR load and write leveling to complete
|
2166 |
|
|
// (write leveling should take much longer than MR load..)
|
2167 |
|
|
INIT_WRLVL_WAIT:
|
2168 |
|
|
if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full))
|
2169 |
|
|
init_next_state = INIT_WRLVL_LOAD_MR;
|
2170 |
|
|
|
2171 |
|
|
// Disable write leveling in MR1 for current rank
|
2172 |
|
|
INIT_WRLVL_LOAD_MR:
|
2173 |
|
|
init_next_state = INIT_WRLVL_LOAD_MR_WAIT;
|
2174 |
|
|
|
2175 |
|
|
INIT_WRLVL_LOAD_MR_WAIT:
|
2176 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
|
2177 |
|
|
init_next_state = INIT_WRLVL_LOAD_MR2;
|
2178 |
|
|
|
2179 |
|
|
// Load MR2 to set ODT: Dynamic ODT for single rank case
|
2180 |
|
|
// And ODTs for multi-rank case as well
|
2181 |
|
|
INIT_WRLVL_LOAD_MR2:
|
2182 |
|
|
init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
|
2183 |
|
|
|
2184 |
|
|
// Wait tMRD before proceeding
|
2185 |
|
|
INIT_WRLVL_LOAD_MR2_WAIT:
|
2186 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2187 |
|
|
//if (wrlvl_byte_done)
|
2188 |
|
|
// init_next_state = INIT_PRECHARGE_PREWAIT;
|
2189 |
|
|
// else if ((RANKS == 2) && wrlvl_rank_done_r2)
|
2190 |
|
|
// init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
|
2191 |
|
|
if (~wrlvl_done_r1)
|
2192 |
|
|
init_next_state = INIT_WRLVL_START;
|
2193 |
|
|
else if (SIM_CAL_OPTION == "SKIP_CAL")
|
2194 |
|
|
// If skip rdlvl, then we're done
|
2195 |
|
|
init_next_state = INIT_DONE;
|
2196 |
|
|
else
|
2197 |
|
|
// Otherwise, proceed to read leveling
|
2198 |
|
|
//init_next_state = INIT_RDLVL_ACT;
|
2199 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2200 |
|
|
end
|
2201 |
|
|
|
2202 |
|
|
//*******************************************************
|
2203 |
|
|
// Read Leveling
|
2204 |
|
|
//*******************************************************
|
2205 |
|
|
|
2206 |
|
|
// single row activate. All subsequent read leveling writes and
|
2207 |
|
|
// read will take place in this row
|
2208 |
|
|
INIT_RDLVL_ACT:
|
2209 |
|
|
init_next_state = INIT_RDLVL_ACT_WAIT;
|
2210 |
|
|
|
2211 |
|
|
// hang out for awhile before issuing subsequent column commands
|
2212 |
|
|
// it's also possible to reach this state at various points
|
2213 |
|
|
// during read leveling - determine what the current stage is
|
2214 |
|
|
INIT_RDLVL_ACT_WAIT:
|
2215 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2216 |
|
|
// Just finished an activate. Now either write, read, or precharge
|
2217 |
|
|
// depending on where we are in the training sequence
|
2218 |
|
|
if (!pi_calib_done_r1)
|
2219 |
|
|
init_next_state = INIT_PI_PHASELOCK_READS;
|
2220 |
|
|
else if (!pi_dqs_found_done)
|
2221 |
|
|
// (!pi_dqs_found_start || pi_dqs_found_rank_done))
|
2222 |
|
|
init_next_state = INIT_RDLVL_STG2_READ;
|
2223 |
|
|
else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500))
|
2224 |
|
|
init_next_state = INIT_WRCAL_ACT_WAIT;
|
2225 |
|
|
else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) ||
|
2226 |
|
|
(!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin
|
2227 |
|
|
// Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl
|
2228 |
|
|
if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done)
|
2229 |
|
|
init_next_state = INIT_RDLVL_ACT_WAIT;
|
2230 |
|
|
else
|
2231 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE;
|
2232 |
|
|
end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin
|
2233 |
|
|
if (rdlvl_last_byte_done || prbs_last_byte_done)
|
2234 |
|
|
// Added to avoid extra reads at the end of read leveling
|
2235 |
|
|
init_next_state = INIT_RDLVL_ACT_WAIT;
|
2236 |
|
|
else begin
|
2237 |
|
|
// Case 2: If in stage 1, and just precharged after training
|
2238 |
|
|
// previous byte, then continue reading
|
2239 |
|
|
if (rdlvl_stg1_done)
|
2240 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
|
2241 |
|
|
else
|
2242 |
|
|
init_next_state = INIT_RDLVL_STG1_READ;
|
2243 |
|
|
end
|
2244 |
|
|
end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") &&
|
2245 |
|
|
(CLK_PERIOD/nCK_PER_CLK > 2500))
|
2246 |
|
|
init_next_state = INIT_WRCAL_ACT_WAIT;
|
2247 |
|
|
else
|
2248 |
|
|
// Otherwise, if we're finished with calibration, then precharge
|
2249 |
|
|
// the row - silly, because we just opened it - possible to take
|
2250 |
|
|
// this out by adding logic to avoid the ACT in first place. Make
|
2251 |
|
|
// sure that cnt_cmd_done will handle tRAS(min)
|
2252 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2253 |
|
|
end
|
2254 |
|
|
|
2255 |
|
|
//**************************************************
|
2256 |
|
|
// Back-to-back reads for Phaser_IN Phase locking
|
2257 |
|
|
// DQS to FREQ_REF clock
|
2258 |
|
|
//**************************************************
|
2259 |
|
|
|
2260 |
|
|
INIT_PI_PHASELOCK_READS:
|
2261 |
|
|
if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)
|
2262 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2263 |
|
|
|
2264 |
|
|
//*********************************************
|
2265 |
|
|
// Stage 1 read-leveling (write and continuous read)
|
2266 |
|
|
//*********************************************
|
2267 |
|
|
|
2268 |
|
|
// Write training pattern for stage 1
|
2269 |
|
|
// PRBS pattern of TBD length
|
2270 |
|
|
INIT_RDLVL_STG1_WRITE:
|
2271 |
|
|
// 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle
|
2272 |
|
|
// 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words
|
2273 |
|
|
// 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words
|
2274 |
|
|
// An entire row worth of writes issued before proceeding to reads
|
2275 |
|
|
// The number of write is (2^column width)/burst length to accomodate
|
2276 |
|
|
// PRBS pattern for window detection.
|
2277 |
|
|
//VCCO/VCCAUX write is not done
|
2278 |
|
|
if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1)
|
2279 |
|
|
init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT;
|
2280 |
|
|
//back to back write from row1
|
2281 |
|
|
else if (stg1_wr_rd_cnt == 9'd1) begin
|
2282 |
|
|
if (rdlvl_stg1_done_r1)
|
2283 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2284 |
|
|
else
|
2285 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
|
2286 |
|
|
end
|
2287 |
|
|
|
2288 |
|
|
INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT:
|
2289 |
|
|
if(read_pause_ext) begin
|
2290 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2291 |
|
|
end else begin
|
2292 |
|
|
|
2293 |
|
|
if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
|
2294 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2295 |
|
|
else if (complex_wait_cnt == 'd15)
|
2296 |
|
|
//At the end of the byte, it goes to REFRESH
|
2297 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE;
|
2298 |
|
|
end
|
2299 |
|
|
|
2300 |
|
|
INIT_RDLVL_COMPLEX_PRECHARGE:
|
2301 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT;
|
2302 |
|
|
|
2303 |
|
|
INIT_RDLVL_COMPLEX_PRECHARGE_WAIT:
|
2304 |
|
|
if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
|
2305 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2306 |
|
|
else if (complex_wait_cnt == 'd15) begin
|
2307 |
|
|
if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26
|
2308 |
|
|
// added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode
|
2309 |
|
|
if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done)
|
2310 |
|
|
init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26
|
2311 |
|
|
else if (lim_done && complex_oclkdelay_calib_start_r2)
|
2312 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_ACT;
|
2313 |
|
|
else
|
2314 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT;
|
2315 |
|
|
end else
|
2316 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_ACT;
|
2317 |
|
|
end
|
2318 |
|
|
|
2319 |
|
|
|
2320 |
|
|
INIT_RDLVL_COMPLEX_ACT:
|
2321 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT;
|
2322 |
|
|
|
2323 |
|
|
INIT_RDLVL_COMPLEX_ACT_WAIT:
|
2324 |
|
|
if (complex_rdlvl_int_ref_req)
|
2325 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2326 |
|
|
else if (complex_wait_cnt == 'd15) begin
|
2327 |
|
|
if (oclkdelay_center_calib_start)
|
2328 |
|
|
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
|
2329 |
|
|
else if (stg1_wr_done)
|
2330 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_READ;
|
2331 |
|
|
else if (~complex_row1_wr_done)
|
2332 |
|
|
if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write
|
2333 |
|
|
init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT;
|
2334 |
|
|
else
|
2335 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE;
|
2336 |
|
|
else
|
2337 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
|
2338 |
|
|
end
|
2339 |
|
|
|
2340 |
|
|
// Write-read turnaround
|
2341 |
|
|
INIT_RDLVL_STG1_WRITE_READ:
|
2342 |
|
|
if (reset_rd_addr_r1)
|
2343 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2344 |
|
|
else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
|
2345 |
|
|
if (rdlvl_stg1_done_r1)
|
2346 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_READ;
|
2347 |
|
|
else
|
2348 |
|
|
init_next_state = INIT_RDLVL_STG1_READ;
|
2349 |
|
|
end
|
2350 |
|
|
|
2351 |
|
|
// Continuous read, where interruptible by precharge request from
|
2352 |
|
|
// calibration logic. Also precharges when stage 1 is complete
|
2353 |
|
|
// No precharges when reads provided to Phaser_IN for phase locking
|
2354 |
|
|
// FREQ_REF to read DQS since data integrity is not important.
|
2355 |
|
|
INIT_RDLVL_STG1_READ:
|
2356 |
|
|
if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
|
2357 |
|
|
prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
|
2358 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2359 |
|
|
|
2360 |
|
|
INIT_RDLVL_COMPLEX_READ:
|
2361 |
|
|
if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
|
2362 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2363 |
|
|
//For non-back-to-back reads from row0 (VCCO and VCCAUX pattern)
|
2364 |
|
|
else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done)
|
2365 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT;
|
2366 |
|
|
//For back-to-back reads from row1 (ISI pattern)
|
2367 |
|
|
else if (stg1_wr_rd_cnt == 'd1)
|
2368 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2369 |
|
|
|
2370 |
|
|
INIT_RDLVL_COMPLEX_READ_WAIT:
|
2371 |
|
|
if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
|
2372 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2373 |
|
|
else if (stg1_wr_rd_cnt == 'd1)
|
2374 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2375 |
|
|
else if (complex_wait_cnt == 'd15)
|
2376 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_READ;
|
2377 |
|
|
|
2378 |
|
|
|
2379 |
|
|
//*********************************************
|
2380 |
|
|
// DQSFOUND calibration (set of 4 reads with gaps)
|
2381 |
|
|
//*********************************************
|
2382 |
|
|
|
2383 |
|
|
// Read of training data. Note that Stage 2 is not a constant read,
|
2384 |
|
|
// instead there is a large gap between each set of back-to-back reads
|
2385 |
|
|
INIT_RDLVL_STG2_READ:
|
2386 |
|
|
// 4 read commands issued back-to-back
|
2387 |
|
|
if (num_reads == 'b1)
|
2388 |
|
|
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
|
2389 |
|
|
|
2390 |
|
|
// Wait before issuing the next set of reads. If a precharge request
|
2391 |
|
|
// comes in then handle - this can occur after stage 2 calibration is
|
2392 |
|
|
// completed for a DQS group
|
2393 |
|
|
INIT_RDLVL_STG2_READ_WAIT:
|
2394 |
|
|
if (~(phy_ctl_full || phy_cmd_full)) begin
|
2395 |
|
|
if (pi_dqs_found_rank_done ||
|
2396 |
|
|
pi_dqs_found_done || prech_req_posedge_r)
|
2397 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2398 |
|
|
else if (cnt_cmd_done_r)
|
2399 |
|
|
init_next_state = INIT_RDLVL_STG2_READ;
|
2400 |
|
|
end
|
2401 |
|
|
|
2402 |
|
|
|
2403 |
|
|
//******************************************************************
|
2404 |
|
|
// MPR Read Leveling for DDR3 OCLK_DELAYED calibration
|
2405 |
|
|
//******************************************************************
|
2406 |
|
|
|
2407 |
|
|
// Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00
|
2408 |
|
|
// to enable Multi Purpose Register (MPR) Read
|
2409 |
|
|
INIT_MPR_RDEN:
|
2410 |
|
|
init_next_state = INIT_MPR_WAIT;
|
2411 |
|
|
|
2412 |
|
|
//Wait tMRD, tMOD
|
2413 |
|
|
INIT_MPR_WAIT:
|
2414 |
|
|
if (cnt_cmd_done_r) begin
|
2415 |
|
|
init_next_state = INIT_MPR_READ;
|
2416 |
|
|
end
|
2417 |
|
|
|
2418 |
|
|
// Issue back-to-back read commands to read from MPR with
|
2419 |
|
|
// Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined
|
2420 |
|
|
// MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...)
|
2421 |
|
|
INIT_MPR_READ:
|
2422 |
|
|
if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req)
|
2423 |
|
|
init_next_state = INIT_MPR_DISABLE_PREWAIT;
|
2424 |
|
|
|
2425 |
|
|
INIT_MPR_DISABLE_PREWAIT:
|
2426 |
|
|
if (cnt_cmd_done_r)
|
2427 |
|
|
init_next_state = INIT_MPR_DISABLE;
|
2428 |
|
|
|
2429 |
|
|
// Issue Load Mode Register 3 command with A[2]=0 to disable
|
2430 |
|
|
// MPR read
|
2431 |
|
|
INIT_MPR_DISABLE:
|
2432 |
|
|
init_next_state = INIT_MPR_DISABLE_WAIT;
|
2433 |
|
|
|
2434 |
|
|
INIT_MPR_DISABLE_WAIT:
|
2435 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2436 |
|
|
|
2437 |
|
|
|
2438 |
|
|
//***********************************************************************
|
2439 |
|
|
// OCLKDELAY Calibration
|
2440 |
|
|
//***********************************************************************
|
2441 |
|
|
|
2442 |
|
|
// This calibration requires single write followed by single read to
|
2443 |
|
|
// determine the Phaser_Out stage 3 delay required to center write DQS
|
2444 |
|
|
// in write DQ valid window.
|
2445 |
|
|
|
2446 |
|
|
// Single Row Activate command before issuing Write command
|
2447 |
|
|
INIT_OCLKDELAY_ACT:
|
2448 |
|
|
init_next_state = INIT_OCLKDELAY_ACT_WAIT;
|
2449 |
|
|
|
2450 |
|
|
INIT_OCLKDELAY_ACT_WAIT:
|
2451 |
|
|
if (cnt_cmd_done_r && ~oclk_prech_req)
|
2452 |
|
|
init_next_state = INIT_OCLKDELAY_WRITE;
|
2453 |
|
|
else if (oclkdelay_calib_done || prech_req_posedge_r)
|
2454 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2455 |
|
|
|
2456 |
|
|
INIT_OCLKDELAY_WRITE:
|
2457 |
|
|
if (oclk_wr_cnt == 4'd1)
|
2458 |
|
|
init_next_state = INIT_OCLKDELAY_WRITE_WAIT;
|
2459 |
|
|
|
2460 |
|
|
INIT_OCLKDELAY_WRITE_WAIT:
|
2461 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2462 |
|
|
if (oclkdelay_int_ref_req)
|
2463 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2464 |
|
|
else
|
2465 |
|
|
init_next_state = INIT_OCLKDELAY_READ;
|
2466 |
|
|
end
|
2467 |
|
|
|
2468 |
|
|
INIT_OCLKDELAY_READ:
|
2469 |
|
|
init_next_state = INIT_OCLKDELAY_READ_WAIT;
|
2470 |
|
|
|
2471 |
|
|
INIT_OCLKDELAY_READ_WAIT:
|
2472 |
|
|
if (~(phy_ctl_full || phy_cmd_full)) begin
|
2473 |
|
|
if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req)
|
2474 |
|
|
init_next_state = INIT_OCLKDELAY_WRITE;
|
2475 |
|
|
else if (oclkdelay_calib_done || prech_req_posedge_r ||
|
2476 |
|
|
wrlvl_final || oclkdelay_int_ref_req)
|
2477 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2478 |
|
|
else if (oclkdelay_center_calib_start)
|
2479 |
|
|
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
|
2480 |
|
|
end
|
2481 |
|
|
|
2482 |
|
|
|
2483 |
|
|
//*********************************************
|
2484 |
|
|
// Write calibration
|
2485 |
|
|
//*********************************************
|
2486 |
|
|
|
2487 |
|
|
// single row activate
|
2488 |
|
|
INIT_WRCAL_ACT:
|
2489 |
|
|
init_next_state = INIT_WRCAL_ACT_WAIT;
|
2490 |
|
|
|
2491 |
|
|
// hang out for awhile before issuing subsequent column command
|
2492 |
|
|
INIT_WRCAL_ACT_WAIT:
|
2493 |
|
|
if (cnt_cmd_done_r && ~wrcal_prech_req)
|
2494 |
|
|
init_next_state = INIT_WRCAL_WRITE;
|
2495 |
|
|
else if (wrcal_done || prech_req_posedge_r)
|
2496 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2497 |
|
|
|
2498 |
|
|
// Write training pattern for write calibration
|
2499 |
|
|
INIT_WRCAL_WRITE:
|
2500 |
|
|
// Once we've issued enough commands for 8 words - proceed to reads
|
2501 |
|
|
//if (burst_addr_r == 1'b1)
|
2502 |
|
|
if (wrcal_wr_cnt == 4'd1)
|
2503 |
|
|
init_next_state = INIT_WRCAL_WRITE_READ;
|
2504 |
|
|
|
2505 |
|
|
// Write-read turnaround
|
2506 |
|
|
INIT_WRCAL_WRITE_READ:
|
2507 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
|
2508 |
|
|
init_next_state = INIT_WRCAL_READ;
|
2509 |
|
|
else if (dqsfound_retry)
|
2510 |
|
|
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
|
2511 |
|
|
|
2512 |
|
|
|
2513 |
|
|
INIT_WRCAL_READ:
|
2514 |
|
|
if (burst_addr_r == 1'b1)
|
2515 |
|
|
init_next_state = INIT_WRCAL_READ_WAIT;
|
2516 |
|
|
|
2517 |
|
|
INIT_WRCAL_READ_WAIT:
|
2518 |
|
|
if (~(phy_ctl_full || phy_cmd_full)) begin
|
2519 |
|
|
if (wrcal_resume_r) begin
|
2520 |
|
|
if (wrcal_final_chk)
|
2521 |
|
|
init_next_state = INIT_WRCAL_READ;
|
2522 |
|
|
else
|
2523 |
|
|
init_next_state = INIT_WRCAL_WRITE;
|
2524 |
|
|
end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req ||
|
2525 |
|
|
// Added to support PO fine delay inc when TG errors
|
2526 |
|
|
wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done))
|
2527 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2528 |
|
|
else if (dqsfound_retry)
|
2529 |
|
|
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
|
2530 |
|
|
else if (wrcal_read_req && cnt_wrcal_rd)
|
2531 |
|
|
init_next_state = INIT_WRCAL_MULT_READS;
|
2532 |
|
|
end
|
2533 |
|
|
|
2534 |
|
|
INIT_WRCAL_MULT_READS:
|
2535 |
|
|
// multiple read commands issued back-to-back
|
2536 |
|
|
if (wrcal_reads == 'b1)
|
2537 |
|
|
init_next_state = INIT_WRCAL_READ_WAIT;
|
2538 |
|
|
|
2539 |
|
|
//*********************************************
|
2540 |
|
|
// Handling of precharge during and in between read-level stages
|
2541 |
|
|
//*********************************************
|
2542 |
|
|
|
2543 |
|
|
// Make sure we aren't violating any timing specs by precharging
|
2544 |
|
|
// immediately
|
2545 |
|
|
INIT_PRECHARGE_PREWAIT:
|
2546 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
|
2547 |
|
|
init_next_state = INIT_PRECHARGE;
|
2548 |
|
|
|
2549 |
|
|
// Initiate precharge
|
2550 |
|
|
INIT_PRECHARGE:
|
2551 |
|
|
init_next_state = INIT_PRECHARGE_WAIT;
|
2552 |
|
|
|
2553 |
|
|
INIT_PRECHARGE_WAIT:
|
2554 |
|
|
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
|
2555 |
|
|
if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) ||
|
2556 |
|
|
(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done &&
|
2557 |
|
|
(DRAM_TYPE == "DDR2")))
|
2558 |
|
|
init_next_state = INIT_DONE;
|
2559 |
|
|
else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done &&
|
2560 |
|
|
pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2")))
|
2561 |
|
|
init_next_state = INIT_WRCAL_ACT;
|
2562 |
|
|
else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done))
|
2563 |
|
|
&& (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done))
|
2564 |
|
|
&& prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin
|
2565 |
|
|
// after all calibration program the correct burst length
|
2566 |
|
|
init_next_state = INIT_LOAD_MR;
|
2567 |
|
|
// Added to support PO fine delay inc when TG errors
|
2568 |
|
|
end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done)
|
2569 |
|
|
init_next_state = INIT_WRCAL_READ_WAIT;
|
2570 |
|
|
else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON"))
|
2571 |
|
|
// If read leveling finished, proceed to write calibration
|
2572 |
|
|
init_next_state = INIT_REFRESH;
|
2573 |
|
|
else
|
2574 |
|
|
// Otherwise, open row for read-leveling purposes
|
2575 |
|
|
init_next_state = INIT_REFRESH;
|
2576 |
|
|
end
|
2577 |
|
|
|
2578 |
|
|
//*******************************************************
|
2579 |
|
|
// COMPLEX OCLK calibration - for fragmented write
|
2580 |
|
|
//*******************************************************
|
2581 |
|
|
INIT_OCAL_COMPLEX_ACT:
|
2582 |
|
|
init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT;
|
2583 |
|
|
|
2584 |
|
|
INIT_OCAL_COMPLEX_ACT_WAIT:
|
2585 |
|
|
if (complex_wait_cnt =='d15)
|
2586 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE;
|
2587 |
|
|
|
2588 |
|
|
INIT_OCAL_COMPLEX_WRITE_WAIT:
|
2589 |
|
|
if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1))
|
2590 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2591 |
|
|
else if (stg1_wr_rd_cnt == 'd1)
|
2592 |
|
|
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
|
2593 |
|
|
else if (complex_wait_cnt == 'd15)
|
2594 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE;
|
2595 |
|
|
|
2596 |
|
|
//wait for all srg2/stg3 tap movement is done and go back to write again
|
2597 |
|
|
INIT_OCAL_COMPLEX_RESUME_WAIT:
|
2598 |
|
|
if (complex_oclk_calib_resume)
|
2599 |
|
|
init_next_state = INIT_RDLVL_STG1_WRITE;
|
2600 |
|
|
else if (complex_oclkdelay_calib_done || complex_ocal_ref_req )
|
2601 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2602 |
|
|
|
2603 |
|
|
//*******************************************************
|
2604 |
|
|
// OCAL STG3 Centering calibration
|
2605 |
|
|
//*******************************************************
|
2606 |
|
|
INIT_OCAL_CENTER_ACT:
|
2607 |
|
|
init_next_state = INIT_OCAL_CENTER_ACT_WAIT;
|
2608 |
|
|
|
2609 |
|
|
INIT_OCAL_CENTER_ACT_WAIT:
|
2610 |
|
|
if (ocal_act_wait_cnt == 'd15)
|
2611 |
|
|
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
|
2612 |
|
|
|
2613 |
|
|
INIT_OCAL_CENTER_WRITE:
|
2614 |
|
|
if(!oclk_center_write_resume && !lim_wr_req)
|
2615 |
|
|
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
|
2616 |
|
|
|
2617 |
|
|
INIT_OCAL_CENTER_WRITE_WAIT:
|
2618 |
|
|
//if (oclkdelay_center_calib_done || prech_req_posedge_r)
|
2619 |
|
|
if (prech_req_posedge_r)
|
2620 |
|
|
init_next_state = INIT_PRECHARGE_PREWAIT;
|
2621 |
|
|
else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start)
|
2622 |
|
|
init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT;
|
2623 |
|
|
else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start)
|
2624 |
|
|
init_next_state = INIT_OCLKDELAY_READ_WAIT;
|
2625 |
|
|
else if (oclk_center_write_resume || lim_wr_req)
|
2626 |
|
|
init_next_state = INIT_OCAL_CENTER_WRITE;
|
2627 |
|
|
|
2628 |
|
|
//*******************************************************
|
2629 |
|
|
// Initialization/Calibration done. Take a long rest, relax
|
2630 |
|
|
//*******************************************************
|
2631 |
|
|
|
2632 |
|
|
INIT_DONE:
|
2633 |
|
|
init_next_state = INIT_DONE;
|
2634 |
|
|
|
2635 |
|
|
endcase
|
2636 |
|
|
end
|
2637 |
|
|
|
2638 |
|
|
//*****************************************************************
|
2639 |
|
|
// Initialization done signal - asserted before leveling starts
|
2640 |
|
|
//*****************************************************************
|
2641 |
|
|
|
2642 |
|
|
|
2643 |
|
|
always @(posedge clk)
|
2644 |
|
|
if (rst)
|
2645 |
|
|
mem_init_done_r <= #TCQ 1'b0;
|
2646 |
|
|
else if ((!cnt_dllk_zqinit_done_r &&
|
2647 |
|
|
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
|
2648 |
|
|
(chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3"))
|
2649 |
|
|
|| ( (init_state_r == INIT_LOAD_MR_WAIT) &&
|
2650 |
|
|
(ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1)
|
2651 |
|
|
&& (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2")))
|
2652 |
|
|
mem_init_done_r <= #TCQ 1'b1;
|
2653 |
|
|
|
2654 |
|
|
//*****************************************************************
|
2655 |
|
|
// Write Calibration signal to PHY Control Block - asserted before
|
2656 |
|
|
// Write Leveling starts
|
2657 |
|
|
//*****************************************************************
|
2658 |
|
|
|
2659 |
|
|
//generate
|
2660 |
|
|
//if (RANKS < 2) begin: ranks_one
|
2661 |
|
|
always @(posedge clk) begin
|
2662 |
|
|
if (rst || (done_dqs_tap_inc &&
|
2663 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2)))
|
2664 |
|
|
write_calib <= #TCQ 1'b0;
|
2665 |
|
|
else if (wrlvl_active_r1)
|
2666 |
|
|
write_calib <= #TCQ 1'b1;
|
2667 |
|
|
end
|
2668 |
|
|
//end else begin: ranks_two
|
2669 |
|
|
// always @(posedge clk) begin
|
2670 |
|
|
// if (rst ||
|
2671 |
|
|
// ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) &&
|
2672 |
|
|
// ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) ||
|
2673 |
|
|
// (SIM_CAL_OPTION == "FAST_CAL"))))
|
2674 |
|
|
// write_calib <= #TCQ 1'b0;
|
2675 |
|
|
// else if (wrlvl_active_r1)
|
2676 |
|
|
// write_calib <= #TCQ 1'b1;
|
2677 |
|
|
// end
|
2678 |
|
|
//end
|
2679 |
|
|
//endgenerate
|
2680 |
|
|
|
2681 |
|
|
//*****************************************************************
|
2682 |
|
|
// Read Calibration signal to PHY Control Block - asserted after
|
2683 |
|
|
// Write Leveling during PHASER_IN phase locking stage.
|
2684 |
|
|
// Must be de-asserted before Read Leveling
|
2685 |
|
|
//*****************************************************************
|
2686 |
|
|
|
2687 |
|
|
always @(posedge clk) begin
|
2688 |
|
|
if (rst || pi_calib_done_r1)
|
2689 |
|
|
read_calib_int <= #TCQ 1'b0;
|
2690 |
|
|
else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) &&
|
2691 |
|
|
(cnt_cmd_r == CNTNEXT_CMD))
|
2692 |
|
|
read_calib_int <= #TCQ 1'b1;
|
2693 |
|
|
end
|
2694 |
|
|
|
2695 |
|
|
always @(posedge clk)
|
2696 |
|
|
read_calib_r <= #TCQ read_calib_int;
|
2697 |
|
|
|
2698 |
|
|
|
2699 |
|
|
always @(posedge clk) begin
|
2700 |
|
|
if (rst || pi_calib_done_r1)
|
2701 |
|
|
read_calib <= #TCQ 1'b0;
|
2702 |
|
|
else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS))
|
2703 |
|
|
read_calib <= #TCQ 1'b1;
|
2704 |
|
|
end
|
2705 |
|
|
|
2706 |
|
|
|
2707 |
|
|
always @(posedge clk)
|
2708 |
|
|
if (rst)
|
2709 |
|
|
pi_calib_done_r <= #TCQ 1'b0;
|
2710 |
|
|
else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1))
|
2711 |
|
|
pi_calib_done_r <= #TCQ 1'b1;
|
2712 |
|
|
|
2713 |
|
|
always @(posedge clk)
|
2714 |
|
|
if (rst)
|
2715 |
|
|
pi_calib_rank_done_r <= #TCQ 1'b0;
|
2716 |
|
|
else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)
|
2717 |
|
|
pi_calib_rank_done_r <= #TCQ 1'b1;
|
2718 |
|
|
else
|
2719 |
|
|
pi_calib_rank_done_r <= #TCQ 1'b0;
|
2720 |
|
|
|
2721 |
|
|
always @(posedge clk) begin
|
2722 |
|
|
if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r))
|
2723 |
|
|
pi_phaselock_timer <= #TCQ 'd0;
|
2724 |
|
|
else if (((init_state_r == INIT_PI_PHASELOCK_READS) &&
|
2725 |
|
|
(pi_phaselock_timer != PHASELOCKED_TIMEOUT)) ||
|
2726 |
|
|
tg_timer_go)
|
2727 |
|
|
pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1;
|
2728 |
|
|
else
|
2729 |
|
|
pi_phaselock_timer <= #TCQ pi_phaselock_timer;
|
2730 |
|
|
end
|
2731 |
|
|
|
2732 |
|
|
assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0;
|
2733 |
|
|
|
2734 |
|
|
//*****************************************************************
|
2735 |
|
|
// DDR3 final burst length programming done. For DDR3 during
|
2736 |
|
|
// calibration the burst length is fixed to BL8. After calibration
|
2737 |
|
|
// the correct burst length is programmed.
|
2738 |
|
|
//*****************************************************************
|
2739 |
|
|
always @(posedge clk)
|
2740 |
|
|
if (rst)
|
2741 |
|
|
ddr3_lm_done_r <= #TCQ 1'b0;
|
2742 |
|
|
else if ((init_state_r == INIT_LOAD_MR_WAIT) &&
|
2743 |
|
|
(chip_cnt_r == RANKS-1) && wrcal_done)
|
2744 |
|
|
ddr3_lm_done_r <= #TCQ 1'b1;
|
2745 |
|
|
|
2746 |
|
|
always @(posedge clk) begin
|
2747 |
|
|
pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done;
|
2748 |
|
|
pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all;
|
2749 |
|
|
pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1;
|
2750 |
|
|
pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2;
|
2751 |
|
|
pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3;
|
2752 |
|
|
pi_dqs_found_all_r <= #TCQ pi_dqs_found_done;
|
2753 |
|
|
pi_calib_done_r1 <= #TCQ pi_calib_done_r;
|
2754 |
|
|
end
|
2755 |
|
|
|
2756 |
|
|
//***************************************************************************
|
2757 |
|
|
// Logic for deep memory (multi-rank) configurations
|
2758 |
|
|
//***************************************************************************
|
2759 |
|
|
|
2760 |
|
|
// For DDR3 asserted when
|
2761 |
|
|
|
2762 |
|
|
generate
|
2763 |
|
|
if (RANKS < 2) begin: single_rank
|
2764 |
|
|
always @(posedge clk)
|
2765 |
|
|
chip_cnt_r <= #TCQ 2'b00;
|
2766 |
|
|
end else begin: dual_rank
|
2767 |
|
|
always @(posedge clk)
|
2768 |
|
|
if (rst ||
|
2769 |
|
|
// Set chip_cnt_r to 2'b00 after both Ranks are read leveled
|
2770 |
|
|
(rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) ||
|
2771 |
|
|
// Set chip_cnt_r to 2'b00 after both Ranks are write leveled
|
2772 |
|
|
(wrlvl_done_r &&
|
2773 |
|
|
(init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin
|
2774 |
|
|
chip_cnt_r <= #TCQ 2'b00;
|
2775 |
|
|
end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&
|
2776 |
|
|
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) &&
|
2777 |
|
|
(DRAM_TYPE == "DDR3")) ||
|
2778 |
|
|
((init_state_r==INIT_REFRESH_RNK2_WAIT) &&
|
2779 |
|
|
(cnt_cmd_r=='d36)) ||
|
2780 |
|
|
//mpr_rnk_done ||
|
2781 |
|
|
//(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) ||
|
2782 |
|
|
//(stg1_wr_done && (init_state_r == INIT_REFRESH) &&
|
2783 |
|
|
//~(rnk_ref_cnt && rdlvl_last_byte_done)) ||
|
2784 |
|
|
|
2785 |
|
|
// Increment chip_cnt_r to issue Refresh to second rank
|
2786 |
|
|
(~pi_dqs_found_all_r &&
|
2787 |
|
|
(init_state_r==INIT_PRECHARGE_PREWAIT) &&
|
2788 |
|
|
(cnt_cmd_r=='d36)) ||
|
2789 |
|
|
|
2790 |
|
|
// Increment chip_cnt_r when DQSFOUND done for the Rank
|
2791 |
|
|
(pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) ||
|
2792 |
|
|
((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r
|
2793 |
|
|
&& wrcal_done) ||
|
2794 |
|
|
((init_state_r == INIT_DDR2_MULTI_RANK)
|
2795 |
|
|
&& (DRAM_TYPE == "DDR2"))) begin
|
2796 |
|
|
if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done ||
|
2797 |
|
|
// condition to increment chip_cnt during
|
2798 |
|
|
// final burst length programming for DDR3
|
2799 |
|
|
~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done ||
|
2800 |
|
|
&& (chip_cnt_r != RANKS-1))
|
2801 |
|
|
chip_cnt_r <= #TCQ chip_cnt_r + 1;
|
2802 |
|
|
else
|
2803 |
|
|
chip_cnt_r <= #TCQ 2'b00;
|
2804 |
|
|
end
|
2805 |
|
|
end
|
2806 |
|
|
endgenerate
|
2807 |
|
|
// verilint STARC-2.2.3.3 off
|
2808 |
|
|
generate
|
2809 |
|
|
if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank
|
2810 |
|
|
always @(posedge clk) begin
|
2811 |
|
|
if (rst)
|
2812 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2813 |
|
|
else if (init_state_r == INIT_REG_WRITE) begin
|
2814 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2815 |
|
|
if(!(CWL_M%2)) begin
|
2816 |
|
|
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
|
2817 |
|
|
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
|
2818 |
|
|
end else begin
|
2819 |
|
|
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
|
2820 |
|
|
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
|
2821 |
|
|
end
|
2822 |
|
|
end else if ((init_state_r == INIT_LOAD_MR) ||
|
2823 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
2824 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
2825 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
2826 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
2827 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
2828 |
|
|
(init_state_r == INIT_ZQCL) ||
|
2829 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
2830 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
2831 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
2832 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
2833 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
2834 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
2835 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
2836 |
|
|
(init_state_r == INIT_REFRESH) ||
|
2837 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
2838 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
2839 |
|
|
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
|
2840 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2841 |
|
|
if (!(CWL_M % 2)) //even CWL
|
2842 |
|
|
phy_int_cs_n[0] <= #TCQ 1'b0;
|
2843 |
|
|
else // odd CWL
|
2844 |
|
|
phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0;
|
2845 |
|
|
end else
|
2846 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2847 |
|
|
end
|
2848 |
|
|
end else if (RANKS == 1) begin: DDR3_1rank
|
2849 |
|
|
always @(posedge clk) begin
|
2850 |
|
|
if (rst)
|
2851 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2852 |
|
|
else if ((init_state_r == INIT_LOAD_MR) ||
|
2853 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
2854 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
2855 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
2856 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
2857 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
2858 |
|
|
(init_state_r == INIT_ZQCL) ||
|
2859 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
2860 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
2861 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
2862 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
2863 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
2864 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
2865 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
2866 |
|
|
(init_state_r == INIT_REFRESH) ||
|
2867 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
2868 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
2869 |
|
|
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
|
2870 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2871 |
|
|
if (!(CWL_M % 2)) begin //even CWL
|
2872 |
|
|
for (n = 0; n < nCS_PER_RANK; n = n + 1) begin
|
2873 |
|
|
phy_int_cs_n[n] <= #TCQ 1'b0;
|
2874 |
|
|
end
|
2875 |
|
|
end else begin //odd CWL
|
2876 |
|
|
for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin
|
2877 |
|
|
phy_int_cs_n[p] <= #TCQ 1'b0;
|
2878 |
|
|
end
|
2879 |
|
|
end
|
2880 |
|
|
end else
|
2881 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2882 |
|
|
end
|
2883 |
|
|
end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank
|
2884 |
|
|
always @(posedge clk) begin
|
2885 |
|
|
if (rst)
|
2886 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2887 |
|
|
else if (init_state_r == INIT_REG_WRITE) begin
|
2888 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2889 |
|
|
if(!(CWL_M%2)) begin
|
2890 |
|
|
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
|
2891 |
|
|
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
|
2892 |
|
|
end else begin
|
2893 |
|
|
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
|
2894 |
|
|
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
|
2895 |
|
|
end
|
2896 |
|
|
end else begin
|
2897 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2898 |
|
|
case (chip_cnt_r)
|
2899 |
|
|
2'b00:begin
|
2900 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
2901 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
2902 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
2903 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
2904 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
2905 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
2906 |
|
|
(init_state_r == INIT_ZQCL) ||
|
2907 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
2908 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
2909 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
2910 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
2911 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
2912 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
2913 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
2914 |
|
|
(init_state_r == INIT_REFRESH) ||
|
2915 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
2916 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
2917 |
|
|
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
|
2918 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2919 |
|
|
if (!(CWL_M % 2)) //even CWL
|
2920 |
|
|
phy_int_cs_n[0] <= #TCQ 1'b0;
|
2921 |
|
|
else // odd CWL
|
2922 |
|
|
phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;
|
2923 |
|
|
end else
|
2924 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2925 |
|
|
//for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
|
2926 |
|
|
//
|
2927 |
|
|
// phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
|
2928 |
|
|
//end
|
2929 |
|
|
end
|
2930 |
|
|
2'b01:begin
|
2931 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
2932 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
2933 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
2934 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
2935 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
2936 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
2937 |
|
|
(init_state_r == INIT_ZQCL) ||
|
2938 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
2939 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
2940 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
2941 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
2942 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
2943 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
2944 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
2945 |
|
|
(init_state_r == INIT_REFRESH) ||
|
2946 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
2947 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
2948 |
|
|
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
|
2949 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2950 |
|
|
if (!(CWL_M % 2)) //even CWL
|
2951 |
|
|
phy_int_cs_n[1] <= #TCQ 1'b0;
|
2952 |
|
|
else // odd CWL
|
2953 |
|
|
phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;
|
2954 |
|
|
end else
|
2955 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2956 |
|
|
//for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
|
2957 |
|
|
//
|
2958 |
|
|
// phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
|
2959 |
|
|
//end
|
2960 |
|
|
end
|
2961 |
|
|
endcase
|
2962 |
|
|
end
|
2963 |
|
|
end
|
2964 |
|
|
end else if (RANKS == 2) begin: DDR3_2rank
|
2965 |
|
|
always @(posedge clk) begin
|
2966 |
|
|
if (rst)
|
2967 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2968 |
|
|
else if (init_state_r == INIT_REG_WRITE) begin
|
2969 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2970 |
|
|
if(!(CWL_M%2)) begin
|
2971 |
|
|
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
|
2972 |
|
|
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
|
2973 |
|
|
end else begin
|
2974 |
|
|
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
|
2975 |
|
|
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
|
2976 |
|
|
end
|
2977 |
|
|
end else begin
|
2978 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
2979 |
|
|
case (chip_cnt_r)
|
2980 |
|
|
2'b00:begin
|
2981 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
2982 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
2983 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
2984 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
2985 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
2986 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
2987 |
|
|
(init_state_r == INIT_ZQCL) ||
|
2988 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
2989 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
2990 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
2991 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
2992 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
2993 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
2994 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
2995 |
|
|
(init_state_r == INIT_REFRESH) ||
|
2996 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
2997 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
2998 |
|
|
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
|
2999 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
3000 |
|
|
if (!(CWL_M % 2)) begin //even CWL
|
3001 |
|
|
for (n = 0; n < nCS_PER_RANK; n = n + 1) begin
|
3002 |
|
|
phy_int_cs_n[n] <= #TCQ 1'b0;
|
3003 |
|
|
end
|
3004 |
|
|
end else begin // odd CWL
|
3005 |
|
|
for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin
|
3006 |
|
|
phy_int_cs_n[p] <= #TCQ 1'b0;
|
3007 |
|
|
end
|
3008 |
|
|
end
|
3009 |
|
|
end else
|
3010 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
3011 |
|
|
//for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
|
3012 |
|
|
//
|
3013 |
|
|
// phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
|
3014 |
|
|
//end
|
3015 |
|
|
end
|
3016 |
|
|
2'b01:begin
|
3017 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
3018 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
3019 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
3020 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
3021 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
3022 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
3023 |
|
|
(init_state_r == INIT_ZQCL) ||
|
3024 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
3025 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
3026 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
3027 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
3028 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
3029 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
3030 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
3031 |
|
|
(init_state_r == INIT_REFRESH) ||
|
3032 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
3033 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
3034 |
|
|
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
|
3035 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
3036 |
|
|
if (!(CWL_M % 2)) begin //even CWL
|
3037 |
|
|
for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin
|
3038 |
|
|
phy_int_cs_n[q] <= #TCQ 1'b0;
|
3039 |
|
|
end
|
3040 |
|
|
end else begin // odd CWL
|
3041 |
|
|
for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin
|
3042 |
|
|
phy_int_cs_n[m] <= #TCQ 1'b0;
|
3043 |
|
|
end
|
3044 |
|
|
end
|
3045 |
|
|
end else
|
3046 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
3047 |
|
|
//for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
|
3048 |
|
|
//
|
3049 |
|
|
// phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
|
3050 |
|
|
//end
|
3051 |
|
|
end
|
3052 |
|
|
endcase
|
3053 |
|
|
end
|
3054 |
|
|
end // always @ (posedge clk)
|
3055 |
|
|
end
|
3056 |
|
|
// verilint STARC-2.2.3.3 on
|
3057 |
|
|
// commented out for now. Need it for DDR2 2T timing
|
3058 |
|
|
/* end else begin: DDR2
|
3059 |
|
|
always @(posedge clk)
|
3060 |
|
|
if (rst) begin
|
3061 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
3062 |
|
|
end else begin
|
3063 |
|
|
if (init_state_r == INIT_REG_WRITE) begin
|
3064 |
|
|
// All ranks selected simultaneously
|
3065 |
|
|
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
|
3066 |
|
|
end else if ((wrlvl_odt) ||
|
3067 |
|
|
(init_state_r == INIT_LOAD_MR) ||
|
3068 |
|
|
(init_state_r == INIT_ZQCL) ||
|
3069 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
3070 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
3071 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
3072 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
3073 |
|
|
(init_state_r == INIT_PI_PHASELOCK_READS) ||
|
3074 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
3075 |
|
|
(init_state_r == INIT_RDLVL_STG1_READ) ||
|
3076 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
3077 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ) ||
|
3078 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
3079 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
3080 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
3081 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
3082 |
|
|
(init_state_r == INIT_REFRESH)) begin
|
3083 |
|
|
phy_int_cs_n[0] <= #TCQ 1'b0;
|
3084 |
|
|
end
|
3085 |
|
|
else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
|
3086 |
|
|
end // else: !if(rst)
|
3087 |
|
|
end // block: DDR2 */
|
3088 |
|
|
endgenerate
|
3089 |
|
|
|
3090 |
|
|
assign phy_cs_n = phy_int_cs_n;
|
3091 |
|
|
|
3092 |
|
|
//***************************************************************************
|
3093 |
|
|
// Write/read burst logic for calibration
|
3094 |
|
|
//***************************************************************************
|
3095 |
|
|
|
3096 |
|
|
assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) ||
|
3097 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
3098 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
3099 |
|
|
(init_state_r == INIT_WRCAL_WRITE);
|
3100 |
|
|
assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) ||
|
3101 |
|
|
(init_state_r == INIT_RDLVL_STG1_READ) ||
|
3102 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
|
3103 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ) ||
|
3104 |
|
|
(init_state_r == INIT_OCLKDELAY_READ) ||
|
3105 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
3106 |
|
|
(init_state_r == INIT_MPR_READ) ||
|
3107 |
|
|
(init_state_r == INIT_WRCAL_MULT_READS);
|
3108 |
|
|
assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;
|
3109 |
|
|
assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering
|
3110 |
|
|
// assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE);
|
3111 |
|
|
|
3112 |
|
|
//***************************************************************************
|
3113 |
|
|
// Address generation and logic to count # of writes/reads issued during
|
3114 |
|
|
// certain stages of calibration
|
3115 |
|
|
//***************************************************************************
|
3116 |
|
|
|
3117 |
|
|
// Column address generation logic:
|
3118 |
|
|
// Keep track of the current column address - since all bursts are in
|
3119 |
|
|
// increments of 8 only during calibration, we need to keep track of
|
3120 |
|
|
// addresses [COL_WIDTH-1:3], lower order address bits will always = 0
|
3121 |
|
|
|
3122 |
|
|
always @(posedge clk)
|
3123 |
|
|
if (rst || wrcal_done)
|
3124 |
|
|
burst_addr_r <= #TCQ 1'b0;
|
3125 |
|
|
else if ((init_state_r == INIT_WRCAL_ACT_WAIT) ||
|
3126 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT_WAIT) ||
|
3127 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE) ||
|
3128 |
|
|
(init_state_r == INIT_OCLKDELAY_READ) ||
|
3129 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
3130 |
|
|
(init_state_r == INIT_WRCAL_WRITE_READ) ||
|
3131 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
3132 |
|
|
(init_state_r == INIT_WRCAL_MULT_READS) ||
|
3133 |
|
|
(init_state_r == INIT_WRCAL_READ_WAIT))
|
3134 |
|
|
burst_addr_r <= #TCQ 1'b1;
|
3135 |
|
|
else if (rdlvl_wr_rd && new_burst_r)
|
3136 |
|
|
burst_addr_r <= #TCQ ~burst_addr_r;
|
3137 |
|
|
else
|
3138 |
|
|
burst_addr_r <= #TCQ 1'b0;
|
3139 |
|
|
|
3140 |
|
|
// Read Level Stage 1 requires writes to the entire row since
|
3141 |
|
|
// a PRBS pattern is being written. This counter keeps track
|
3142 |
|
|
// of the number of writes which depends on the column width
|
3143 |
|
|
// The (stg1_wr_rd_cnt==9'd0) condition was added so the col
|
3144 |
|
|
// address wraps around during stage1 reads
|
3145 |
|
|
always @(posedge clk)
|
3146 |
|
|
if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) &&
|
3147 |
|
|
~rdlvl_stg1_done))
|
3148 |
|
|
stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD;
|
3149 |
|
|
else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) ||
|
3150 |
|
|
(prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||
|
3151 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin
|
3152 |
|
|
if (~complex_row0_wr_done || wr_victim_inc ||
|
3153 |
|
|
(complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done))))
|
3154 |
|
|
stg1_wr_rd_cnt <= #TCQ 'd127;
|
3155 |
|
|
else
|
3156 |
|
|
stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22;
|
3157 |
|
|
end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full)
|
3158 |
|
|
||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done))
|
3159 |
|
|
stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1;
|
3160 |
|
|
|
3161 |
|
|
always @(posedge clk)
|
3162 |
|
|
if (rst)
|
3163 |
|
|
wr_victim_inc <= #TCQ 1'b0;
|
3164 |
|
|
else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done)
|
3165 |
|
|
wr_victim_inc <= #TCQ 1'b1;
|
3166 |
|
|
else
|
3167 |
|
|
wr_victim_inc <= #TCQ 1'b0;
|
3168 |
|
|
|
3169 |
|
|
always @(posedge clk)
|
3170 |
|
|
reset_rd_addr_r1 <= #TCQ reset_rd_addr;
|
3171 |
|
|
|
3172 |
|
|
generate
|
3173 |
|
|
if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate
|
3174 |
|
|
always @(posedge clk)
|
3175 |
|
|
if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done)
|
3176 |
|
|
complex_row_cnt <= #TCQ 'd0;
|
3177 |
|
|
else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
3178 |
|
|
(complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) ||
|
3179 |
|
|
complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin
|
3180 |
|
|
// During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22
|
3181 |
|
|
if ((complex_row_cnt < DQ_WIDTH*2-1) && ~stg1_wr_done)
|
3182 |
|
|
complex_row_cnt <= #TCQ complex_row_cnt + 1;
|
3183 |
|
|
// During reads row count requires different conditions for increments
|
3184 |
|
|
else if (stg1_wr_done) begin
|
3185 |
|
|
if (reset_rd_addr_r1)
|
3186 |
|
|
complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16;
|
3187 |
|
|
// When looping multiple times in the same victim bit in a byte
|
3188 |
|
|
else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc)
|
3189 |
|
|
complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16 + rd_victim_sel*2;
|
3190 |
|
|
// When looping through victim bits within a byte
|
3191 |
|
|
else if (complex_row_cnt < pi_stg2_prbs_rdlvl_cnt*16+15)
|
3192 |
|
|
complex_row_cnt <= #TCQ complex_row_cnt + 1;
|
3193 |
|
|
// When the number of samples is done and tap is incremented within a byte
|
3194 |
|
|
else
|
3195 |
|
|
complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16;
|
3196 |
|
|
end
|
3197 |
|
|
end
|
3198 |
|
|
end else begin: row_cnt_victim_fixed
|
3199 |
|
|
always @(posedge clk)
|
3200 |
|
|
if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done)
|
3201 |
|
|
complex_row_cnt <= #TCQ 'd0;
|
3202 |
|
|
else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req))
|
3203 |
|
|
complex_row_cnt <= #TCQ 'd1;
|
3204 |
|
|
else
|
3205 |
|
|
complex_row_cnt <= #TCQ 'd0;
|
3206 |
|
|
end
|
3207 |
|
|
endgenerate
|
3208 |
|
|
|
3209 |
|
|
//row count
|
3210 |
|
|
|
3211 |
|
|
always @(posedge clk)
|
3212 |
|
|
if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done)
|
3213 |
|
|
complex_row_cnt_ocal <= #TCQ 'd0;
|
3214 |
|
|
else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) ||
|
3215 |
|
|
(complex_sample_cnt_inc_r2) || wr_victim_inc)) begin
|
3216 |
|
|
// During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22
|
3217 |
|
|
if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin
|
3218 |
|
|
complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1;
|
3219 |
|
|
end
|
3220 |
|
|
end
|
3221 |
|
|
|
3222 |
|
|
always @(posedge clk)
|
3223 |
|
|
if (rst)
|
3224 |
|
|
complex_odt_ext <= #TCQ 1'b0;
|
3225 |
|
|
else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE))
|
3226 |
|
|
complex_odt_ext <= #TCQ 1'b0;
|
3227 |
|
|
else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE))
|
3228 |
|
|
complex_odt_ext <= #TCQ 1'b1;
|
3229 |
|
|
|
3230 |
|
|
always @(posedge clk)
|
3231 |
|
|
if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1))) begin
|
3232 |
|
|
wr_victim_sel <= #TCQ 'd0;
|
3233 |
|
|
wr_byte_cnt <= #TCQ 'd0;
|
3234 |
|
|
end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin
|
3235 |
|
|
wr_victim_sel <= #TCQ wr_victim_sel + 1;
|
3236 |
|
|
if (wr_victim_sel == 'd7)
|
3237 |
|
|
wr_byte_cnt <= #TCQ wr_byte_cnt + 1;
|
3238 |
|
|
end
|
3239 |
|
|
|
3240 |
|
|
always @(posedge clk)
|
3241 |
|
|
if (rst) begin
|
3242 |
|
|
wr_victim_sel_ocal <= #TCQ 'd0;
|
3243 |
|
|
end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin
|
3244 |
|
|
wr_victim_sel_ocal <= #TCQ 'd0;
|
3245 |
|
|
end else if (prbs_rdlvl_done && wr_victim_inc) begin
|
3246 |
|
|
wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1;
|
3247 |
|
|
end
|
3248 |
|
|
|
3249 |
|
|
always @(posedge clk)
|
3250 |
|
|
if (rst) begin
|
3251 |
|
|
victim_sel <= #TCQ 'd0;
|
3252 |
|
|
victim_byte_cnt <= #TCQ 'd0;
|
3253 |
|
|
end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin
|
3254 |
|
|
victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel;
|
3255 |
|
|
victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:wr_byte_cnt;
|
3256 |
|
|
end else begin
|
3257 |
|
|
if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr)
|
3258 |
|
|
victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel;
|
3259 |
|
|
victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:pi_stg2_prbs_rdlvl_cnt;
|
3260 |
|
|
end
|
3261 |
|
|
|
3262 |
|
|
generate
|
3263 |
|
|
if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate
|
3264 |
|
|
always @(posedge clk)
|
3265 |
|
|
if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) ||
|
3266 |
|
|
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
|
3267 |
|
|
complex_byte_rd_done || prbs_rdlvl_done_pulse) begin
|
3268 |
|
|
complex_row0_wr_done <= #TCQ 1'b0;
|
3269 |
|
|
end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin
|
3270 |
|
|
complex_row0_wr_done <= #TCQ 1'b1;
|
3271 |
|
|
end
|
3272 |
|
|
|
3273 |
|
|
always @(posedge clk)
|
3274 |
|
|
if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) ||
|
3275 |
|
|
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
|
3276 |
|
|
complex_byte_rd_done || prbs_rdlvl_done_pulse) begin
|
3277 |
|
|
complex_row1_wr_done <= #TCQ 1'b0;
|
3278 |
|
|
end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin
|
3279 |
|
|
complex_row1_wr_done <= #TCQ 1'b1;
|
3280 |
|
|
end
|
3281 |
|
|
end else begin: wr_done_victim_fixed
|
3282 |
|
|
always @(posedge clk)
|
3283 |
|
|
if (rst || prbs_rdlvl_done_pulse ||
|
3284 |
|
|
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
|
3285 |
|
|
complex_byte_rd_done ) begin
|
3286 |
|
|
complex_row0_wr_done <= #TCQ 1'b0;
|
3287 |
|
|
end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin
|
3288 |
|
|
complex_row0_wr_done <= #TCQ 1'b1;
|
3289 |
|
|
end
|
3290 |
|
|
|
3291 |
|
|
always @(posedge clk)
|
3292 |
|
|
if (rst || prbs_rdlvl_done_pulse ||
|
3293 |
|
|
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
|
3294 |
|
|
complex_byte_rd_done ) begin
|
3295 |
|
|
complex_row1_wr_done <= #TCQ 1'b0;
|
3296 |
|
|
end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin
|
3297 |
|
|
complex_row1_wr_done <= #TCQ 1'b1;
|
3298 |
|
|
end
|
3299 |
|
|
end
|
3300 |
|
|
endgenerate
|
3301 |
|
|
|
3302 |
|
|
always @(posedge clk)
|
3303 |
|
|
if (rst || prbs_rdlvl_done_pulse)
|
3304 |
|
|
complex_row0_rd_done <= #TCQ 1'b0;
|
3305 |
|
|
else if (complex_sample_cnt_inc)
|
3306 |
|
|
complex_row0_rd_done <= #TCQ 1'b0;
|
3307 |
|
|
else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done)
|
3308 |
|
|
complex_row0_rd_done <= #TCQ 1'b1;
|
3309 |
|
|
|
3310 |
|
|
always @(posedge clk)
|
3311 |
|
|
complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done;
|
3312 |
|
|
|
3313 |
|
|
always @(posedge clk)
|
3314 |
|
|
if (rst || prbs_rdlvl_done_pulse)
|
3315 |
|
|
complex_row1_rd_done <= #TCQ 1'b0;
|
3316 |
|
|
else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE))
|
3317 |
|
|
complex_row1_rd_done <= #TCQ 1'b0;
|
3318 |
|
|
else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2))
|
3319 |
|
|
complex_row1_rd_done <= #TCQ 1'b1;
|
3320 |
|
|
|
3321 |
|
|
always @(posedge clk)
|
3322 |
|
|
complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done;
|
3323 |
|
|
|
3324 |
|
|
//calculate row rd num for complex_oclkdelay_calib
|
3325 |
|
|
//once it reached to 8
|
3326 |
|
|
always @ (posedge clk)
|
3327 |
|
|
if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0;
|
3328 |
|
|
else
|
3329 |
|
|
complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ?
|
3330 |
|
|
((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1)
|
3331 |
|
|
: complex_row1_rd_cnt;
|
3332 |
|
|
//For write, reset rd_done for the byte
|
3333 |
|
|
always @ (posedge clk) begin
|
3334 |
|
|
if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse)
|
3335 |
|
|
complex_byte_rd_done <= #TCQ 'b0;
|
3336 |
|
|
else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1))
|
3337 |
|
|
complex_byte_rd_done <= #TCQ 'b1;
|
3338 |
|
|
end
|
3339 |
|
|
|
3340 |
|
|
always @ (posedge clk) begin
|
3341 |
|
|
complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done;
|
3342 |
|
|
complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1);
|
3343 |
|
|
end
|
3344 |
|
|
|
3345 |
|
|
generate
|
3346 |
|
|
if (RANKS < 2) begin: one_rank_complex
|
3347 |
|
|
always @(posedge clk)
|
3348 |
|
|
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) ||
|
3349 |
|
|
(complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse )
|
3350 |
|
|
complex_wr_done <= #TCQ 1'b0;
|
3351 |
|
|
else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
|
3352 |
|
|
complex_wr_done <= #TCQ 1'b1;
|
3353 |
|
|
else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
|
3354 |
|
|
complex_wr_done <= #TCQ 1'b1;
|
3355 |
|
|
end else begin: dual_rank_complex
|
3356 |
|
|
always @(posedge clk)
|
3357 |
|
|
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) ||
|
3358 |
|
|
(rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse )
|
3359 |
|
|
complex_wr_done <= #TCQ 1'b0;
|
3360 |
|
|
else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
|
3361 |
|
|
complex_wr_done <= #TCQ 1'b1;
|
3362 |
|
|
else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
|
3363 |
|
|
complex_wr_done <= #TCQ 1'b1;
|
3364 |
|
|
end
|
3365 |
|
|
endgenerate
|
3366 |
|
|
|
3367 |
|
|
always @(posedge clk)
|
3368 |
|
|
if (rst)
|
3369 |
|
|
complex_wait_cnt <= #TCQ 'd0;
|
3370 |
|
|
else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) ||
|
3371 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
3372 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) ||
|
3373 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) ||
|
3374 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ||
|
3375 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15)
|
3376 |
|
|
complex_wait_cnt <= #TCQ complex_wait_cnt + 1;
|
3377 |
|
|
else
|
3378 |
|
|
complex_wait_cnt <= #TCQ 'd0;
|
3379 |
|
|
|
3380 |
|
|
always @(posedge clk)
|
3381 |
|
|
if (rst) begin
|
3382 |
|
|
complex_num_reads <= #TCQ 'd1;
|
3383 |
|
|
end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) ||
|
3384 |
|
|
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) &&
|
3385 |
|
|
~complex_row0_rd_done) begin
|
3386 |
|
|
if (stg1_wr_rd_cnt > 'd85) begin
|
3387 |
|
|
if (complex_num_reads < 'd6)
|
3388 |
|
|
complex_num_reads <= #TCQ complex_num_reads + 1;
|
3389 |
|
|
else
|
3390 |
|
|
complex_num_reads <= #TCQ 'd1;
|
3391 |
|
|
// Initila value for VCCAUX pattern is 3, 7, and 12
|
3392 |
|
|
end else if (stg1_wr_rd_cnt > 'd73) begin
|
3393 |
|
|
if (stg1_wr_rd_cnt == 'd85)
|
3394 |
|
|
complex_num_reads <= #TCQ 'd3;
|
3395 |
|
|
else if (complex_num_reads < 'd5)
|
3396 |
|
|
complex_num_reads <= #TCQ complex_num_reads + 1;
|
3397 |
|
|
end else if (stg1_wr_rd_cnt > 'd39) begin
|
3398 |
|
|
if (stg1_wr_rd_cnt == 'd73)
|
3399 |
|
|
complex_num_reads <= #TCQ 'd7;
|
3400 |
|
|
else if (complex_num_reads < 'd10)
|
3401 |
|
|
complex_num_reads <= #TCQ complex_num_reads + 1;
|
3402 |
|
|
end else begin
|
3403 |
|
|
if (stg1_wr_rd_cnt == 'd39)
|
3404 |
|
|
complex_num_reads <= #TCQ 'd12;
|
3405 |
|
|
else if (complex_num_reads < 'd14)
|
3406 |
|
|
complex_num_reads <= #TCQ complex_num_reads + 1;
|
3407 |
|
|
end
|
3408 |
|
|
// Initialize to 1 at the start of reads or after precharge and activate
|
3409 |
|
|
end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) ||
|
3410 |
|
|
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22)))
|
3411 |
|
|
complex_num_reads <= #TCQ 'd1;
|
3412 |
|
|
|
3413 |
|
|
always @(posedge clk)
|
3414 |
|
|
if (rst)
|
3415 |
|
|
complex_num_reads_dec <= #TCQ 'd1;
|
3416 |
|
|
else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) ||
|
3417 |
|
|
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)))
|
3418 |
|
|
complex_num_reads_dec <= #TCQ complex_num_reads;
|
3419 |
|
|
else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0))
|
3420 |
|
|
complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1;
|
3421 |
|
|
|
3422 |
|
|
always @(posedge clk)
|
3423 |
|
|
if (rst)
|
3424 |
|
|
complex_address <= #TCQ 'd0;
|
3425 |
|
|
else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) ||
|
3426 |
|
|
((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT)))
|
3427 |
|
|
complex_address <= #TCQ phy_address[COL_WIDTH-1:0];
|
3428 |
|
|
|
3429 |
|
|
|
3430 |
|
|
always @ (posedge clk)
|
3431 |
|
|
if (rst)
|
3432 |
|
|
complex_oclkdelay_calib_start_int <= #TCQ 'b0;
|
3433 |
|
|
else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26
|
3434 |
|
|
complex_oclkdelay_calib_start_int <= #TCQ 'b1;
|
3435 |
|
|
|
3436 |
|
|
always @(posedge clk) begin
|
3437 |
|
|
complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int;
|
3438 |
|
|
complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1;
|
3439 |
|
|
end
|
3440 |
|
|
|
3441 |
|
|
always @ (posedge clk)
|
3442 |
|
|
if (rst)
|
3443 |
|
|
complex_oclkdelay_calib_start <= #TCQ 'b0;
|
3444 |
|
|
else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26
|
3445 |
|
|
complex_oclkdelay_calib_start <= #TCQ 'b1;
|
3446 |
|
|
|
3447 |
|
|
//packet fragmentation for complex oclkdealy calib write
|
3448 |
|
|
always @(posedge clk)
|
3449 |
|
|
if (rst || prbs_rdlvl_done_pulse) begin
|
3450 |
|
|
complex_num_writes <= #TCQ 'd1;
|
3451 |
|
|
end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin
|
3452 |
|
|
if (stg1_wr_rd_cnt > 'd85) begin
|
3453 |
|
|
if (complex_num_writes < 'd6)
|
3454 |
|
|
complex_num_writes <= #TCQ complex_num_writes + 1;
|
3455 |
|
|
else
|
3456 |
|
|
complex_num_writes <= #TCQ 'd1;
|
3457 |
|
|
// Initila value for VCCAUX pattern is 3, 7, and 12
|
3458 |
|
|
end else if (stg1_wr_rd_cnt > 'd73) begin
|
3459 |
|
|
if (stg1_wr_rd_cnt == 'd85)
|
3460 |
|
|
complex_num_writes <= #TCQ 'd3;
|
3461 |
|
|
else if (complex_num_writes < 'd5)
|
3462 |
|
|
complex_num_writes <= #TCQ complex_num_writes + 1;
|
3463 |
|
|
end else if (stg1_wr_rd_cnt > 'd39) begin
|
3464 |
|
|
if (stg1_wr_rd_cnt == 'd73)
|
3465 |
|
|
complex_num_writes <= #TCQ 'd7;
|
3466 |
|
|
else if (complex_num_writes < 'd10)
|
3467 |
|
|
complex_num_writes <= #TCQ complex_num_writes + 1;
|
3468 |
|
|
end else begin
|
3469 |
|
|
if (stg1_wr_rd_cnt == 'd39)
|
3470 |
|
|
complex_num_writes <= #TCQ 'd12;
|
3471 |
|
|
else if (complex_num_writes < 'd14)
|
3472 |
|
|
complex_num_writes <= #TCQ complex_num_writes + 1;
|
3473 |
|
|
end
|
3474 |
|
|
// Initialize to 1 at the start of write or after precharge and activate
|
3475 |
|
|
end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done)
|
3476 |
|
|
complex_num_writes <= #TCQ 'd30;
|
3477 |
|
|
else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)
|
3478 |
|
|
complex_num_writes <= #TCQ 'd1;
|
3479 |
|
|
|
3480 |
|
|
always @(posedge clk)
|
3481 |
|
|
if (rst || prbs_rdlvl_done_pulse)
|
3482 |
|
|
complex_num_writes_dec <= #TCQ 'd1;
|
3483 |
|
|
else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) ||
|
3484 |
|
|
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)))
|
3485 |
|
|
complex_num_writes_dec <= #TCQ complex_num_writes;
|
3486 |
|
|
else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0))
|
3487 |
|
|
complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1;
|
3488 |
|
|
|
3489 |
|
|
always @(posedge clk)
|
3490 |
|
|
if (rst)
|
3491 |
|
|
complex_sample_cnt_inc_ocal <= #TCQ 1'b0;
|
3492 |
|
|
else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done)
|
3493 |
|
|
complex_sample_cnt_inc_ocal <= #TCQ 1'b1;
|
3494 |
|
|
else
|
3495 |
|
|
complex_sample_cnt_inc_ocal <= #TCQ 1'b0;
|
3496 |
|
|
|
3497 |
|
|
always @(posedge clk)
|
3498 |
|
|
if (rst)
|
3499 |
|
|
complex_sample_cnt_inc <= #TCQ 1'b0;
|
3500 |
|
|
else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done)
|
3501 |
|
|
complex_sample_cnt_inc <= #TCQ 1'b1;
|
3502 |
|
|
else
|
3503 |
|
|
complex_sample_cnt_inc <= #TCQ 1'b0;
|
3504 |
|
|
|
3505 |
|
|
always @(posedge clk) begin
|
3506 |
|
|
complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc;
|
3507 |
|
|
complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1;
|
3508 |
|
|
end
|
3509 |
|
|
|
3510 |
|
|
//complex refresh req
|
3511 |
|
|
always @ (posedge clk) begin
|
3512 |
|
|
if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
3513 |
|
|
(prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) )
|
3514 |
|
|
complex_ocal_ref_done <= #TCQ 1'b1;
|
3515 |
|
|
else if (init_state_r == INIT_RDLVL_STG1_WRITE)
|
3516 |
|
|
complex_ocal_ref_done <= #TCQ 1'b0;
|
3517 |
|
|
end
|
3518 |
|
|
|
3519 |
|
|
//complex ocal odt extention
|
3520 |
|
|
always @(posedge clk)
|
3521 |
|
|
if (rst)
|
3522 |
|
|
complex_ocal_odt_ext <= #TCQ 1'b0;
|
3523 |
|
|
else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT))
|
3524 |
|
|
complex_ocal_odt_ext <= #TCQ 1'b0;
|
3525 |
|
|
else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT))
|
3526 |
|
|
complex_ocal_odt_ext <= #TCQ 1'b1;
|
3527 |
|
|
|
3528 |
|
|
// OCLKDELAY calibration requires multiple writes because
|
3529 |
|
|
// write can be up to 2 cycles early since OCLKDELAY tap
|
3530 |
|
|
// can go down to 0
|
3531 |
|
|
always @(posedge clk)
|
3532 |
|
|
if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) ||
|
3533 |
|
|
(oclk_wr_cnt == 4'd0))
|
3534 |
|
|
oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD;
|
3535 |
|
|
else if ((init_state_r == INIT_OCLKDELAY_WRITE) &&
|
3536 |
|
|
new_burst_r && ~phy_data_full)
|
3537 |
|
|
oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1;
|
3538 |
|
|
|
3539 |
|
|
// Write calibration requires multiple writes because
|
3540 |
|
|
// write can be up to 2 cycles early due to new write
|
3541 |
|
|
// leveling algorithm to avoid late writes
|
3542 |
|
|
always @(posedge clk)
|
3543 |
|
|
if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) ||
|
3544 |
|
|
(wrcal_wr_cnt == 4'd0))
|
3545 |
|
|
wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD;
|
3546 |
|
|
else if ((init_state_r == INIT_WRCAL_WRITE) &&
|
3547 |
|
|
new_burst_r && ~phy_data_full)
|
3548 |
|
|
wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1;
|
3549 |
|
|
|
3550 |
|
|
|
3551 |
|
|
generate
|
3552 |
|
|
if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1
|
3553 |
|
|
// 4 back-to-back reads with gaps for
|
3554 |
|
|
// read data_offset calibration (rdlvl stage 2)
|
3555 |
|
|
always @(posedge clk)
|
3556 |
|
|
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
|
3557 |
|
|
num_reads <= #TCQ 3'b000;
|
3558 |
|
|
else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))
|
3559 |
|
|
num_reads <= #TCQ num_reads - 1;
|
3560 |
|
|
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full ||
|
3561 |
|
|
phy_cmd_full && new_burst_r)
|
3562 |
|
|
num_reads <= #TCQ 3'b011;
|
3563 |
|
|
end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1
|
3564 |
|
|
// 4 back-to-back reads with gaps for
|
3565 |
|
|
// read data_offset calibration (rdlvl stage 2)
|
3566 |
|
|
always @(posedge clk)
|
3567 |
|
|
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
|
3568 |
|
|
num_reads <= #TCQ 3'b000;
|
3569 |
|
|
else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))
|
3570 |
|
|
num_reads <= #TCQ num_reads - 1;
|
3571 |
|
|
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full ||
|
3572 |
|
|
phy_cmd_full && new_burst_r)
|
3573 |
|
|
num_reads <= #TCQ 3'b111;
|
3574 |
|
|
end
|
3575 |
|
|
endgenerate
|
3576 |
|
|
|
3577 |
|
|
// back-to-back reads during write calibration
|
3578 |
|
|
always @(posedge clk)
|
3579 |
|
|
if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT))
|
3580 |
|
|
wrcal_reads <= #TCQ 2'b00;
|
3581 |
|
|
else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full))
|
3582 |
|
|
wrcal_reads <= #TCQ wrcal_reads - 1;
|
3583 |
|
|
else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full ||
|
3584 |
|
|
phy_cmd_full && new_burst_r)
|
3585 |
|
|
wrcal_reads <= #TCQ 'd255;
|
3586 |
|
|
|
3587 |
|
|
// determine how often to issue row command during read leveling writes
|
3588 |
|
|
// and reads
|
3589 |
|
|
always @(posedge clk)
|
3590 |
|
|
if (rdlvl_wr_rd) begin
|
3591 |
|
|
// 2:1 mode - every other command issued is a data command
|
3592 |
|
|
// 4:1 mode - every command issued is a data command
|
3593 |
|
|
if (nCK_PER_CLK == 2) begin
|
3594 |
|
|
if (!phy_ctl_full)
|
3595 |
|
|
new_burst_r <= #TCQ ~new_burst_r;
|
3596 |
|
|
end else
|
3597 |
|
|
new_burst_r <= #TCQ 1'b1;
|
3598 |
|
|
end else
|
3599 |
|
|
new_burst_r <= #TCQ 1'b1;
|
3600 |
|
|
|
3601 |
|
|
// indicate when a write is occurring. PHY_WRDATA_EN must be asserted
|
3602 |
|
|
// simultaneous with the corresponding command/address for CWL = 5,6
|
3603 |
|
|
always @(posedge clk) begin
|
3604 |
|
|
rdlvl_wr_r <= #TCQ rdlvl_wr;
|
3605 |
|
|
calib_wrdata_en <= #TCQ phy_wrdata_en;
|
3606 |
|
|
end
|
3607 |
|
|
|
3608 |
|
|
always @(posedge clk) begin
|
3609 |
|
|
if (rst || wrcal_done)
|
3610 |
|
|
extend_cal_pat <= #TCQ 1'b0;
|
3611 |
|
|
else if (temp_lmr_done && (PRE_REV3ES == "ON"))
|
3612 |
|
|
extend_cal_pat <= #TCQ 1'b1;
|
3613 |
|
|
end
|
3614 |
|
|
|
3615 |
|
|
|
3616 |
|
|
generate
|
3617 |
|
|
if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4
|
3618 |
|
|
// Write data enable asserted for one DIV4 clock cycle
|
3619 |
|
|
// Only BL8 supported with DIV4. DDR2 BL4 will use DIV2.
|
3620 |
|
|
always @(*) begin
|
3621 |
|
|
if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
3622 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE) ||
|
3623 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
3624 |
|
|
(init_state_r == INIT_WRCAL_WRITE)))
|
3625 |
|
|
phy_wrdata_en = 1'b1;
|
3626 |
|
|
else
|
3627 |
|
|
phy_wrdata_en = 1'b0;
|
3628 |
|
|
end
|
3629 |
|
|
end else begin: wrdqen_div2 // block: wrdqen_div4
|
3630 |
|
|
always @(*)
|
3631 |
|
|
if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full)
|
3632 |
|
|
| phy_wrdata_en_r1)
|
3633 |
|
|
phy_wrdata_en = 1'b1;
|
3634 |
|
|
else
|
3635 |
|
|
phy_wrdata_en = 1'b0;
|
3636 |
|
|
|
3637 |
|
|
always @(posedge clk)
|
3638 |
|
|
phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r
|
3639 |
|
|
& ~phy_data_full;
|
3640 |
|
|
|
3641 |
|
|
always @(posedge clk) begin
|
3642 |
|
|
if (!phy_wrdata_en & first_rdlvl_pat_r)
|
3643 |
|
|
wrdata_pat_cnt <= #TCQ 2'b00;
|
3644 |
|
|
else if (wrdata_pat_cnt == 2'b11)
|
3645 |
|
|
wrdata_pat_cnt <= #TCQ 2'b10;
|
3646 |
|
|
else
|
3647 |
|
|
wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1;
|
3648 |
|
|
end
|
3649 |
|
|
|
3650 |
|
|
always @(posedge clk) begin
|
3651 |
|
|
if (!phy_wrdata_en & first_wrcal_pat_r)
|
3652 |
|
|
wrcal_pat_cnt <= #TCQ 2'b00;
|
3653 |
|
|
else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01))
|
3654 |
|
|
wrcal_pat_cnt <= #TCQ 2'b00;
|
3655 |
|
|
else if (wrcal_pat_cnt == 2'b11)
|
3656 |
|
|
wrcal_pat_cnt <= #TCQ 2'b10;
|
3657 |
|
|
else
|
3658 |
|
|
wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1;
|
3659 |
|
|
end
|
3660 |
|
|
|
3661 |
|
|
end
|
3662 |
|
|
endgenerate
|
3663 |
|
|
|
3664 |
|
|
|
3665 |
|
|
// indicate when a write is occurring. PHY_RDDATA_EN must be asserted
|
3666 |
|
|
// simultaneous with the corresponding command/address. PHY_RDDATA_EN
|
3667 |
|
|
// is used during read-leveling to determine read latency
|
3668 |
|
|
assign phy_rddata_en = ~phy_if_empty;
|
3669 |
|
|
|
3670 |
|
|
// Read data valid generation for MC and User Interface after calibration is
|
3671 |
|
|
// complete
|
3672 |
|
|
assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0;
|
3673 |
|
|
|
3674 |
|
|
//***************************************************************************
|
3675 |
|
|
// Generate training data written at start of each read-leveling stage
|
3676 |
|
|
// For every stage of read leveling, 8 words are written into memory
|
3677 |
|
|
// The format is as follows (shown as {rise,fall}):
|
3678 |
|
|
// Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0
|
3679 |
|
|
// Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
|
3680 |
|
|
//***************************************************************************
|
3681 |
|
|
|
3682 |
|
|
|
3683 |
|
|
always @(posedge clk)
|
3684 |
|
|
if ((init_state_r == INIT_IDLE) ||
|
3685 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE))
|
3686 |
|
|
cnt_init_data_r <= #TCQ 2'b00;
|
3687 |
|
|
else if (phy_wrdata_en)
|
3688 |
|
|
cnt_init_data_r <= #TCQ cnt_init_data_r + 1;
|
3689 |
|
|
else if (init_state_r == INIT_WRCAL_WRITE)
|
3690 |
|
|
cnt_init_data_r <= #TCQ 2'b10;
|
3691 |
|
|
|
3692 |
|
|
|
3693 |
|
|
// write different sequence for very
|
3694 |
|
|
// first write to memory only. Used to help us differentiate
|
3695 |
|
|
// if the writes are "early" or "on-time" during read leveling
|
3696 |
|
|
always @(posedge clk)
|
3697 |
|
|
if (rst || rdlvl_stg1_rank_done)
|
3698 |
|
|
first_rdlvl_pat_r <= #TCQ 1'b1;
|
3699 |
|
|
else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE))
|
3700 |
|
|
first_rdlvl_pat_r <= #TCQ 1'b0;
|
3701 |
|
|
|
3702 |
|
|
|
3703 |
|
|
always @(posedge clk)
|
3704 |
|
|
if (rst || wrcal_resume ||
|
3705 |
|
|
(init_state_r == INIT_WRCAL_ACT_WAIT))
|
3706 |
|
|
first_wrcal_pat_r <= #TCQ 1'b1;
|
3707 |
|
|
else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE))
|
3708 |
|
|
first_wrcal_pat_r <= #TCQ 1'b0;
|
3709 |
|
|
|
3710 |
|
|
generate
|
3711 |
|
|
if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first
|
3712 |
|
|
|
3713 |
|
|
always @(posedge clk)
|
3714 |
|
|
if (~oclkdelay_calib_done)
|
3715 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},
|
3716 |
|
|
{DQ_WIDTH/4{4'h0}},
|
3717 |
|
|
{DQ_WIDTH/4{4'hF}},
|
3718 |
|
|
{DQ_WIDTH/4{4'h0}}};
|
3719 |
|
|
else if (!rdlvl_stg1_done) begin
|
3720 |
|
|
// The 16 words for stage 1 write data in 2:1 mode is written
|
3721 |
|
|
// over 4 consecutive controller clock cycles. Note that write
|
3722 |
|
|
// data follows phy_wrdata_en by one clock cycle
|
3723 |
|
|
case (wrdata_pat_cnt)
|
3724 |
|
|
2'b00: begin
|
3725 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
|
3726 |
|
|
{DQ_WIDTH/4{4'h7}},
|
3727 |
|
|
{DQ_WIDTH/4{4'h3}},
|
3728 |
|
|
{DQ_WIDTH/4{4'h9}}};
|
3729 |
|
|
end
|
3730 |
|
|
|
3731 |
|
|
2'b01: begin
|
3732 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
|
3733 |
|
|
{DQ_WIDTH/4{4'h2}},
|
3734 |
|
|
{DQ_WIDTH/4{4'h9}},
|
3735 |
|
|
{DQ_WIDTH/4{4'hC}}};
|
3736 |
|
|
end
|
3737 |
|
|
|
3738 |
|
|
2'b10: begin
|
3739 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
|
3740 |
|
|
{DQ_WIDTH/4{4'h7}},
|
3741 |
|
|
{DQ_WIDTH/4{4'h1}},
|
3742 |
|
|
{DQ_WIDTH/4{4'hB}}};
|
3743 |
|
|
end
|
3744 |
|
|
|
3745 |
|
|
2'b11: begin
|
3746 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
|
3747 |
|
|
{DQ_WIDTH/4{4'h2}},
|
3748 |
|
|
{DQ_WIDTH/4{4'h9}},
|
3749 |
|
|
{DQ_WIDTH/4{4'hC}}};
|
3750 |
|
|
end
|
3751 |
|
|
endcase
|
3752 |
|
|
end else if (!prbs_rdlvl_done && ~phy_data_full) begin
|
3753 |
|
|
phy_wrdata <= #TCQ prbs_o;
|
3754 |
|
|
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
|
3755 |
|
|
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
|
3756 |
|
|
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},
|
3757 |
|
|
{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
|
3758 |
|
|
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},
|
3759 |
|
|
{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
|
3760 |
|
|
end else if (!wrcal_done) begin
|
3761 |
|
|
case (wrcal_pat_cnt)
|
3762 |
|
|
2'b00: begin
|
3763 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},
|
3764 |
|
|
{DQ_WIDTH/4{4'hA}},
|
3765 |
|
|
{DQ_WIDTH/4{4'h0}},
|
3766 |
|
|
{DQ_WIDTH/4{4'hF}}};
|
3767 |
|
|
end
|
3768 |
|
|
2'b01: begin
|
3769 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},
|
3770 |
|
|
{DQ_WIDTH/4{4'h9}},
|
3771 |
|
|
{DQ_WIDTH/4{4'hA}},
|
3772 |
|
|
{DQ_WIDTH/4{4'h5}}};
|
3773 |
|
|
end
|
3774 |
|
|
2'b10: begin
|
3775 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
|
3776 |
|
|
{DQ_WIDTH/4{4'hE}},
|
3777 |
|
|
{DQ_WIDTH/4{4'h1}},
|
3778 |
|
|
{DQ_WIDTH/4{4'hB}}};
|
3779 |
|
|
end
|
3780 |
|
|
2'b11: begin
|
3781 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},
|
3782 |
|
|
{DQ_WIDTH/4{4'hD}},
|
3783 |
|
|
{DQ_WIDTH/4{4'hE}},
|
3784 |
|
|
{DQ_WIDTH/4{4'h4}}};
|
3785 |
|
|
end
|
3786 |
|
|
endcase
|
3787 |
|
|
end
|
3788 |
|
|
|
3789 |
|
|
end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first
|
3790 |
|
|
|
3791 |
|
|
always @(posedge clk)
|
3792 |
|
|
if (~oclkdelay_calib_done)
|
3793 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
|
3794 |
|
|
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
|
3795 |
|
|
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
|
3796 |
|
|
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};
|
3797 |
|
|
else if (!rdlvl_stg1_done && ~phy_data_full)
|
3798 |
|
|
// write different sequence for very
|
3799 |
|
|
// first write to memory only. Used to help us differentiate
|
3800 |
|
|
// if the writes are "early" or "on-time" during read leveling
|
3801 |
|
|
if (first_rdlvl_pat_r)
|
3802 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
|
3803 |
|
|
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
|
3804 |
|
|
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
|
3805 |
|
|
{DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};
|
3806 |
|
|
else
|
3807 |
|
|
// For all others, change the first two words written in order
|
3808 |
|
|
// to differentiate the "early write" and "on-time write"
|
3809 |
|
|
// readback patterns during read leveling
|
3810 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
|
3811 |
|
|
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
|
3812 |
|
|
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
|
3813 |
|
|
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
|
3814 |
|
|
else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full)
|
3815 |
|
|
phy_wrdata <= #TCQ prbs_o;
|
3816 |
|
|
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
|
3817 |
|
|
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
|
3818 |
|
|
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},
|
3819 |
|
|
{DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},
|
3820 |
|
|
{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
|
3821 |
|
|
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
|
3822 |
|
|
else if (!wrcal_done)
|
3823 |
|
|
if (first_wrcal_pat_r)
|
3824 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
|
3825 |
|
|
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
|
3826 |
|
|
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
|
3827 |
|
|
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
|
3828 |
|
|
else
|
3829 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},
|
3830 |
|
|
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},
|
3831 |
|
|
{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},
|
3832 |
|
|
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
|
3833 |
|
|
|
3834 |
|
|
|
3835 |
|
|
end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first
|
3836 |
|
|
|
3837 |
|
|
always @(posedge clk)
|
3838 |
|
|
if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3"))
|
3839 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
|
3840 |
|
|
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
|
3841 |
|
|
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
|
3842 |
|
|
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};
|
3843 |
|
|
else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
|
3844 |
|
|
if (extend_cal_pat)
|
3845 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
|
3846 |
|
|
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
|
3847 |
|
|
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
|
3848 |
|
|
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
|
3849 |
|
|
else if (first_wrcal_pat_r)
|
3850 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
|
3851 |
|
|
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
|
3852 |
|
|
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
|
3853 |
|
|
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
|
3854 |
|
|
else
|
3855 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},
|
3856 |
|
|
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},
|
3857 |
|
|
{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},
|
3858 |
|
|
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
|
3859 |
|
|
end else if (!rdlvl_stg1_done && ~phy_data_full) begin
|
3860 |
|
|
// write different sequence for very
|
3861 |
|
|
// first write to memory only. Used to help us differentiate
|
3862 |
|
|
// if the writes are "early" or "on-time" during read leveling
|
3863 |
|
|
if (first_rdlvl_pat_r)
|
3864 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
|
3865 |
|
|
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
|
3866 |
|
|
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
|
3867 |
|
|
{DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};
|
3868 |
|
|
else
|
3869 |
|
|
// For all others, change the first two words written in order
|
3870 |
|
|
// to differentiate the "early write" and "on-time write"
|
3871 |
|
|
// readback patterns during read leveling
|
3872 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
|
3873 |
|
|
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
|
3874 |
|
|
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
|
3875 |
|
|
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
|
3876 |
|
|
end else if (!prbs_rdlvl_done && ~phy_data_full)
|
3877 |
|
|
phy_wrdata <= #TCQ prbs_o;
|
3878 |
|
|
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
|
3879 |
|
|
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
|
3880 |
|
|
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},
|
3881 |
|
|
{DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},
|
3882 |
|
|
{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
|
3883 |
|
|
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
|
3884 |
|
|
else if (!complex_oclkdelay_calib_done && ~phy_data_full)
|
3885 |
|
|
phy_wrdata <= #TCQ prbs_o;
|
3886 |
|
|
end else begin: wrdq_div1_2to1_wrcal_first
|
3887 |
|
|
|
3888 |
|
|
always @(posedge clk)
|
3889 |
|
|
if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3"))
|
3890 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},
|
3891 |
|
|
{DQ_WIDTH/4{4'h0}},
|
3892 |
|
|
{DQ_WIDTH/4{4'hF}},
|
3893 |
|
|
{DQ_WIDTH/4{4'h0}}};
|
3894 |
|
|
else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin
|
3895 |
|
|
case (wrcal_pat_cnt)
|
3896 |
|
|
2'b00: begin
|
3897 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},
|
3898 |
|
|
{DQ_WIDTH/4{4'hA}},
|
3899 |
|
|
{DQ_WIDTH/4{4'h0}},
|
3900 |
|
|
{DQ_WIDTH/4{4'hF}}};
|
3901 |
|
|
end
|
3902 |
|
|
2'b01: begin
|
3903 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},
|
3904 |
|
|
{DQ_WIDTH/4{4'h9}},
|
3905 |
|
|
{DQ_WIDTH/4{4'hA}},
|
3906 |
|
|
{DQ_WIDTH/4{4'h5}}};
|
3907 |
|
|
end
|
3908 |
|
|
2'b10: begin
|
3909 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
|
3910 |
|
|
{DQ_WIDTH/4{4'hE}},
|
3911 |
|
|
{DQ_WIDTH/4{4'h1}},
|
3912 |
|
|
{DQ_WIDTH/4{4'hB}}};
|
3913 |
|
|
end
|
3914 |
|
|
2'b11: begin
|
3915 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},
|
3916 |
|
|
{DQ_WIDTH/4{4'hD}},
|
3917 |
|
|
{DQ_WIDTH/4{4'hE}},
|
3918 |
|
|
{DQ_WIDTH/4{4'h4}}};
|
3919 |
|
|
end
|
3920 |
|
|
endcase
|
3921 |
|
|
end else if (!rdlvl_stg1_done) begin
|
3922 |
|
|
// The 16 words for stage 1 write data in 2:1 mode is written
|
3923 |
|
|
// over 4 consecutive controller clock cycles. Note that write
|
3924 |
|
|
// data follows phy_wrdata_en by one clock cycle
|
3925 |
|
|
case (wrdata_pat_cnt)
|
3926 |
|
|
2'b00: begin
|
3927 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
|
3928 |
|
|
{DQ_WIDTH/4{4'h7}},
|
3929 |
|
|
{DQ_WIDTH/4{4'h3}},
|
3930 |
|
|
{DQ_WIDTH/4{4'h9}}};
|
3931 |
|
|
end
|
3932 |
|
|
|
3933 |
|
|
2'b01: begin
|
3934 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
|
3935 |
|
|
{DQ_WIDTH/4{4'h2}},
|
3936 |
|
|
{DQ_WIDTH/4{4'h9}},
|
3937 |
|
|
{DQ_WIDTH/4{4'hC}}};
|
3938 |
|
|
end
|
3939 |
|
|
|
3940 |
|
|
2'b10: begin
|
3941 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
|
3942 |
|
|
{DQ_WIDTH/4{4'h7}},
|
3943 |
|
|
{DQ_WIDTH/4{4'h1}},
|
3944 |
|
|
{DQ_WIDTH/4{4'hB}}};
|
3945 |
|
|
end
|
3946 |
|
|
|
3947 |
|
|
2'b11: begin
|
3948 |
|
|
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
|
3949 |
|
|
{DQ_WIDTH/4{4'h2}},
|
3950 |
|
|
{DQ_WIDTH/4{4'h9}},
|
3951 |
|
|
{DQ_WIDTH/4{4'hC}}};
|
3952 |
|
|
end
|
3953 |
|
|
endcase
|
3954 |
|
|
end else if (!prbs_rdlvl_done && ~phy_data_full) begin
|
3955 |
|
|
phy_wrdata <= #TCQ prbs_o;
|
3956 |
|
|
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
|
3957 |
|
|
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
|
3958 |
|
|
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},
|
3959 |
|
|
{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
|
3960 |
|
|
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},
|
3961 |
|
|
{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
|
3962 |
|
|
end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin
|
3963 |
|
|
phy_wrdata <= #TCQ prbs_o;
|
3964 |
|
|
end
|
3965 |
|
|
|
3966 |
|
|
end
|
3967 |
|
|
endgenerate
|
3968 |
|
|
|
3969 |
|
|
//***************************************************************************
|
3970 |
|
|
// Memory control/address
|
3971 |
|
|
//***************************************************************************
|
3972 |
|
|
|
3973 |
|
|
|
3974 |
|
|
// Phases [2] and [3] are always deasserted for 4:1 mode
|
3975 |
|
|
generate
|
3976 |
|
|
if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff
|
3977 |
|
|
always @(posedge clk) begin
|
3978 |
|
|
phy_ras_n[3:2] <= #TCQ 3'b11;
|
3979 |
|
|
phy_cas_n[3:2] <= #TCQ 3'b11;
|
3980 |
|
|
phy_we_n[3:2] <= #TCQ 3'b11;
|
3981 |
|
|
end
|
3982 |
|
|
end
|
3983 |
|
|
endgenerate
|
3984 |
|
|
|
3985 |
|
|
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
|
3986 |
|
|
// (4) auto refresh
|
3987 |
|
|
// verilint STARC-2.7.3.3b off
|
3988 |
|
|
generate
|
3989 |
|
|
if (!(CWL_M % 2)) begin: even_cwl
|
3990 |
|
|
always @(posedge clk) begin
|
3991 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
3992 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
3993 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
3994 |
|
|
(init_state_r == INIT_REG_WRITE) ||
|
3995 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
3996 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
3997 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
3998 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
3999 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
4000 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
4001 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
4002 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
4003 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
4004 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
4005 |
|
|
(init_state_r == INIT_REFRESH) ||
|
4006 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
4007 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT))begin
|
4008 |
|
|
phy_ras_n[0] <= #TCQ 1'b0;
|
4009 |
|
|
phy_ras_n[1] <= #TCQ 1'b1;
|
4010 |
|
|
end else begin
|
4011 |
|
|
phy_ras_n[0] <= #TCQ 1'b1;
|
4012 |
|
|
phy_ras_n[1] <= #TCQ 1'b1;
|
4013 |
|
|
end
|
4014 |
|
|
end
|
4015 |
|
|
|
4016 |
|
|
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
|
4017 |
|
|
// (3) auto refresh
|
4018 |
|
|
always @(posedge clk) begin
|
4019 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
4020 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
4021 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
4022 |
|
|
(init_state_r == INIT_REG_WRITE) ||
|
4023 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
4024 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
4025 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
4026 |
|
|
(init_state_r == INIT_REFRESH) ||
|
4027 |
|
|
(rdlvl_wr_rd && new_burst_r))begin
|
4028 |
|
|
phy_cas_n[0] <= #TCQ 1'b0;
|
4029 |
|
|
phy_cas_n[1] <= #TCQ 1'b1;
|
4030 |
|
|
end else begin
|
4031 |
|
|
phy_cas_n[0] <= #TCQ 1'b1;
|
4032 |
|
|
phy_cas_n[1] <= #TCQ 1'b1;
|
4033 |
|
|
end
|
4034 |
|
|
end
|
4035 |
|
|
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
|
4036 |
|
|
// occur during read leveling), (3) Issuing ZQ Long Calib command,
|
4037 |
|
|
// (4) Precharge
|
4038 |
|
|
always @(posedge clk) begin
|
4039 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
4040 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
4041 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
4042 |
|
|
(init_state_r == INIT_REG_WRITE) ||
|
4043 |
|
|
(init_state_r == INIT_ZQCL) ||
|
4044 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
4045 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
4046 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
4047 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
4048 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE)||
|
4049 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
4050 |
|
|
(rdlvl_wr && new_burst_r))begin
|
4051 |
|
|
phy_we_n[0] <= #TCQ 1'b0;
|
4052 |
|
|
phy_we_n[1] <= #TCQ 1'b1;
|
4053 |
|
|
end else begin
|
4054 |
|
|
phy_we_n[0] <= #TCQ 1'b1;
|
4055 |
|
|
phy_we_n[1] <= #TCQ 1'b1;
|
4056 |
|
|
end
|
4057 |
|
|
end
|
4058 |
|
|
end else begin: odd_cwl
|
4059 |
|
|
always @(posedge clk) begin
|
4060 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
4061 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
4062 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
4063 |
|
|
(init_state_r == INIT_REG_WRITE) ||
|
4064 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
4065 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
4066 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
4067 |
|
|
(init_state_r == INIT_RDLVL_ACT) ||
|
4068 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
4069 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT) ||
|
4070 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
4071 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
4072 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
4073 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE) ||
|
4074 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
4075 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
4076 |
|
|
(init_state_r == INIT_REFRESH))begin
|
4077 |
|
|
phy_ras_n[0] <= #TCQ 1'b1;
|
4078 |
|
|
phy_ras_n[1] <= #TCQ 1'b0;
|
4079 |
|
|
end else begin
|
4080 |
|
|
phy_ras_n[0] <= #TCQ 1'b1;
|
4081 |
|
|
phy_ras_n[1] <= #TCQ 1'b1;
|
4082 |
|
|
end
|
4083 |
|
|
end
|
4084 |
|
|
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
|
4085 |
|
|
// (3) auto refresh
|
4086 |
|
|
always @(posedge clk) begin
|
4087 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
4088 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
4089 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
4090 |
|
|
(init_state_r == INIT_REG_WRITE) ||
|
4091 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
4092 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
4093 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
4094 |
|
|
(init_state_r == INIT_REFRESH) ||
|
4095 |
|
|
(rdlvl_wr_rd && new_burst_r))begin
|
4096 |
|
|
phy_cas_n[0] <= #TCQ 1'b1;
|
4097 |
|
|
phy_cas_n[1] <= #TCQ 1'b0;
|
4098 |
|
|
end else begin
|
4099 |
|
|
phy_cas_n[0] <= #TCQ 1'b1;
|
4100 |
|
|
phy_cas_n[1] <= #TCQ 1'b1;
|
4101 |
|
|
end
|
4102 |
|
|
end
|
4103 |
|
|
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
|
4104 |
|
|
// occur during read leveling), (3) Issuing ZQ Long Calib command,
|
4105 |
|
|
// (4) Precharge
|
4106 |
|
|
always @(posedge clk) begin
|
4107 |
|
|
if ((init_state_r == INIT_LOAD_MR) ||
|
4108 |
|
|
(init_state_r == INIT_MPR_RDEN) ||
|
4109 |
|
|
(init_state_r == INIT_MPR_DISABLE) ||
|
4110 |
|
|
(init_state_r == INIT_REG_WRITE) ||
|
4111 |
|
|
(init_state_r == INIT_ZQCL) ||
|
4112 |
|
|
(init_state_r == INIT_WRLVL_START) ||
|
4113 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR) ||
|
4114 |
|
|
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
|
4115 |
|
|
(init_state_r == INIT_PRECHARGE) ||
|
4116 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE)||
|
4117 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
4118 |
|
|
(rdlvl_wr && new_burst_r))begin
|
4119 |
|
|
phy_we_n[0] <= #TCQ 1'b1;
|
4120 |
|
|
phy_we_n[1] <= #TCQ 1'b0;
|
4121 |
|
|
end else begin
|
4122 |
|
|
phy_we_n[0] <= #TCQ 1'b1;
|
4123 |
|
|
phy_we_n[1] <= #TCQ 1'b1;
|
4124 |
|
|
end
|
4125 |
|
|
end
|
4126 |
|
|
end
|
4127 |
|
|
endgenerate
|
4128 |
|
|
// verilint STARC-2.7.3.3b on
|
4129 |
|
|
|
4130 |
|
|
|
4131 |
|
|
// Assign calib_cmd for the command field in PHY_Ctl_Word
|
4132 |
|
|
always @(posedge clk) begin
|
4133 |
|
|
if (wr_level_dqs_asrt) begin
|
4134 |
|
|
// Request to toggle DQS during write leveling
|
4135 |
|
|
calib_cmd <= #TCQ 3'b001;
|
4136 |
|
|
if (CWL_M % 2) begin // odd write latency
|
4137 |
|
|
calib_data_offset_0 <= #TCQ CWL_M + 3;
|
4138 |
|
|
calib_data_offset_1 <= #TCQ CWL_M + 3;
|
4139 |
|
|
calib_data_offset_2 <= #TCQ CWL_M + 3;
|
4140 |
|
|
calib_cas_slot <= #TCQ 2'b01;
|
4141 |
|
|
end else begin // even write latency
|
4142 |
|
|
calib_data_offset_0 <= #TCQ CWL_M + 2;
|
4143 |
|
|
calib_data_offset_1 <= #TCQ CWL_M + 2;
|
4144 |
|
|
calib_data_offset_2 <= #TCQ CWL_M + 2;
|
4145 |
|
|
calib_cas_slot <= #TCQ 2'b00;
|
4146 |
|
|
end
|
4147 |
|
|
end else if (rdlvl_wr && new_burst_r) begin
|
4148 |
|
|
// Write Command
|
4149 |
|
|
calib_cmd <= #TCQ 3'b001;
|
4150 |
|
|
if (CWL_M % 2) begin // odd write latency
|
4151 |
|
|
calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
|
4152 |
|
|
calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
|
4153 |
|
|
calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
|
4154 |
|
|
calib_cas_slot <= #TCQ 2'b01;
|
4155 |
|
|
end else begin // even write latency
|
4156 |
|
|
calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
|
4157 |
|
|
calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
|
4158 |
|
|
calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
|
4159 |
|
|
calib_cas_slot <= #TCQ 2'b00;
|
4160 |
|
|
end
|
4161 |
|
|
end else if (rdlvl_rd && new_burst_r) begin
|
4162 |
|
|
// Read Command
|
4163 |
|
|
calib_cmd <= #TCQ 3'b011;
|
4164 |
|
|
if (CWL_M % 2)
|
4165 |
|
|
calib_cas_slot <= #TCQ 2'b01;
|
4166 |
|
|
else
|
4167 |
|
|
calib_cas_slot <= #TCQ 2'b00;
|
4168 |
|
|
if (~pi_calib_done_r1) begin
|
4169 |
|
|
calib_data_offset_0 <= #TCQ 6'd0;
|
4170 |
|
|
calib_data_offset_1 <= #TCQ 6'd0;
|
4171 |
|
|
calib_data_offset_2 <= #TCQ 6'd0;
|
4172 |
|
|
end else if (~pi_dqs_found_done_r1) begin
|
4173 |
|
|
calib_data_offset_0 <= #TCQ rd_data_offset_0;
|
4174 |
|
|
calib_data_offset_1 <= #TCQ rd_data_offset_1;
|
4175 |
|
|
calib_data_offset_2 <= #TCQ rd_data_offset_2;
|
4176 |
|
|
end else begin
|
4177 |
|
|
calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6];
|
4178 |
|
|
calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6];
|
4179 |
|
|
calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6];
|
4180 |
|
|
end
|
4181 |
|
|
end else begin
|
4182 |
|
|
// Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge,
|
4183 |
|
|
// Active, Refresh
|
4184 |
|
|
calib_cmd <= #TCQ 3'b100;
|
4185 |
|
|
calib_data_offset_0 <= #TCQ 6'd0;
|
4186 |
|
|
calib_data_offset_1 <= #TCQ 6'd0;
|
4187 |
|
|
calib_data_offset_2 <= #TCQ 6'd0;
|
4188 |
|
|
if (CWL_M % 2)
|
4189 |
|
|
calib_cas_slot <= #TCQ 2'b01;
|
4190 |
|
|
else
|
4191 |
|
|
calib_cas_slot <= #TCQ 2'b00;
|
4192 |
|
|
end
|
4193 |
|
|
end
|
4194 |
|
|
|
4195 |
|
|
// Write Enable to PHY_Control FIFO always asserted
|
4196 |
|
|
// No danger of this FIFO being Full with 4:1 sync clock ratio
|
4197 |
|
|
// This is also the write enable to the command OUT_FIFO
|
4198 |
|
|
always @(posedge clk) begin
|
4199 |
|
|
if (rst) begin
|
4200 |
|
|
calib_ctl_wren <= #TCQ 1'b0;
|
4201 |
|
|
calib_cmd_wren <= #TCQ 1'b0;
|
4202 |
|
|
calib_seq <= #TCQ 2'b00;
|
4203 |
|
|
end else if (cnt_pwron_cke_done_r && phy_ctl_ready
|
4204 |
|
|
&& ~(phy_ctl_full || phy_cmd_full )) begin
|
4205 |
|
|
calib_ctl_wren <= #TCQ 1'b1;
|
4206 |
|
|
calib_cmd_wren <= #TCQ 1'b1;
|
4207 |
|
|
calib_seq <= #TCQ calib_seq + 1;
|
4208 |
|
|
end else begin
|
4209 |
|
|
calib_ctl_wren <= #TCQ 1'b0;
|
4210 |
|
|
calib_cmd_wren <= #TCQ 1'b0;
|
4211 |
|
|
calib_seq <= #TCQ calib_seq;
|
4212 |
|
|
end
|
4213 |
|
|
end
|
4214 |
|
|
|
4215 |
|
|
generate
|
4216 |
|
|
genvar rnk_i;
|
4217 |
|
|
for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk
|
4218 |
|
|
always @(posedge clk) begin
|
4219 |
|
|
if (rst) begin
|
4220 |
|
|
mr2_r[rnk_i] <= #TCQ 2'b00;
|
4221 |
|
|
mr1_r[rnk_i] <= #TCQ 3'b000;
|
4222 |
|
|
end else begin
|
4223 |
|
|
mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];
|
4224 |
|
|
mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];
|
4225 |
|
|
end
|
4226 |
|
|
end
|
4227 |
|
|
end
|
4228 |
|
|
endgenerate
|
4229 |
|
|
|
4230 |
|
|
// ODT assignment based on slot config and slot present
|
4231 |
|
|
// For single slot systems slot_1_present input will be ignored
|
4232 |
|
|
// Assuming component interfaces to be single slot systems
|
4233 |
|
|
generate
|
4234 |
|
|
if (nSLOTS == 1) begin: gen_single_slot_odt
|
4235 |
|
|
always @(posedge clk) begin
|
4236 |
|
|
if (rst) begin
|
4237 |
|
|
tmp_mr2_r[1] <= #TCQ 2'b00;
|
4238 |
|
|
tmp_mr2_r[2] <= #TCQ 2'b00;
|
4239 |
|
|
tmp_mr2_r[3] <= #TCQ 2'b00;
|
4240 |
|
|
tmp_mr1_r[1] <= #TCQ 3'b000;
|
4241 |
|
|
tmp_mr1_r[2] <= #TCQ 3'b000;
|
4242 |
|
|
tmp_mr1_r[3] <= #TCQ 3'b000;
|
4243 |
|
|
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
|
4244 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0000;
|
4245 |
|
|
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
|
4246 |
|
|
end else begin
|
4247 |
|
|
case ({slot_0_present[0],slot_0_present[1],
|
4248 |
|
|
slot_0_present[2],slot_0_present[3]})
|
4249 |
|
|
// Single slot configuration with quad rank
|
4250 |
|
|
// Assuming same behavior as single slot dual rank for now
|
4251 |
|
|
// DDR2 does not have quad rank parts
|
4252 |
|
|
4'b1111: begin
|
4253 |
|
|
if ((RTT_WR == "OFF") ||
|
4254 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4255 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4256 |
|
|
//Rank0 Dynamic ODT disabled
|
4257 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4258 |
|
|
//Rank0 RTT_NOM
|
4259 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4260 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4261 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4262 |
|
|
3'b000;
|
4263 |
|
|
end else begin
|
4264 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4265 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4266 |
|
|
2'b10;
|
4267 |
|
|
//Rank0 RTT_NOM after write leveling completes
|
4268 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4269 |
|
|
end
|
4270 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4271 |
|
|
// Chip Select assignments
|
4272 |
|
|
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
|
4273 |
|
|
) +: nCS_PER_RANK] <= #TCQ 'b0;
|
4274 |
|
|
end
|
4275 |
|
|
|
4276 |
|
|
// Single slot configuration with single rank
|
4277 |
|
|
4'b1000: begin
|
4278 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4279 |
|
|
if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin
|
4280 |
|
|
phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;
|
4281 |
|
|
end else begin
|
4282 |
|
|
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
|
4283 |
|
|
end
|
4284 |
|
|
if ((RTT_WR == "OFF") ||
|
4285 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4286 |
|
|
((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin
|
4287 |
|
|
//Rank0 Dynamic ODT disabled
|
4288 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4289 |
|
|
//Rank0 RTT_NOM
|
4290 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4291 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4292 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4293 |
|
|
3'b000;
|
4294 |
|
|
end else begin
|
4295 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4296 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4297 |
|
|
2'b10;
|
4298 |
|
|
//Rank0 RTT_NOM after write leveling completes
|
4299 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4300 |
|
|
end
|
4301 |
|
|
end
|
4302 |
|
|
|
4303 |
|
|
// Single slot configuration with dual rank
|
4304 |
|
|
4'b1100: begin
|
4305 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4306 |
|
|
// Chip Select assignments
|
4307 |
|
|
|
4308 |
|
|
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
|
4309 |
|
|
) +: nCS_PER_RANK] <= #TCQ 'b0;
|
4310 |
|
|
if ((RTT_WR == "OFF") ||
|
4311 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4312 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4313 |
|
|
//Rank0 Dynamic ODT disabled
|
4314 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4315 |
|
|
//Rank0 Rtt_NOM
|
4316 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4317 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4318 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4319 |
|
|
3'b000;
|
4320 |
|
|
end else begin
|
4321 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4322 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4323 |
|
|
2'b10;
|
4324 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4325 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4326 |
|
|
end
|
4327 |
|
|
end
|
4328 |
|
|
|
4329 |
|
|
default: begin
|
4330 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4331 |
|
|
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
|
4332 |
|
|
if ((RTT_WR == "OFF") ||
|
4333 |
|
|
((WRLVL=="ON") && ~wrlvl_done)) begin
|
4334 |
|
|
//Rank0 Dynamic ODT disabled
|
4335 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4336 |
|
|
//Rank0 Rtt_NOM
|
4337 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4338 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4339 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4340 |
|
|
3'b000;
|
4341 |
|
|
end else begin
|
4342 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4343 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4344 |
|
|
2'b10;
|
4345 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4346 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4347 |
|
|
end
|
4348 |
|
|
end
|
4349 |
|
|
endcase
|
4350 |
|
|
end
|
4351 |
|
|
end
|
4352 |
|
|
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
|
4353 |
|
|
always @ (posedge clk) begin
|
4354 |
|
|
if (rst) begin
|
4355 |
|
|
tmp_mr2_r[1] <= #TCQ 2'b00;
|
4356 |
|
|
tmp_mr2_r[2] <= #TCQ 2'b00;
|
4357 |
|
|
tmp_mr2_r[3] <= #TCQ 2'b00;
|
4358 |
|
|
tmp_mr1_r[1] <= #TCQ 3'b000;
|
4359 |
|
|
tmp_mr1_r[2] <= #TCQ 3'b000;
|
4360 |
|
|
tmp_mr1_r[3] <= #TCQ 3'b000;
|
4361 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0000;
|
4362 |
|
|
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
|
4363 |
|
|
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
|
4364 |
|
|
end else begin
|
4365 |
|
|
case ({slot_0_present[0],slot_0_present[1],
|
4366 |
|
|
slot_1_present[0],slot_1_present[1]})
|
4367 |
|
|
// Two slot configuration, one slot present, single rank
|
4368 |
|
|
4'b10_00: begin
|
4369 |
|
|
if (//wrlvl_odt ||
|
4370 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4371 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4372 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4373 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4374 |
|
|
// odt turned on only during write
|
4375 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4376 |
|
|
end
|
4377 |
|
|
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
|
4378 |
|
|
if ((RTT_WR == "OFF") ||
|
4379 |
|
|
((WRLVL=="ON") && ~wrlvl_done)) begin
|
4380 |
|
|
//Rank0 Dynamic ODT disabled
|
4381 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4382 |
|
|
//Rank0 Rtt_NOM
|
4383 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4384 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4385 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4386 |
|
|
3'b000;
|
4387 |
|
|
end else begin
|
4388 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4389 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4390 |
|
|
2'b10;
|
4391 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4392 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4393 |
|
|
end
|
4394 |
|
|
end
|
4395 |
|
|
4'b00_10: begin
|
4396 |
|
|
|
4397 |
|
|
//Rank1 ODT enabled
|
4398 |
|
|
if (//wrlvl_odt ||
|
4399 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4400 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4401 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4402 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4403 |
|
|
// odt turned on only during write
|
4404 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4405 |
|
|
end
|
4406 |
|
|
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
|
4407 |
|
|
if ((RTT_WR == "OFF") ||
|
4408 |
|
|
((WRLVL=="ON") && ~wrlvl_done)) begin
|
4409 |
|
|
//Rank1 Dynamic ODT disabled
|
4410 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4411 |
|
|
//Rank1 Rtt_NOM defaults to 120 ohms
|
4412 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4413 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4414 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4415 |
|
|
3'b000;
|
4416 |
|
|
end else begin
|
4417 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4418 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4419 |
|
|
2'b10;
|
4420 |
|
|
//Rank1 Rtt_NOM after write leveling completes
|
4421 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4422 |
|
|
end
|
4423 |
|
|
end
|
4424 |
|
|
// Two slot configuration, one slot present, dual rank
|
4425 |
|
|
4'b00_11: begin
|
4426 |
|
|
if (//wrlvl_odt ||
|
4427 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4428 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4429 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4430 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4431 |
|
|
// odt turned on only during write
|
4432 |
|
|
phy_tmp_odt_r
|
4433 |
|
|
<= #TCQ 4'b0001;
|
4434 |
|
|
end
|
4435 |
|
|
|
4436 |
|
|
// Chip Select assignments
|
4437 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4438 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4439 |
|
|
|
4440 |
|
|
if ((RTT_WR == "OFF") ||
|
4441 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4442 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4443 |
|
|
//Rank0 Dynamic ODT disabled
|
4444 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4445 |
|
|
//Rank0 Rtt_NOM
|
4446 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4447 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4448 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4449 |
|
|
3'b000;
|
4450 |
|
|
end else begin
|
4451 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4452 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4453 |
|
|
2'b10;
|
4454 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4455 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4456 |
|
|
end
|
4457 |
|
|
end
|
4458 |
|
|
4'b11_00: begin
|
4459 |
|
|
if (//wrlvl_odt ||
|
4460 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4461 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4462 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4463 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4464 |
|
|
// odt turned on only during write
|
4465 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0001;
|
4466 |
|
|
end
|
4467 |
|
|
|
4468 |
|
|
// Chip Select assignments
|
4469 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4470 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4471 |
|
|
|
4472 |
|
|
if ((RTT_WR == "OFF") ||
|
4473 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4474 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4475 |
|
|
//Rank1 Dynamic ODT disabled
|
4476 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4477 |
|
|
//Rank1 Rtt_NOM
|
4478 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4479 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4480 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4481 |
|
|
3'b000;
|
4482 |
|
|
end else begin
|
4483 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4484 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4485 |
|
|
2'b10;
|
4486 |
|
|
//Rank1 Rtt_NOM after write leveling completes
|
4487 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4488 |
|
|
end
|
4489 |
|
|
end
|
4490 |
|
|
// Two slot configuration, one rank per slot
|
4491 |
|
|
4'b10_10: begin
|
4492 |
|
|
if(DRAM_TYPE == "DDR2")begin
|
4493 |
|
|
if(chip_cnt_r == 2'b00)begin
|
4494 |
|
|
phy_tmp_odt_r
|
4495 |
|
|
<= #TCQ 4'b0010; //bit0 for rank0
|
4496 |
|
|
end else begin
|
4497 |
|
|
phy_tmp_odt_r
|
4498 |
|
|
<= #TCQ 4'b0001; //bit0 for rank0
|
4499 |
|
|
end
|
4500 |
|
|
end else begin
|
4501 |
|
|
if((init_state_r == INIT_WRLVL_WAIT) ||
|
4502 |
|
|
(init_next_state == INIT_RDLVL_STG1_WRITE) ||
|
4503 |
|
|
(init_next_state == INIT_WRCAL_WRITE) ||
|
4504 |
|
|
(init_next_state == INIT_OCAL_CENTER_WRITE) ||
|
4505 |
|
|
(init_next_state == INIT_OCLKDELAY_WRITE))
|
4506 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write)
|
4507 |
|
|
else if ((init_next_state == INIT_PI_PHASELOCK_READS) ||
|
4508 |
|
|
(init_next_state == INIT_MPR_READ) ||
|
4509 |
|
|
(init_next_state == INIT_RDLVL_STG1_READ) ||
|
4510 |
|
|
(init_next_state == INIT_RDLVL_COMPLEX_READ) ||
|
4511 |
|
|
(init_next_state == INIT_RDLVL_STG2_READ) ||
|
4512 |
|
|
(init_next_state == INIT_OCLKDELAY_READ) ||
|
4513 |
|
|
(init_next_state == INIT_WRCAL_READ) ||
|
4514 |
|
|
(init_next_state == INIT_WRCAL_MULT_READS))
|
4515 |
|
|
phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd)
|
4516 |
|
|
end
|
4517 |
|
|
|
4518 |
|
|
// Chip Select assignments
|
4519 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4520 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4521 |
|
|
|
4522 |
|
|
if ((RTT_WR == "OFF") ||
|
4523 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4524 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4525 |
|
|
//Rank0 Dynamic ODT disabled
|
4526 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4527 |
|
|
//Rank0 Rtt_NOM
|
4528 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 :
|
4529 |
|
|
(RTT_WR == "120") ? 3'b010 :
|
4530 |
|
|
3'b000;
|
4531 |
|
|
//Rank1 Dynamic ODT disabled
|
4532 |
|
|
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4533 |
|
|
2'b10;
|
4534 |
|
|
//Rank1 Rtt_NOM
|
4535 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4536 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4537 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4538 |
|
|
3'b000;
|
4539 |
|
|
end else begin
|
4540 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4541 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4542 |
|
|
2'b10;
|
4543 |
|
|
//Rank0 Rtt_NOM
|
4544 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4545 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4546 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4547 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4548 |
|
|
(RTT_NOM_int == "40") ? 3'b011 :
|
4549 |
|
|
3'b000;
|
4550 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4551 |
|
|
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4552 |
|
|
2'b10;
|
4553 |
|
|
//Rank1 Rtt_NOM
|
4554 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4555 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4556 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4557 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4558 |
|
|
(RTT_NOM_int == "40") ? 3'b011 :
|
4559 |
|
|
3'b000;
|
4560 |
|
|
end
|
4561 |
|
|
end
|
4562 |
|
|
// Two Slots - One slot with dual rank and other with single rank
|
4563 |
|
|
4'b10_11: begin
|
4564 |
|
|
|
4565 |
|
|
//Rank3 Rtt_NOM
|
4566 |
|
|
tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4567 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4568 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4569 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4570 |
|
|
(RTT_NOM_int == "40") ? 3'b011 :
|
4571 |
|
|
3'b000;
|
4572 |
|
|
tmp_mr2_r[2] <= #TCQ 2'b00;
|
4573 |
|
|
if ((RTT_WR == "OFF") ||
|
4574 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4575 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4576 |
|
|
//Rank0 Dynamic ODT disabled
|
4577 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4578 |
|
|
//Rank0 Rtt_NOM
|
4579 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4580 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4581 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4582 |
|
|
3'b000;
|
4583 |
|
|
//Rank1 Dynamic ODT disabled
|
4584 |
|
|
tmp_mr2_r[1] <= #TCQ 2'b00;
|
4585 |
|
|
//Rank1 Rtt_NOM
|
4586 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4587 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4588 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4589 |
|
|
3'b000;
|
4590 |
|
|
end else begin
|
4591 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4592 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4593 |
|
|
2'b10;
|
4594 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4595 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4596 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4597 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4598 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4599 |
|
|
(RTT_NOM_int == "40") ? 3'b011 :
|
4600 |
|
|
3'b000;
|
4601 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4602 |
|
|
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4603 |
|
|
2'b10;
|
4604 |
|
|
//Rank1 Rtt_NOM after write leveling completes
|
4605 |
|
|
tmp_mr1_r[1] <= #TCQ 3'b000;
|
4606 |
|
|
end
|
4607 |
|
|
//Slot1 Rank1 or Rank3 is being written
|
4608 |
|
|
if(DRAM_TYPE == "DDR2")begin
|
4609 |
|
|
if(chip_cnt_r == 2'b00)begin
|
4610 |
|
|
phy_tmp_odt_r
|
4611 |
|
|
<= #TCQ 4'b0010;
|
4612 |
|
|
end else begin
|
4613 |
|
|
phy_tmp_odt_r
|
4614 |
|
|
<= #TCQ 4'b0001;
|
4615 |
|
|
end
|
4616 |
|
|
end else begin
|
4617 |
|
|
if (//wrlvl_odt ||
|
4618 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4619 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4620 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4621 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4622 |
|
|
if (chip_cnt_r[0] == 1'b1) begin
|
4623 |
|
|
phy_tmp_odt_r
|
4624 |
|
|
<= #TCQ 4'b0011;
|
4625 |
|
|
//Slot0 Rank0 is being written
|
4626 |
|
|
end else begin
|
4627 |
|
|
phy_tmp_odt_r
|
4628 |
|
|
<= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted
|
4629 |
|
|
end
|
4630 |
|
|
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
|
4631 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
|
4632 |
|
|
(init_state_r == INIT_PI_PHASELOCK_READS) ||
|
4633 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ) ||
|
4634 |
|
|
(init_state_r == INIT_OCLKDELAY_READ) ||
|
4635 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
4636 |
|
|
(init_state_r == INIT_WRCAL_MULT_READS))begin
|
4637 |
|
|
if (chip_cnt_r == 2'b00) begin
|
4638 |
|
|
phy_tmp_odt_r
|
4639 |
|
|
<= #TCQ 4'b0100;
|
4640 |
|
|
end else begin
|
4641 |
|
|
phy_tmp_odt_r
|
4642 |
|
|
<= #TCQ 4'b0001;
|
4643 |
|
|
end
|
4644 |
|
|
end
|
4645 |
|
|
end
|
4646 |
|
|
|
4647 |
|
|
// Chip Select assignments
|
4648 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4649 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4650 |
|
|
|
4651 |
|
|
end
|
4652 |
|
|
// Two Slots - One slot with dual rank and other with single rank
|
4653 |
|
|
4'b11_10: begin
|
4654 |
|
|
|
4655 |
|
|
//Rank2 Rtt_NOM
|
4656 |
|
|
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
|
4657 |
|
|
(RTT_NOM2 == "120") ? 3'b010 :
|
4658 |
|
|
(RTT_NOM2 == "20") ? 3'b100 :
|
4659 |
|
|
(RTT_NOM2 == "30") ? 3'b101 :
|
4660 |
|
|
(RTT_NOM2 == "40") ? 3'b011:
|
4661 |
|
|
3'b000;
|
4662 |
|
|
tmp_mr2_r[2] <= #TCQ 2'b00;
|
4663 |
|
|
if ((RTT_WR == "OFF") ||
|
4664 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4665 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4666 |
|
|
//Rank0 Dynamic ODT disabled
|
4667 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4668 |
|
|
//Rank0 Rtt_NOM
|
4669 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4670 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4671 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4672 |
|
|
3'b000;
|
4673 |
|
|
//Rank1 Dynamic ODT disabled
|
4674 |
|
|
tmp_mr2_r[1] <= #TCQ 2'b00;
|
4675 |
|
|
//Rank1 Rtt_NOM
|
4676 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4677 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4678 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4679 |
|
|
3'b000;
|
4680 |
|
|
end else begin
|
4681 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4682 |
|
|
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4683 |
|
|
2'b10;
|
4684 |
|
|
//Rank1 Rtt_NOM
|
4685 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4686 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4687 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4688 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4689 |
|
|
(RTT_NOM_int == "40") ? 3'b011:
|
4690 |
|
|
3'b000;
|
4691 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4692 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4693 |
|
|
2'b10;
|
4694 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4695 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4696 |
|
|
end
|
4697 |
|
|
|
4698 |
|
|
if(DRAM_TYPE == "DDR2")begin
|
4699 |
|
|
if(chip_cnt_r[1] == 1'b1)begin
|
4700 |
|
|
phy_tmp_odt_r <=
|
4701 |
|
|
#TCQ 4'b0001;
|
4702 |
|
|
end else begin
|
4703 |
|
|
phy_tmp_odt_r
|
4704 |
|
|
<= #TCQ 4'b0100; // rank 2 ODT asserted
|
4705 |
|
|
end
|
4706 |
|
|
end else begin
|
4707 |
|
|
if (// wrlvl_odt ||
|
4708 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4709 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4710 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4711 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4712 |
|
|
|
4713 |
|
|
if (chip_cnt_r[1] == 1'b1) begin
|
4714 |
|
|
phy_tmp_odt_r
|
4715 |
|
|
<= #TCQ 4'b0110;
|
4716 |
|
|
end else begin
|
4717 |
|
|
phy_tmp_odt_r <=
|
4718 |
|
|
#TCQ 4'b0101;
|
4719 |
|
|
end
|
4720 |
|
|
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
|
4721 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
|
4722 |
|
|
(init_state_r == INIT_PI_PHASELOCK_READS) ||
|
4723 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ) ||
|
4724 |
|
|
(init_state_r == INIT_OCLKDELAY_READ) ||
|
4725 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
4726 |
|
|
(init_state_r == INIT_WRCAL_MULT_READS)) begin
|
4727 |
|
|
|
4728 |
|
|
if (chip_cnt_r[1] == 1'b1) begin
|
4729 |
|
|
phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
|
4730 |
|
|
<= #TCQ 4'b0010;
|
4731 |
|
|
end else begin
|
4732 |
|
|
phy_tmp_odt_r
|
4733 |
|
|
<= #TCQ 4'b0100;
|
4734 |
|
|
end
|
4735 |
|
|
end
|
4736 |
|
|
end
|
4737 |
|
|
|
4738 |
|
|
// Chip Select assignments
|
4739 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4740 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4741 |
|
|
end
|
4742 |
|
|
// Two Slots - two ranks per slot
|
4743 |
|
|
4'b11_11: begin
|
4744 |
|
|
//Rank2 Rtt_NOM
|
4745 |
|
|
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
|
4746 |
|
|
(RTT_NOM2 == "120") ? 3'b010 :
|
4747 |
|
|
(RTT_NOM2 == "20") ? 3'b100 :
|
4748 |
|
|
(RTT_NOM2 == "30") ? 3'b101 :
|
4749 |
|
|
(RTT_NOM2 == "40") ? 3'b011 :
|
4750 |
|
|
3'b000;
|
4751 |
|
|
//Rank3 Rtt_NOM
|
4752 |
|
|
tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
|
4753 |
|
|
(RTT_NOM3 == "120") ? 3'b010 :
|
4754 |
|
|
(RTT_NOM3 == "20") ? 3'b100 :
|
4755 |
|
|
(RTT_NOM3 == "30") ? 3'b101 :
|
4756 |
|
|
(RTT_NOM3 == "40") ? 3'b011 :
|
4757 |
|
|
3'b000;
|
4758 |
|
|
tmp_mr2_r[2] <= #TCQ 2'b00;
|
4759 |
|
|
tmp_mr2_r[3] <= #TCQ 2'b00;
|
4760 |
|
|
if ((RTT_WR == "OFF") ||
|
4761 |
|
|
((WRLVL=="ON") && ~wrlvl_done &&
|
4762 |
|
|
(wrlvl_rank_cntr==3'd0))) begin
|
4763 |
|
|
//Rank0 Dynamic ODT disabled
|
4764 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4765 |
|
|
//Rank0 Rtt_NOM
|
4766 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4767 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4768 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4769 |
|
|
3'b000;
|
4770 |
|
|
//Rank1 Dynamic ODT disabled
|
4771 |
|
|
tmp_mr2_r[1] <= #TCQ 2'b00;
|
4772 |
|
|
//Rank1 Rtt_NOM
|
4773 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4774 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4775 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4776 |
|
|
3'b000;
|
4777 |
|
|
end else begin
|
4778 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4779 |
|
|
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4780 |
|
|
2'b10;
|
4781 |
|
|
//Rank1 Rtt_NOM after write leveling completes
|
4782 |
|
|
tmp_mr1_r[1] <= #TCQ 3'b000;
|
4783 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4784 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4785 |
|
|
2'b10;
|
4786 |
|
|
//Rank0 Rtt_NOM after write leveling completes
|
4787 |
|
|
tmp_mr1_r[0] <= #TCQ 3'b000;
|
4788 |
|
|
end
|
4789 |
|
|
|
4790 |
|
|
if(DRAM_TYPE == "DDR2")begin
|
4791 |
|
|
if(chip_cnt_r[1] == 1'b1)begin
|
4792 |
|
|
phy_tmp_odt_r
|
4793 |
|
|
<= #TCQ 4'b0001;
|
4794 |
|
|
end else begin
|
4795 |
|
|
phy_tmp_odt_r
|
4796 |
|
|
<= #TCQ 4'b0100;
|
4797 |
|
|
end
|
4798 |
|
|
end else begin
|
4799 |
|
|
if (//wrlvl_odt ||
|
4800 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4801 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4802 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4803 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4804 |
|
|
//Slot1 Rank1 or Rank3 is being written
|
4805 |
|
|
if (chip_cnt_r[0] == 1'b1) begin
|
4806 |
|
|
phy_tmp_odt_r
|
4807 |
|
|
<= #TCQ 4'b0110;
|
4808 |
|
|
//Slot0 Rank0 or Rank2 is being written
|
4809 |
|
|
end else begin
|
4810 |
|
|
phy_tmp_odt_r
|
4811 |
|
|
<= #TCQ 4'b1001;
|
4812 |
|
|
end
|
4813 |
|
|
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
|
4814 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
|
4815 |
|
|
(init_state_r == INIT_PI_PHASELOCK_READS) ||
|
4816 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ) ||
|
4817 |
|
|
(init_state_r == INIT_OCLKDELAY_READ) ||
|
4818 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
4819 |
|
|
(init_state_r == INIT_WRCAL_MULT_READS))begin
|
4820 |
|
|
//Slot1 Rank1 or Rank3 is being read
|
4821 |
|
|
if (chip_cnt_r[0] == 1'b1) begin
|
4822 |
|
|
phy_tmp_odt_r
|
4823 |
|
|
<= #TCQ 4'b0100;
|
4824 |
|
|
//Slot0 Rank0 or Rank2 is being read
|
4825 |
|
|
end else begin
|
4826 |
|
|
phy_tmp_odt_r
|
4827 |
|
|
<= #TCQ 4'b1000;
|
4828 |
|
|
end
|
4829 |
|
|
end
|
4830 |
|
|
end
|
4831 |
|
|
|
4832 |
|
|
// Chip Select assignments
|
4833 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4834 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4835 |
|
|
end
|
4836 |
|
|
default: begin
|
4837 |
|
|
phy_tmp_odt_r <= #TCQ 4'b1111;
|
4838 |
|
|
// Chip Select assignments
|
4839 |
|
|
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
|
4840 |
|
|
<= #TCQ {nCS_PER_RANK{1'b0}};
|
4841 |
|
|
if ((RTT_WR == "OFF") ||
|
4842 |
|
|
((WRLVL=="ON") && ~wrlvl_done)) begin
|
4843 |
|
|
//Rank0 Dynamic ODT disabled
|
4844 |
|
|
tmp_mr2_r[0] <= #TCQ 2'b00;
|
4845 |
|
|
//Rank0 Rtt_NOM
|
4846 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4847 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4848 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4849 |
|
|
3'b000;
|
4850 |
|
|
//Rank1 Dynamic ODT disabled
|
4851 |
|
|
tmp_mr2_r[1] <= #TCQ 2'b00;
|
4852 |
|
|
//Rank1 Rtt_NOM
|
4853 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
|
4854 |
|
|
(RTT_NOM_int == "60") ? 3'b001 :
|
4855 |
|
|
(RTT_NOM_int == "60") ? 3'b010 :
|
4856 |
|
|
3'b000;
|
4857 |
|
|
end else begin
|
4858 |
|
|
//Rank0 Dynamic ODT defaults to 120 ohms
|
4859 |
|
|
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4860 |
|
|
2'b10;
|
4861 |
|
|
//Rank0 Rtt_NOM
|
4862 |
|
|
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4863 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4864 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4865 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4866 |
|
|
(RTT_NOM_int == "40") ? 3'b011 :
|
4867 |
|
|
3'b000;
|
4868 |
|
|
//Rank1 Dynamic ODT defaults to 120 ohms
|
4869 |
|
|
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
|
4870 |
|
|
2'b10;
|
4871 |
|
|
//Rank1 Rtt_NOM
|
4872 |
|
|
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
|
4873 |
|
|
(RTT_NOM_int == "120") ? 3'b010 :
|
4874 |
|
|
(RTT_NOM_int == "20") ? 3'b100 :
|
4875 |
|
|
(RTT_NOM_int == "30") ? 3'b101 :
|
4876 |
|
|
(RTT_NOM_int == "40") ? 3'b011 :
|
4877 |
|
|
3'b000;
|
4878 |
|
|
end
|
4879 |
|
|
end
|
4880 |
|
|
endcase
|
4881 |
|
|
end
|
4882 |
|
|
end
|
4883 |
|
|
end
|
4884 |
|
|
endgenerate
|
4885 |
|
|
|
4886 |
|
|
|
4887 |
|
|
// PHY only supports two ranks.
|
4888 |
|
|
// calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0
|
4889 |
|
|
// calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1
|
4890 |
|
|
|
4891 |
|
|
generate
|
4892 |
|
|
if(CKE_ODT_AUX == "FALSE") begin
|
4893 |
|
|
if ((nSLOTS == 1) && (RANKS < 2)) begin
|
4894 |
|
|
always @(posedge clk)
|
4895 |
|
|
if (rst) begin
|
4896 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
|
4897 |
|
|
calib_odt <= 2'b00 ;
|
4898 |
|
|
end else begin
|
4899 |
|
|
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
|
4900 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
|
4901 |
|
|
end else begin
|
4902 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
|
4903 |
|
|
end
|
4904 |
|
|
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* ||
|
4905 |
|
|
wrlvl_rank_done || wrlvl_rank_done_r1 ||
|
4906 |
|
|
(wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin
|
4907 |
|
|
calib_odt[0] <= #TCQ 1'b0;
|
4908 |
|
|
calib_odt[1] <= #TCQ 1'b0;
|
4909 |
|
|
end else if (((DRAM_TYPE == "DDR3")
|
4910 |
|
|
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
|
4911 |
|
|
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) ||
|
4912 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4913 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
4914 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
|
4915 |
|
|
complex_odt_ext ||
|
4916 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4917 |
|
|
(init_state_r == INIT_WRCAL_WRITE_READ) ||
|
4918 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4919 |
|
|
complex_ocal_odt_ext ||
|
4920 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)||
|
4921 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin
|
4922 |
|
|
// Quad rank in a single slot
|
4923 |
|
|
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
|
4924 |
|
|
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
|
4925 |
|
|
end else begin
|
4926 |
|
|
calib_odt[0] <= #TCQ 1'b0;
|
4927 |
|
|
calib_odt[1] <= #TCQ 1'b0;
|
4928 |
|
|
end
|
4929 |
|
|
end
|
4930 |
|
|
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
|
4931 |
|
|
always @(posedge clk)
|
4932 |
|
|
if (rst) begin
|
4933 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
|
4934 |
|
|
calib_odt <= 2'b00 ;
|
4935 |
|
|
end else begin
|
4936 |
|
|
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
|
4937 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
|
4938 |
|
|
end else begin
|
4939 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
|
4940 |
|
|
end
|
4941 |
|
|
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* ||
|
4942 |
|
|
wrlvl_rank_done_r2 ||
|
4943 |
|
|
(wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin
|
4944 |
|
|
calib_odt[0] <= #TCQ 1'b0;
|
4945 |
|
|
calib_odt[1] <= #TCQ 1'b0;
|
4946 |
|
|
end else if (((DRAM_TYPE == "DDR3")
|
4947 |
|
|
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
|
4948 |
|
|
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)||
|
4949 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4950 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
4951 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
|
4952 |
|
|
complex_odt_ext ||
|
4953 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4954 |
|
|
(init_state_r == INIT_WRCAL_WRITE_READ) ||
|
4955 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4956 |
|
|
complex_ocal_odt_ext ||
|
4957 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)||
|
4958 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin
|
4959 |
|
|
// Dual rank in a single slot
|
4960 |
|
|
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
|
4961 |
|
|
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
|
4962 |
|
|
end else begin
|
4963 |
|
|
calib_odt[0] <= #TCQ 1'b0;
|
4964 |
|
|
calib_odt[1] <= #TCQ 1'b0;
|
4965 |
|
|
end
|
4966 |
|
|
end
|
4967 |
|
|
end else if ((nSLOTS == 2) && (RANKS == 2)) begin
|
4968 |
|
|
always @(posedge clk)
|
4969 |
|
|
if (rst)begin
|
4970 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
|
4971 |
|
|
calib_odt <= 2'b00 ;
|
4972 |
|
|
end else begin
|
4973 |
|
|
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
|
4974 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
|
4975 |
|
|
end else begin
|
4976 |
|
|
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
|
4977 |
|
|
end
|
4978 |
|
|
if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) ||
|
4979 |
|
|
((DRAM_TYPE == "DDR3") &&
|
4980 |
|
|
(RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin
|
4981 |
|
|
calib_odt[0] <= #TCQ 1'b0;
|
4982 |
|
|
calib_odt[1] <= #TCQ 1'b0;
|
4983 |
|
|
end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
|
4984 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
4985 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
4986 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
4987 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
4988 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
|
4989 |
|
|
// Quad rank in a single slot
|
4990 |
|
|
if (nCK_PER_CLK == 2) begin
|
4991 |
|
|
calib_odt[0]
|
4992 |
|
|
<= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;
|
4993 |
|
|
calib_odt[1]
|
4994 |
|
|
<= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;
|
4995 |
|
|
end else begin
|
4996 |
|
|
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
|
4997 |
|
|
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
|
4998 |
|
|
end
|
4999 |
|
|
// Turn on for idle rank during read if dynamic ODT is enabled in DDR3
|
5000 |
|
|
end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) &&
|
5001 |
|
|
((init_state_r == INIT_PI_PHASELOCK_READS) ||
|
5002 |
|
|
(init_state_r == INIT_MPR_READ) ||
|
5003 |
|
|
(init_state_r == INIT_RDLVL_STG1_READ) ||
|
5004 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
|
5005 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ) ||
|
5006 |
|
|
(init_state_r == INIT_OCLKDELAY_READ) ||
|
5007 |
|
|
(init_state_r == INIT_WRCAL_READ) ||
|
5008 |
|
|
(init_state_r == INIT_WRCAL_MULT_READS))) begin
|
5009 |
|
|
if (nCK_PER_CLK == 2) begin
|
5010 |
|
|
calib_odt[0]
|
5011 |
|
|
<= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;
|
5012 |
|
|
calib_odt[1]
|
5013 |
|
|
<= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;
|
5014 |
|
|
end else begin
|
5015 |
|
|
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
|
5016 |
|
|
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
|
5017 |
|
|
end
|
5018 |
|
|
// disable well before next command and before disabling write leveling
|
5019 |
|
|
end else if(cnt_cmd_done_m7_r ||
|
5020 |
|
|
(init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt))
|
5021 |
|
|
calib_odt <= #TCQ 2'b00;
|
5022 |
|
|
end
|
5023 |
|
|
end
|
5024 |
|
|
end else begin//USE AUX OUTPUT for routing CKE and ODT.
|
5025 |
|
|
if ((nSLOTS == 1) && (RANKS < 2)) begin
|
5026 |
|
|
always @(posedge clk)
|
5027 |
|
|
if (rst) begin
|
5028 |
|
|
calib_aux_out <= #TCQ 4'b0000;
|
5029 |
|
|
end else begin
|
5030 |
|
|
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
|
5031 |
|
|
calib_aux_out[0] <= #TCQ 1'b1;
|
5032 |
|
|
calib_aux_out[2] <= #TCQ 1'b1;
|
5033 |
|
|
end else begin
|
5034 |
|
|
calib_aux_out[0] <= #TCQ 1'b0;
|
5035 |
|
|
calib_aux_out[2] <= #TCQ 1'b0;
|
5036 |
|
|
end
|
5037 |
|
|
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
|
5038 |
|
|
wrlvl_rank_done || wrlvl_rank_done_r1 ||
|
5039 |
|
|
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
|
5040 |
|
|
calib_aux_out[1] <= #TCQ 1'b0;
|
5041 |
|
|
calib_aux_out[3] <= #TCQ 1'b0;
|
5042 |
|
|
end else if (((DRAM_TYPE == "DDR3")
|
5043 |
|
|
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
|
5044 |
|
|
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
|
5045 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
5046 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
5047 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
5048 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
5049 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
|
5050 |
|
|
// Quad rank in a single slot
|
5051 |
|
|
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
|
5052 |
|
|
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
|
5053 |
|
|
end else begin
|
5054 |
|
|
calib_aux_out[1] <= #TCQ 1'b0;
|
5055 |
|
|
calib_aux_out[3] <= #TCQ 1'b0;
|
5056 |
|
|
end
|
5057 |
|
|
end
|
5058 |
|
|
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
|
5059 |
|
|
always @(posedge clk)
|
5060 |
|
|
if (rst) begin
|
5061 |
|
|
calib_aux_out <= #TCQ 4'b0000;
|
5062 |
|
|
end else begin
|
5063 |
|
|
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
|
5064 |
|
|
calib_aux_out[0] <= #TCQ 1'b1;
|
5065 |
|
|
calib_aux_out[2] <= #TCQ 1'b1;
|
5066 |
|
|
end else begin
|
5067 |
|
|
calib_aux_out[0] <= #TCQ 1'b0;
|
5068 |
|
|
calib_aux_out[2] <= #TCQ 1'b0;
|
5069 |
|
|
end
|
5070 |
|
|
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
|
5071 |
|
|
wrlvl_rank_done_r2 ||
|
5072 |
|
|
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
|
5073 |
|
|
calib_aux_out[1] <= #TCQ 1'b0;
|
5074 |
|
|
calib_aux_out[3] <= #TCQ 1'b0;
|
5075 |
|
|
end else if (((DRAM_TYPE == "DDR3")
|
5076 |
|
|
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
|
5077 |
|
|
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
|
5078 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
5079 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
5080 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
5081 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
5082 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
|
5083 |
|
|
// Dual rank in a single slot
|
5084 |
|
|
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
|
5085 |
|
|
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
|
5086 |
|
|
end else begin
|
5087 |
|
|
calib_aux_out[1] <= #TCQ 1'b0;
|
5088 |
|
|
calib_aux_out[3] <= #TCQ 1'b0;
|
5089 |
|
|
end
|
5090 |
|
|
end
|
5091 |
|
|
end else if ((nSLOTS == 2) && (RANKS == 2)) begin
|
5092 |
|
|
always @(posedge clk)
|
5093 |
|
|
if (rst)
|
5094 |
|
|
calib_aux_out <= #TCQ 4'b0000;
|
5095 |
|
|
else begin
|
5096 |
|
|
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
|
5097 |
|
|
calib_aux_out[0] <= #TCQ 1'b1;
|
5098 |
|
|
calib_aux_out[2] <= #TCQ 1'b1;
|
5099 |
|
|
end else begin
|
5100 |
|
|
calib_aux_out[0] <= #TCQ 1'b0;
|
5101 |
|
|
calib_aux_out[2] <= #TCQ 1'b0;
|
5102 |
|
|
end
|
5103 |
|
|
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
|
5104 |
|
|
wrlvl_rank_done_r2 ||
|
5105 |
|
|
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
|
5106 |
|
|
calib_aux_out[1] <= #TCQ 1'b0;
|
5107 |
|
|
calib_aux_out[3] <= #TCQ 1'b0;
|
5108 |
|
|
end else if (((DRAM_TYPE == "DDR3")
|
5109 |
|
|
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
|
5110 |
|
|
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
|
5111 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
5112 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
|
5113 |
|
|
(init_state_r == INIT_WRCAL_WRITE) ||
|
5114 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
5115 |
|
|
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
|
5116 |
|
|
// Quad rank in a single slot
|
5117 |
|
|
if (nCK_PER_CLK == 2) begin
|
5118 |
|
|
calib_aux_out[1]
|
5119 |
|
|
<= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0;
|
5120 |
|
|
calib_aux_out[3]
|
5121 |
|
|
<= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0;
|
5122 |
|
|
end else begin
|
5123 |
|
|
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
|
5124 |
|
|
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
|
5125 |
|
|
end
|
5126 |
|
|
end else begin
|
5127 |
|
|
calib_aux_out[1] <= #TCQ 1'b0;
|
5128 |
|
|
calib_aux_out[3] <= #TCQ 1'b0;
|
5129 |
|
|
end
|
5130 |
|
|
end
|
5131 |
|
|
end
|
5132 |
|
|
end
|
5133 |
|
|
endgenerate
|
5134 |
|
|
|
5135 |
|
|
//*****************************************************************
|
5136 |
|
|
// memory address during init
|
5137 |
|
|
//*****************************************************************
|
5138 |
|
|
|
5139 |
|
|
always @(posedge clk)
|
5140 |
|
|
phy_data_full_r <= #TCQ phy_data_full;
|
5141 |
|
|
// verilint STARC-2.7.3.3b off
|
5142 |
|
|
always @(*)begin
|
5143 |
|
|
// Bus 0 for address/bank never used
|
5144 |
|
|
address_w = 'b0;
|
5145 |
|
|
bank_w = 'b0;
|
5146 |
|
|
if ((init_state_r == INIT_PRECHARGE) ||
|
5147 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
|
5148 |
|
|
(init_state_r == INIT_ZQCL) ||
|
5149 |
|
|
(init_state_r == INIT_DDR2_PRECHARGE)) begin
|
5150 |
|
|
// Set A10=1 for ZQ long calibration or Precharge All
|
5151 |
|
|
address_w = 'b0;
|
5152 |
|
|
address_w[10] = 1'b1;
|
5153 |
|
|
bank_w = 'b0;
|
5154 |
|
|
end else if (init_state_r == INIT_WRLVL_START) begin
|
5155 |
|
|
// Enable wrlvl in MR1
|
5156 |
|
|
bank_w[1:0] = 2'b01;
|
5157 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5158 |
|
|
address_w[2] = mr1_r[chip_cnt_r][0];
|
5159 |
|
|
address_w[6] = mr1_r[chip_cnt_r][1];
|
5160 |
|
|
address_w[9] = mr1_r[chip_cnt_r][2];
|
5161 |
|
|
address_w[7] = 1'b1;
|
5162 |
|
|
end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin
|
5163 |
|
|
// Finished with write leveling, disable wrlvl in MR1
|
5164 |
|
|
// For single rank disable Rtt_Nom
|
5165 |
|
|
bank_w[1:0] = 2'b01;
|
5166 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5167 |
|
|
address_w[2] = mr1_r[chip_cnt_r][0];
|
5168 |
|
|
address_w[6] = mr1_r[chip_cnt_r][1];
|
5169 |
|
|
address_w[9] = mr1_r[chip_cnt_r][2];
|
5170 |
|
|
end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin
|
5171 |
|
|
// Set RTT_WR in MR2 after write leveling disabled
|
5172 |
|
|
bank_w[1:0] = 2'b10;
|
5173 |
|
|
address_w = load_mr2[ROW_WIDTH-1:0];
|
5174 |
|
|
address_w[10:9] = mr2_r[chip_cnt_r];
|
5175 |
|
|
end else if (init_state_r == INIT_MPR_READ) begin
|
5176 |
|
|
address_w = 'b0;
|
5177 |
|
|
bank_w = 'b0;
|
5178 |
|
|
end else if (init_state_r == INIT_MPR_RDEN) begin
|
5179 |
|
|
// Enable MPR read with LMR3 and A2=1
|
5180 |
|
|
bank_w[BANK_WIDTH-1:0] = 'd3;
|
5181 |
|
|
address_w = {ROW_WIDTH{1'b0}};
|
5182 |
|
|
address_w[2] = 1'b1;
|
5183 |
|
|
end else if (init_state_r == INIT_MPR_DISABLE) begin
|
5184 |
|
|
// Disable MPR read with LMR3 and A2=0
|
5185 |
|
|
bank_w[BANK_WIDTH-1:0] = 'd3;
|
5186 |
|
|
address_w = {ROW_WIDTH{1'b0}};
|
5187 |
|
|
end else if ((init_state_r == INIT_REG_WRITE)&
|
5188 |
|
|
(DRAM_TYPE == "DDR3"))begin
|
5189 |
|
|
// bank_w is assigned a 3 bit value. In some
|
5190 |
|
|
// DDR2 cases there will be only two bank bits.
|
5191 |
|
|
//Qualifying the condition with DDR3
|
5192 |
|
|
bank_w = 'b0;
|
5193 |
|
|
address_w = 'b0;
|
5194 |
|
|
case (reg_ctrl_cnt_r)
|
5195 |
|
|
4'h1:begin
|
5196 |
|
|
address_w[4:0] = REG_RC1[4:0];
|
5197 |
|
|
bank_w = REG_RC1[7:5];
|
5198 |
|
|
end
|
5199 |
|
|
4'h2: address_w[4:0] = REG_RC2[4:0];
|
5200 |
|
|
4'h3: begin
|
5201 |
|
|
address_w[4:0] = REG_RC3[4:0];
|
5202 |
|
|
bank_w = REG_RC3[7:5];
|
5203 |
|
|
end
|
5204 |
|
|
4'h4: begin
|
5205 |
|
|
address_w[4:0] = REG_RC4[4:0];
|
5206 |
|
|
bank_w = REG_RC4[7:5];
|
5207 |
|
|
end
|
5208 |
|
|
4'h5: begin
|
5209 |
|
|
address_w[4:0] = REG_RC5[4:0];
|
5210 |
|
|
bank_w = REG_RC5[7:5];
|
5211 |
|
|
end
|
5212 |
|
|
4'h6: begin
|
5213 |
|
|
address_w[4:0] = REG_RC10[4:0];
|
5214 |
|
|
bank_w = REG_RC10[7:5];
|
5215 |
|
|
end
|
5216 |
|
|
4'h7: begin
|
5217 |
|
|
address_w[4:0] = REG_RC11[4:0];
|
5218 |
|
|
bank_w = REG_RC11[7:5];
|
5219 |
|
|
end
|
5220 |
|
|
default: address_w[4:0] = REG_RC0[4:0];
|
5221 |
|
|
endcase
|
5222 |
|
|
end else if (init_state_r == INIT_LOAD_MR) begin
|
5223 |
|
|
// If loading mode register, look at cnt_init_mr to determine
|
5224 |
|
|
// which MR is currently being programmed
|
5225 |
|
|
address_w = 'b0;
|
5226 |
|
|
bank_w = 'b0;
|
5227 |
|
|
if(DRAM_TYPE == "DDR3")begin
|
5228 |
|
|
if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin
|
5229 |
|
|
// end of the calibration programming correct
|
5230 |
|
|
// burst length
|
5231 |
|
|
if (TEST_AL == "0") begin
|
5232 |
|
|
bank_w[1:0] = 2'b00;
|
5233 |
|
|
address_w = load_mr0[ROW_WIDTH-1:0];
|
5234 |
|
|
address_w[8]= 1'b0; //Don't reset DLL
|
5235 |
|
|
end else begin
|
5236 |
|
|
// programming correct AL value
|
5237 |
|
|
bank_w[1:0] = 2'b01;
|
5238 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5239 |
|
|
if (TEST_AL == "CL-1")
|
5240 |
|
|
address_w[4:3]= 2'b01; // AL="CL-1"
|
5241 |
|
|
else
|
5242 |
|
|
address_w[4:3]= 2'b10; // AL="CL-2"
|
5243 |
|
|
end
|
5244 |
|
|
end else begin
|
5245 |
|
|
case (cnt_init_mr_r)
|
5246 |
|
|
INIT_CNT_MR2: begin
|
5247 |
|
|
bank_w[1:0] = 2'b10;
|
5248 |
|
|
address_w = load_mr2[ROW_WIDTH-1:0];
|
5249 |
|
|
address_w[10:9] = mr2_r[chip_cnt_r];
|
5250 |
|
|
end
|
5251 |
|
|
INIT_CNT_MR3: begin
|
5252 |
|
|
bank_w[1:0] = 2'b11;
|
5253 |
|
|
address_w = load_mr3[ROW_WIDTH-1:0];
|
5254 |
|
|
end
|
5255 |
|
|
INIT_CNT_MR1: begin
|
5256 |
|
|
bank_w[1:0] = 2'b01;
|
5257 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5258 |
|
|
address_w[2] = mr1_r[chip_cnt_r][0];
|
5259 |
|
|
address_w[6] = mr1_r[chip_cnt_r][1];
|
5260 |
|
|
address_w[9] = mr1_r[chip_cnt_r][2];
|
5261 |
|
|
end
|
5262 |
|
|
INIT_CNT_MR0: begin
|
5263 |
|
|
bank_w[1:0] = 2'b00;
|
5264 |
|
|
address_w = load_mr0[ROW_WIDTH-1:0];
|
5265 |
|
|
// fixing it to BL8 for calibration
|
5266 |
|
|
address_w[1:0] = 2'b00;
|
5267 |
|
|
end
|
5268 |
|
|
default: begin
|
5269 |
|
|
bank_w = {BANK_WIDTH{1'bx}};
|
5270 |
|
|
address_w = {ROW_WIDTH{1'bx}};
|
5271 |
|
|
end
|
5272 |
|
|
endcase
|
5273 |
|
|
end
|
5274 |
|
|
end else begin // DDR2
|
5275 |
|
|
case (cnt_init_mr_r)
|
5276 |
|
|
INIT_CNT_MR2: begin
|
5277 |
|
|
if(~ddr2_refresh_flag_r)begin
|
5278 |
|
|
bank_w[1:0] = 2'b10;
|
5279 |
|
|
address_w = load_mr2[ROW_WIDTH-1:0];
|
5280 |
|
|
end else begin // second set of lm commands
|
5281 |
|
|
bank_w[1:0] = 2'b00;
|
5282 |
|
|
address_w = load_mr0[ROW_WIDTH-1:0];
|
5283 |
|
|
address_w[8]= 1'b0;
|
5284 |
|
|
//MRS command without resetting DLL
|
5285 |
|
|
end
|
5286 |
|
|
end
|
5287 |
|
|
INIT_CNT_MR3: begin
|
5288 |
|
|
if(~ddr2_refresh_flag_r)begin
|
5289 |
|
|
bank_w[1:0] = 2'b11;
|
5290 |
|
|
address_w = load_mr3[ROW_WIDTH-1:0];
|
5291 |
|
|
end else begin // second set of lm commands
|
5292 |
|
|
bank_w[1:0] = 2'b00;
|
5293 |
|
|
address_w = load_mr0[ROW_WIDTH-1:0];
|
5294 |
|
|
address_w[8]= 1'b0;
|
5295 |
|
|
//MRS command without resetting DLL. Repeted again
|
5296 |
|
|
// because there is an extra state.
|
5297 |
|
|
end
|
5298 |
|
|
end
|
5299 |
|
|
INIT_CNT_MR1: begin
|
5300 |
|
|
bank_w[1:0] = 2'b01;
|
5301 |
|
|
if(~ddr2_refresh_flag_r)begin
|
5302 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5303 |
|
|
end else begin // second set of lm commands
|
5304 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5305 |
|
|
address_w[9:7] = 3'b111;
|
5306 |
|
|
//OCD default state
|
5307 |
|
|
end
|
5308 |
|
|
end
|
5309 |
|
|
INIT_CNT_MR0: begin
|
5310 |
|
|
if(~ddr2_refresh_flag_r)begin
|
5311 |
|
|
bank_w[1:0] = 2'b00;
|
5312 |
|
|
address_w = load_mr0[ROW_WIDTH-1:0];
|
5313 |
|
|
end else begin // second set of lm commands
|
5314 |
|
|
bank_w[1:0] = 2'b01;
|
5315 |
|
|
address_w = load_mr1[ROW_WIDTH-1:0];
|
5316 |
|
|
if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin
|
5317 |
|
|
// always disable odt for rank 1 and rank 3 as per SPEC
|
5318 |
|
|
address_w[2] = 'b0;
|
5319 |
|
|
address_w[6] = 'b0;
|
5320 |
|
|
end
|
5321 |
|
|
//OCD exit
|
5322 |
|
|
end
|
5323 |
|
|
end
|
5324 |
|
|
default: begin
|
5325 |
|
|
bank_w = {BANK_WIDTH{1'bx}};
|
5326 |
|
|
address_w = {ROW_WIDTH{1'bx}};
|
5327 |
|
|
end
|
5328 |
|
|
endcase
|
5329 |
|
|
end
|
5330 |
|
|
end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) ||
|
5331 |
|
|
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
5332 |
|
|
(init_state_r == INIT_RDLVL_STG1_READ) ||
|
5333 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ))) begin
|
5334 |
|
|
// Writing and reading PRBS pattern for read leveling stage 1
|
5335 |
|
|
// Need to support burst length 4 or 8. PRBS pattern will be
|
5336 |
|
|
// written to entire row and read back from the same row repeatedly
|
5337 |
|
|
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
|
5338 |
|
|
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
|
5339 |
|
|
if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) ||
|
5340 |
|
|
((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin
|
5341 |
|
|
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
|
5342 |
|
|
end else if (phy_data_full_r || (!new_burst_r))
|
5343 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
|
5344 |
|
|
else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin
|
5345 |
|
|
if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// ||
|
5346 |
|
|
// ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) )
|
5347 |
|
|
address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC;
|
5348 |
|
|
else
|
5349 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
|
5350 |
|
|
end
|
5351 |
|
|
//need to add address for complex oclkdelay calib
|
5352 |
|
|
end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
|
5353 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_READ))) begin
|
5354 |
|
|
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
|
5355 |
|
|
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
|
5356 |
|
|
if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin
|
5357 |
|
|
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
|
5358 |
|
|
end else if (phy_data_full_r || (!new_burst_r))
|
5359 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
|
5360 |
|
|
else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin
|
5361 |
|
|
if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) )
|
5362 |
|
|
// ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) )
|
5363 |
|
|
address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC;
|
5364 |
|
|
else
|
5365 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
|
5366 |
|
|
end
|
5367 |
|
|
|
5368 |
|
|
end else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||
|
5369 |
|
|
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
|
5370 |
|
|
(init_state_r == INIT_OCLKDELAY_READ)) begin
|
5371 |
|
|
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
|
5372 |
|
|
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
|
5373 |
|
|
if (oclk_wr_cnt == NUM_STG1_WR_RD)
|
5374 |
|
|
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
|
5375 |
|
|
else if (phy_data_full_r || (!new_burst_r))
|
5376 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
|
5377 |
|
|
else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)
|
5378 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
|
5379 |
|
|
end else if ((init_state_r == INIT_WRCAL_WRITE) ||
|
5380 |
|
|
(init_state_r == INIT_WRCAL_READ)) begin
|
5381 |
|
|
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
|
5382 |
|
|
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
|
5383 |
|
|
if (wrcal_wr_cnt == NUM_STG1_WR_RD)
|
5384 |
|
|
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
|
5385 |
|
|
else if (phy_data_full_r || (!new_burst_r))
|
5386 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
|
5387 |
|
|
else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)
|
5388 |
|
|
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
|
5389 |
|
|
end else if ((init_state_r == INIT_WRCAL_MULT_READS) ||
|
5390 |
|
|
(init_state_r == INIT_RDLVL_STG2_READ)) begin
|
5391 |
|
|
// when writing or reading back training pattern for read leveling stage2
|
5392 |
|
|
// need to support burst length of 4 or 8. This may mean issuing
|
5393 |
|
|
// multiple commands to cover the entire range of addresses accessed
|
5394 |
|
|
// during read leveling.
|
5395 |
|
|
// Hard coding A[12] to 1 so that it will always be burst length of 8
|
5396 |
|
|
// for DDR3. Does not have any effect on DDR2.
|
5397 |
|
|
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
|
5398 |
|
|
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
|
5399 |
|
|
address_w[COL_WIDTH-1:0] =
|
5400 |
|
|
{CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000};
|
5401 |
|
|
address_w[12] = 1'b1;
|
5402 |
|
|
end else if ((init_state_r == INIT_RDLVL_ACT) ||
|
5403 |
|
|
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
|
5404 |
|
|
(init_state_r == INIT_WRCAL_ACT) ||
|
5405 |
|
|
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
|
5406 |
|
|
(init_state_r == INIT_OCAL_CENTER_ACT) ||
|
5407 |
|
|
(init_state_r == INIT_OCLKDELAY_ACT)) begin
|
5408 |
|
|
|
5409 |
|
|
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
|
5410 |
|
|
//if (stg1_wr_rd_cnt == 'd22)
|
5411 |
|
|
// address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1;
|
5412 |
|
|
//else
|
5413 |
|
|
address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal :
|
5414 |
|
|
CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt;
|
5415 |
|
|
end else begin
|
5416 |
|
|
bank_w = {BANK_WIDTH{1'bx}};
|
5417 |
|
|
address_w = {ROW_WIDTH{1'bx}};
|
5418 |
|
|
end
|
5419 |
|
|
end
|
5420 |
|
|
// verilint STARC-2.7.3.3b on
|
5421 |
|
|
// registring before sending out
|
5422 |
|
|
generate
|
5423 |
|
|
genvar r,s;
|
5424 |
|
|
if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror
|
5425 |
|
|
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop
|
5426 |
|
|
always @(posedge clk) begin
|
5427 |
|
|
phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w;
|
5428 |
|
|
phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w;
|
5429 |
|
|
end
|
5430 |
|
|
end
|
5431 |
|
|
end else begin: gen_mirror
|
5432 |
|
|
// Control/addressing mirroring (optional for DDR3 dual rank DIMMs)
|
5433 |
|
|
// Mirror for the 2nd rank only. Logic needs to be enhanced to account
|
5434 |
|
|
// for multiple slots, currently only supports one slot, 2-rank config
|
5435 |
|
|
|
5436 |
|
|
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop
|
5437 |
|
|
for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba
|
5438 |
|
|
|
5439 |
|
|
always @(posedge clk)
|
5440 |
|
|
if (chip_cnt_r == 2'b00) begin
|
5441 |
|
|
phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s];
|
5442 |
|
|
end else begin
|
5443 |
|
|
phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)];
|
5444 |
|
|
end
|
5445 |
|
|
|
5446 |
|
|
end
|
5447 |
|
|
end
|
5448 |
|
|
|
5449 |
|
|
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop
|
5450 |
|
|
for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr
|
5451 |
|
|
always @(posedge clk)
|
5452 |
|
|
if (chip_cnt_r == 2'b00) begin
|
5453 |
|
|
phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s];
|
5454 |
|
|
end else begin
|
5455 |
|
|
phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[
|
5456 |
|
|
(s == 3) ? 4 :
|
5457 |
|
|
((s == 4) ? 3 :
|
5458 |
|
|
((s == 5) ? 6 :
|
5459 |
|
|
((s == 6) ? 5 :
|
5460 |
|
|
((s == 7) ? 8 :
|
5461 |
|
|
((s == 8) ? 7 : s)))))];
|
5462 |
|
|
end
|
5463 |
|
|
end
|
5464 |
|
|
end
|
5465 |
|
|
|
5466 |
|
|
end
|
5467 |
|
|
endgenerate
|
5468 |
|
|
|
5469 |
|
|
endmodule
|