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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_v2_3_phy_ocd_cntlr.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Steps through the major sections of the output clock
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// delay algorithm. Enabling various subblocks at the right time.
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//
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// Steps through each byte of the interface.
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//
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// Implements both the simple and complex data pattern.
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//
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// for each byte in interface
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// begin
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// Limit
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// Scan - which includes DQS centering
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// Precharge
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// end
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// set _wrlvl and _done equal to one
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ocd_cntlr #
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(parameter TCQ = 100,
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parameter DQS_CNT_WIDTH = 3,
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parameter DQS_WIDTH = 8)
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(/*AUTOARG*/
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// Outputs
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wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,
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ocd_prech_req, lim_start, complex_oclkdelay_calib_done,
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oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,
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phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,
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reset_scan,
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// Inputs
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clk, rst, prech_done, oclkdelay_calib_start,
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complex_oclkdelay_calib_start, lim_done, phy_rddata_en,
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po_counter_read_val, po_rdy, scan_done
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);
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localparam ONE = 1;
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input clk;
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input rst;
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output wrlvl_final, complex_wrlvl_final;
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reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;
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always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;
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always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;
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assign wrlvl_final = wrlvl_final_r;
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assign complex_wrlvl_final = complex_wrlvl_final_r;
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// Completed initial delay increment
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output oclk_init_delay_done; // may not need this... maybe for fast cal mode.
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assign oclk_init_delay_done = 1'b1;
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// Precharge done status from ddr_phy_init
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input prech_done;
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reg ocd_prech_req_ns, ocd_prech_req_r;
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always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;
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output ocd_prech_req;
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assign ocd_prech_req = ocd_prech_req_r;
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input oclkdelay_calib_start, complex_oclkdelay_calib_start;
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input lim_done;
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reg lim_start_ns, lim_start_r;
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always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;
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output lim_start;
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assign lim_start = lim_start_r;
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reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;
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always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;
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output complex_oclkdelay_calib_done;
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assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;
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reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;
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always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;
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output oclkdelay_calib_done;
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assign oclkdelay_calib_done = oclkdelay_calib_done_r;
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input phy_rddata_en;
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reg prde_r1, prde_r2;
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always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;
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always @(posedge clk) prde_r2 <= #TCQ prde_r1;
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wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;
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reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;
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always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;
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always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;
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always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;
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output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;
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assign phy_rddata_en_1 = phy_rddata_en_r1;
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assign phy_rddata_en_2 = phy_rddata_en_r2;
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assign phy_rddata_en_3 = phy_rddata_en_r3;
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input [8:0] po_counter_read_val;
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reg ocd_cntlr2stg2_dec_r;
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output ocd_cntlr2stg2_dec;
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assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;
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input po_rdy;
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reg [3:0] po_rd_wait_ns, po_rd_wait_r;
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always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;
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reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;
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always @(posedge clk) byte_r <= #TCQ byte_ns;
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output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
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assign oclkdelay_calib_cnt = {1'b0, byte_r};
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reg reset_scan_ns, reset_scan_r;
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always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;
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output reset_scan;
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assign reset_scan = reset_scan_r;
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input scan_done;
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reg [2:0] sm_ns, sm_r;
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always @(posedge clk) sm_r <= #TCQ sm_ns;
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// Primary state machine.
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always @(*) begin
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// Default next state assignments.
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byte_ns = byte_r;
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complex_wrlvl_final_ns = complex_wrlvl_final_r;
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lim_start_ns = lim_start_r;
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oclkdelay_calib_done_ns = oclkdelay_calib_done_r;
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complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;
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ocd_cntlr2stg2_dec_r = 1'b0;
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po_rd_wait_ns = po_rd_wait_r;
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if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;
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reset_scan_ns = reset_scan_r;
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wrlvl_final_ns = wrlvl_final_r;
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sm_ns = sm_r;
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ocd_prech_req_ns= 1'b0;
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if (rst == 1'b1) begin
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// RESET next states
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complex_oclkdelay_calib_done_ns = 1'b0;
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complex_wrlvl_final_ns = 1'b0;
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sm_ns = /*AK("READY")*/3'd0;
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lim_start_ns = 1'b0;
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oclkdelay_calib_done_ns = 1'b0;
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reset_scan_ns = 1'b1;
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wrlvl_final_ns = 1'b0;
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end else
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// State based actions and next states.
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case (sm_r)
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/*AL("READY")*/3'd0: begin
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byte_ns = {DQS_CNT_WIDTH{1'b0}};
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if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||
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complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)
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begin
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sm_ns = /*AK("LIMIT_START")*/3'd1;
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lim_start_ns = 1'b1;
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end
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end
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/*AL("LIMIT_START")*/3'd1:
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sm_ns = /*AK("LIMIT_WAIT")*/3'd2;
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/*AL("LIMIT_WAIT")*/3'd2:begin
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if (lim_done) begin
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lim_start_ns = 1'b0;
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sm_ns = /*AK("SCAN")*/3'd3;
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reset_scan_ns = 1'b0;
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end
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end
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/*AL("SCAN")*/3'd3:begin
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if (scan_done) begin
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reset_scan_ns = 1'b1;
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sm_ns = /*AK("COMPUTE")*/3'd4;
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end
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end
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/*AL("COMPUTE")*/3'd4:begin
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sm_ns = /*AK("PRECHARGE")*/3'd5;
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ocd_prech_req_ns = 1'b1;
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end
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/*AL("PRECHARGE")*/3'd5:begin
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if (prech_done) sm_ns = /*AK("DONE")*/3'd6;
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end
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/*AL("DONE")*/3'd6:begin
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byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
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if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
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byte_ns = {DQS_CNT_WIDTH{1'b0}};
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po_rd_wait_ns = 4'd8;
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sm_ns = /*AK("STG2_2_ZERO")*/3'd7;
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end else begin
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sm_ns = /*AK("LIMIT_START")*/3'd1;
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lim_start_ns = 1'b1;
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end
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end
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/*AL("STG2_2_ZERO")*/3'd7:
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if (~|po_rd_wait_r && po_rdy)
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if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;
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else begin
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if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
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sm_ns = /*AK("READY")*/3'd0;
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oclkdelay_calib_done_ns= 1'b1;
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wrlvl_final_ns = 1'b1;
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if (complex_oclkdelay_calib_start) begin
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complex_oclkdelay_calib_done_ns = 1'b1;
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complex_wrlvl_final_ns = 1'b1;
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end
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end else begin
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byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
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po_rd_wait_ns = 4'd8;
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end
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end // else: !if(|po_counter_read_val[5:0])
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endcase // case (sm_r)
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end // always @ begin
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endmodule // mig_7series_v2_3_ddr_phy_ocd_cntlr
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// Local Variables:
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// verilog-autolabel-prefix: "3'd"
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// End:
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