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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_v2_3_phy_ocd_po_cntlr.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Manipulates phaser out stg2f and stg3 on behalf of
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// scan and DQS centering.
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//
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// Maintains a shadow of the phaser out stg2f and stg3 tap settings.
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// The stg3 shadow is 6 bits, just like the phaser out. stg2f is
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// 8 bits. This allows the po_cntlr to track how far past the stg2f
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// saturation points we have gone when stepping to the limits of stg3.
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// This way we're can stay in sync when we step back from the saturation
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// limits.
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//
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// Looks at the edge values and determines which case has been
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// detected by the scan. Uses the results to drive the centering.
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//
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// Main state machine waits until it sees reset_scan go to zero. While
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// waiting it is writing the initialzation values to the stg2 and stg3
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// shadows. When reset_scan goes low, taps_set is pulsed. This
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// tells the sampling block to begin sampling. When the sampling
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// block has finished sampling this setting of the phaser out taps,
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// is signals by setting samp_done. When the main state machine
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// sees samp_done it sets the next value in the phaser out and
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// waits for the phaser out to be ready before beginning the next
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// sample.
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//
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// Turns out phy_init is sensitive to the length of the ocal_num_samples_done
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// pulse. Something like a precharge and activate time. Added feature
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// to resume_wait to wait at least 32 cycles between assertion and
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// subsequent deassertion of ocal_num_samples_done.
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//
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// Also turns out phy_init needs help to get into consistent
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// starting state for complex cal. This can be done by preseting
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// ocal_num_samples_done to one. Then waiting for 32 fabric clocks,
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// turn off _done and then assert _resume.
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//
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// Scanning algorithm.
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//
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// Phaser manipulation algoritm.
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ocd_po_cntlr #
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(parameter DQS_CNT_WIDTH = 3,
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parameter DQS_WIDTH = 8,
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parameter nCK_PER_CLK = 4,
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parameter TCQ = 100)
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(/*AUTOARG*/
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// Outputs
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scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start,
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oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc,
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ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final,
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cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets,
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scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy,
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taps_set, use_noise_window, ocal_scan_win_not_found,
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// Inputs
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clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim,
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lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start,
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po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done,
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mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz,
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fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o,
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scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy
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);
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input clk;
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input rst;
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input reset_scan;
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reg scan_done_r;
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output scan_done;
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assign scan_done = scan_done_r;
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output [5:0] simp_stg3_final_sel;
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reg cmplx_samples_done_ns, cmplx_samples_done_r;
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always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns;
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output ocal_num_samples_done_r;
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assign ocal_num_samples_done_r = cmplx_samples_done_r;
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// Write Level signals during OCLKDELAY calibration
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input [5:0] oclkdelay_init_val;
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input [5:0] lim2ocal_stg3_right_lim;
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input [5:0] lim2ocal_stg3_left_lim;
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input complex_oclkdelay_calib_start;
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reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r;
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always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns;
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output oclkdelay_center_calib_start;
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assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r;
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reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r;
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always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns;
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output oclkdelay_center_calib_done;
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assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r;
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reg oclk_center_write_resume_ns, oclk_center_write_resume_r;
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always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns;
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output oclk_center_write_resume;
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assign oclk_center_write_resume = oclk_center_write_resume_r;
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reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r;
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output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec;
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assign ocd2stg2_inc = ocd2stg2_inc_r;
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assign ocd2stg2_dec = ocd2stg2_dec_r;
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assign ocd2stg3_inc = ocd2stg3_inc_r;
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assign ocd2stg3_dec = ocd2stg3_dec_r;
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// Remember, two stage 2 steps for every stg 3 step. And we need a sign bit.
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reg [8:0] stg2_ns, stg2_r;
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always @(posedge clk) stg2_r <= #TCQ stg2_ns;
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reg [5:0] stg3_ns, stg3_r;
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always @(posedge clk) stg3_r <= #TCQ stg3_ns;
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output [5:0] stg3;
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assign stg3 = stg3_r;
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input [5:0] wl_po_fine_cnt_sel;
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input [8:0] po_counter_read_val;
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reg [5:0] po_counter_read_val_r;
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always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0];
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reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r;
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always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns;
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always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns;
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output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
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assign simp_stg3_final = simp_stg3_final_r;
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assign cmplx_stg3_final = cmplx_stg3_final_r;
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input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
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wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6;
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assign simp_stg3_final_sel = simp_stg3_final_shft[5:0];
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wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val;
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wire signed [8:0] stg2_steps = stg3_r > stg3_init
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? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)})
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: 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)});
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wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps;
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reg signed [8:0] stg2_target_r;
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always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns;
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reg [5:0] stg2_final_ns, stg2_final_r;
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always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns;
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always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1
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? 6'd0
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: stg2_target_r > 9'd63
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? 6'd63
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: stg2_target_r[5:0];
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wire final_stg2_inc = stg2_final_r > po_counter_read_val_r;
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wire final_stg2_dec = stg2_final_r < po_counter_read_val_r;
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wire left_lim = stg3_r == lim2ocal_stg3_left_lim;
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wire right_lim = stg3_r == lim2ocal_stg3_right_lim;
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reg [1:0] ninety_offsets_ns, ninety_offsets_r;
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always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns;
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output [1:0] ninety_offsets;
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assign ninety_offsets = ninety_offsets_r;
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reg scanning_right_ns, scanning_right_r;
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always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns;
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output scanning_right;
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assign scanning_right = scanning_right_r;
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reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r;
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always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns;
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always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns;
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output ocd_ktap_left, ocd_ktap_right;
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assign ocd_ktap_left = ocd_ktap_left_r;
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assign ocd_ktap_right = ocd_ktap_right_r;
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reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r;
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always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns;
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output ocd_edge_detect_rdy;
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assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r;
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input mmcm_edge_detect_done;
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input mmcm_lbclk_edge_aligned;
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input poc_backup;
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reg poc_backup_ns, poc_backup_r;
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always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
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reg taps_set_r;
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output taps_set;
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assign taps_set = taps_set_r;
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input phy_rddata_en_3;
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input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
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input z2f, f2z, o2f, f2o;
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wire zero = f2z && z2f;
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wire noise = z2f && f2o;
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wire oneeighty = f2o && o2f;
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reg win_not_found;
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reg [1:0] ninety_offsets_final;
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reg [5:0] left, right, current_edge;
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always @(*) begin
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left = lim2ocal_stg3_left_lim;
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right = lim2ocal_stg3_right_lim;
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ninety_offsets_final = 2'd0;
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win_not_found = 1'b0;
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if (zero) begin
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left = fuzz2zero;
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right = zero2fuzz;
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end
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else if (noise) begin
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left = zero2fuzz;
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right = fuzz2oneeighty;
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ninety_offsets_final = 2'd1;
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end
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else if (oneeighty) begin
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left = fuzz2oneeighty;
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right = oneeighty2fuzz;
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ninety_offsets_final = 2'd2;
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end
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else if (z2f) begin
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right = zero2fuzz;
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end
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else if (f2o) begin
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left = fuzz2oneeighty;
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ninety_offsets_final = 2'd2;
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end
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else if (f2z) begin
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left = fuzz2zero;
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end
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else win_not_found = 1'b1;
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current_edge = ocd_ktap_left_r ? left : right;
|
294 |
|
|
end // always @ begin
|
295 |
|
|
|
296 |
|
|
output use_noise_window;
|
297 |
|
|
assign use_noise_window = ninety_offsets == 2'd1;
|
298 |
|
|
|
299 |
|
|
reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r;
|
300 |
|
|
always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns;
|
301 |
|
|
output ocal_scan_win_not_found;
|
302 |
|
|
assign ocal_scan_win_not_found = ocal_scan_win_not_found_r;
|
303 |
|
|
|
304 |
|
|
wire inc_po_ns = current_edge > stg3_r;
|
305 |
|
|
wire dec_po_ns = current_edge < stg3_r;
|
306 |
|
|
reg inc_po_r, dec_po_r;
|
307 |
|
|
always @(posedge clk) inc_po_r <= #TCQ inc_po_ns;
|
308 |
|
|
always @(posedge clk) dec_po_r <= #TCQ dec_po_ns;
|
309 |
|
|
|
310 |
|
|
input scan_right;
|
311 |
|
|
|
312 |
|
|
wire left_stop = left_lim || scan_right;
|
313 |
|
|
wire right_stop = right_lim || o2f;
|
314 |
|
|
|
315 |
|
|
reg [4:0] resume_wait_ns, resume_wait_r;
|
316 |
|
|
always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns;
|
317 |
|
|
|
318 |
|
|
wire resume_wait = |resume_wait_r;
|
319 |
|
|
|
320 |
|
|
reg po_done_ns, po_done_r;
|
321 |
|
|
always @(posedge clk) po_done_r <= #TCQ po_done_ns;
|
322 |
|
|
|
323 |
|
|
input samp_done;
|
324 |
|
|
|
325 |
|
|
input po_rdy;
|
326 |
|
|
|
327 |
|
|
reg up_ns, up_r;
|
328 |
|
|
always @(posedge clk) up_r <= #TCQ up_ns;
|
329 |
|
|
|
330 |
|
|
reg [1:0] two_ns, two_r;
|
331 |
|
|
always @(posedge clk) two_r <= #TCQ two_ns;
|
332 |
|
|
|
333 |
|
|
|
334 |
|
|
/* wire stg2_zero = ~|stg2_r;
|
335 |
|
|
wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0
|
336 |
|
|
: stg2_r > 9'd63
|
337 |
|
|
? 9'd63
|
338 |
|
|
: stg2_r; */
|
339 |
|
|
|
340 |
|
|
reg [3:0] sm_ns, sm_r;
|
341 |
|
|
always @(posedge clk) sm_r <= #TCQ sm_ns;
|
342 |
|
|
|
343 |
|
|
(* dont_touch = "true" *) reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r;
|
344 |
|
|
always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns;
|
345 |
|
|
always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3
|
346 |
|
|
? ~phy_rddata_en_3_second_r
|
347 |
|
|
: phy_rddata_en_3_second_r);
|
348 |
|
|
(* dont_touch = "true" *) wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3;
|
349 |
|
|
|
350 |
|
|
reg po_center_wait;
|
351 |
|
|
reg po_slew;
|
352 |
|
|
reg po_finish_scan;
|
353 |
|
|
|
354 |
|
|
always @(*) begin
|
355 |
|
|
|
356 |
|
|
// Default next state assignments.
|
357 |
|
|
|
358 |
|
|
cmplx_samples_done_ns = cmplx_samples_done_r;
|
359 |
|
|
cmplx_stg3_final_ns = cmplx_stg3_final_r;
|
360 |
|
|
scanning_right_ns = scanning_right_r;
|
361 |
|
|
ninety_offsets_ns = ninety_offsets_r;
|
362 |
|
|
ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r;
|
363 |
|
|
ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r;
|
364 |
|
|
ocd_ktap_left_ns = ocd_ktap_left_r;
|
365 |
|
|
ocd_ktap_right_ns = ocd_ktap_right_r;
|
366 |
|
|
ocd2stg2_inc_r = 1'b0;
|
367 |
|
|
ocd2stg2_dec_r = 1'b0;
|
368 |
|
|
ocd2stg3_inc_r = 1'b0;
|
369 |
|
|
ocd2stg3_dec_r = 1'b0;
|
370 |
|
|
oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r;
|
371 |
|
|
oclkdelay_center_calib_done_ns = 1'b0;
|
372 |
|
|
oclk_center_write_resume_ns = oclk_center_write_resume_r;
|
373 |
|
|
po_center_wait = 1'b0;
|
374 |
|
|
po_done_ns = po_done_r;
|
375 |
|
|
po_finish_scan = 1'b0;
|
376 |
|
|
po_slew = 1'b0;
|
377 |
|
|
poc_backup_ns = poc_backup_r;
|
378 |
|
|
scan_done_r = 1'b0;
|
379 |
|
|
simp_stg3_final_ns = simp_stg3_final_r;
|
380 |
|
|
sm_ns = sm_r;
|
381 |
|
|
taps_set_r = 1'b0;
|
382 |
|
|
up_ns = up_r;
|
383 |
|
|
stg2_ns = stg2_r;
|
384 |
|
|
stg3_ns = stg3_r;
|
385 |
|
|
two_ns = two_r;
|
386 |
|
|
resume_wait_ns = resume_wait_r;
|
387 |
|
|
|
388 |
|
|
if (rst == 1'b1) begin
|
389 |
|
|
|
390 |
|
|
// RESET next states
|
391 |
|
|
cmplx_samples_done_ns = 1'b0;
|
392 |
|
|
ocal_scan_win_not_found_ns = 1'b0;
|
393 |
|
|
ocd_ktap_left_ns = 1'b0;
|
394 |
|
|
ocd_ktap_right_ns = 1'b0;
|
395 |
|
|
ocd_edge_detect_rdy_ns = 1'b0;
|
396 |
|
|
oclk_center_write_resume_ns = 1'b0;
|
397 |
|
|
oclkdelay_center_calib_start_ns = 1'b0;
|
398 |
|
|
po_done_ns = 1'b1;
|
399 |
|
|
resume_wait_ns = 5'd0;
|
400 |
|
|
sm_ns = /*AK("READY")*/4'd0;
|
401 |
|
|
|
402 |
|
|
end else
|
403 |
|
|
|
404 |
|
|
// State based actions and next states.
|
405 |
|
|
case (sm_r)
|
406 |
|
|
|
407 |
|
|
/*AL("READY")*/4'd0:begin
|
408 |
|
|
poc_backup_ns = 1'b0;
|
409 |
|
|
stg2_ns = {3'b0, wl_po_fine_cnt_sel};
|
410 |
|
|
stg3_ns = stg3_init;
|
411 |
|
|
scanning_right_ns = 1'b0;
|
412 |
|
|
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
|
413 |
|
|
if (!reset_scan && ~resume_wait) begin
|
414 |
|
|
cmplx_samples_done_ns = 1'b0;
|
415 |
|
|
ocal_scan_win_not_found_ns = 1'b0;
|
416 |
|
|
taps_set_r = 1'b1;
|
417 |
|
|
sm_ns = /*AK("SAMPLING")*/4'd1;
|
418 |
|
|
end
|
419 |
|
|
end
|
420 |
|
|
|
421 |
|
|
/*AL("SAMPLING")*/4'd1:begin
|
422 |
|
|
if (samp_done && use_samp_done) begin
|
423 |
|
|
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
|
424 |
|
|
scanning_right_ns = scanning_right_r || left_stop;
|
425 |
|
|
if (right_stop && scanning_right_r) begin
|
426 |
|
|
oclkdelay_center_calib_start_ns = 1'b1;
|
427 |
|
|
ocd_ktap_left_ns = 1'b1;
|
428 |
|
|
ocal_scan_win_not_found_ns = win_not_found;
|
429 |
|
|
sm_ns = /*AK("SLEW_PO")*/4'd3;
|
430 |
|
|
end else begin
|
431 |
|
|
if (scanning_right_ns) ocd2stg3_inc_r = 1'b1;
|
432 |
|
|
else ocd2stg3_dec_r = 1'b1;
|
433 |
|
|
sm_ns = /*AK("PO_WAIT")*/4'd2;
|
434 |
|
|
end
|
435 |
|
|
end
|
436 |
|
|
end
|
437 |
|
|
|
438 |
|
|
/*AL("PO_WAIT")*/4'd2:begin
|
439 |
|
|
if (po_done_r && ~resume_wait) begin
|
440 |
|
|
taps_set_r = 1'b1;
|
441 |
|
|
sm_ns = /*AK("SAMPLING")*/4'd1;
|
442 |
|
|
cmplx_samples_done_ns = 1'b0;
|
443 |
|
|
end
|
444 |
|
|
end
|
445 |
|
|
|
446 |
|
|
/*AL("SLEW_PO")*/4'd3:begin
|
447 |
|
|
po_slew = 1'b1;
|
448 |
|
|
ninety_offsets_ns = |ninety_offsets_final ? 2'b01 : 2'b00;
|
449 |
|
|
if (~resume_wait) begin
|
450 |
|
|
if (po_done_r) begin
|
451 |
|
|
if (inc_po_r) ocd2stg3_inc_r = 1'b1;
|
452 |
|
|
else if (dec_po_r) ocd2stg3_dec_r = 1'b1;
|
453 |
|
|
else if (~resume_wait) begin
|
454 |
|
|
cmplx_samples_done_ns = 1'b0;
|
455 |
|
|
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
|
456 |
|
|
oclk_center_write_resume_ns = 1'b1;
|
457 |
|
|
end
|
458 |
|
|
end // if (po_done)
|
459 |
|
|
end
|
460 |
|
|
end // case: 3'd3
|
461 |
|
|
|
462 |
|
|
/*AL("ALIGN_EDGES")*/4'd4:
|
463 |
|
|
if (~resume_wait) begin
|
464 |
|
|
if (mmcm_edge_detect_done) begin
|
465 |
|
|
ocd_edge_detect_rdy_ns = 1'b0;
|
466 |
|
|
if (ocd_ktap_left_r) begin
|
467 |
|
|
ocd_ktap_left_ns = 1'b0;
|
468 |
|
|
ocd_ktap_right_ns = 1'b1;
|
469 |
|
|
oclk_center_write_resume_ns = 1'b0;
|
470 |
|
|
sm_ns = /*AK("SLEW_PO")*/4'd3;
|
471 |
|
|
end else if (ocd_ktap_right_r) begin
|
472 |
|
|
ocd_ktap_right_ns = 1'b0;
|
473 |
|
|
sm_ns = /*AK("WAIT_ONE")*/4'd5;
|
474 |
|
|
end else if (~mmcm_lbclk_edge_aligned) begin
|
475 |
|
|
sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6;
|
476 |
|
|
oclk_center_write_resume_ns = 1'b0;
|
477 |
|
|
end else begin
|
478 |
|
|
if (ninety_offsets_r != ninety_offsets_final && ocd_edge_detect_rdy_r) begin
|
479 |
|
|
ninety_offsets_ns = ninety_offsets_r + 2'b01;
|
480 |
|
|
sm_ns = /*AK("WAIT_ONE")*/4'd5;
|
481 |
|
|
end else begin
|
482 |
|
|
oclk_center_write_resume_ns = 1'b0;
|
483 |
|
|
poc_backup_ns = poc_backup;
|
484 |
|
|
// stg2_ns = stg2_2_zero;
|
485 |
|
|
sm_ns = /*AK("FINISH_SCAN")*/4'd8;
|
486 |
|
|
end
|
487 |
|
|
end // else: !if(~mmcm_lbclk_edge_aligned)
|
488 |
|
|
end else ocd_edge_detect_rdy_ns = 1'b1;
|
489 |
|
|
end // if (~resume_wait)
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
/*AL("WAIT_ONE")*/4'd5:
|
493 |
|
|
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
|
494 |
|
|
|
495 |
|
|
/*AL("DQS_STOP_WAIT")*/4'd6:
|
496 |
|
|
if (~resume_wait) begin
|
497 |
|
|
ocd2stg3_dec_r = 1'b1;
|
498 |
|
|
sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7;
|
499 |
|
|
end
|
500 |
|
|
|
501 |
|
|
/*AL("CENTER_PO_WAIT")*/4'd7: begin
|
502 |
|
|
po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols.
|
503 |
|
|
if (po_done_r) begin
|
504 |
|
|
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
|
505 |
|
|
oclk_center_write_resume_ns = 1'b1;
|
506 |
|
|
end
|
507 |
|
|
end
|
508 |
|
|
|
509 |
|
|
/*AL("FINISH_SCAN")*/4'd8: begin
|
510 |
|
|
po_finish_scan = 1'b1;
|
511 |
|
|
if (resume_wait_r == 5'd1) begin
|
512 |
|
|
if (~poc_backup_r) begin
|
513 |
|
|
oclkdelay_center_calib_done_ns = 1'b1;
|
514 |
|
|
oclkdelay_center_calib_start_ns = 1'b0;
|
515 |
|
|
end
|
516 |
|
|
end
|
517 |
|
|
if (~resume_wait) begin
|
518 |
|
|
if (po_rdy)
|
519 |
|
|
if (poc_backup_r) begin
|
520 |
|
|
ocd2stg3_inc_r = 1'b1;
|
521 |
|
|
poc_backup_ns = 1'b0;
|
522 |
|
|
end
|
523 |
|
|
else if (~final_stg2_inc && ~final_stg2_dec) begin
|
524 |
|
|
if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
|
525 |
|
|
else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
|
526 |
|
|
sm_ns = /*AK("READY")*/4'd0;
|
527 |
|
|
scan_done_r = 1'b1;
|
528 |
|
|
end else begin
|
529 |
|
|
ocd2stg2_inc_r = final_stg2_inc;
|
530 |
|
|
ocd2stg2_dec_r = final_stg2_dec;
|
531 |
|
|
end
|
532 |
|
|
end // if (~resume_wait)
|
533 |
|
|
end // case: 4'd8
|
534 |
|
|
|
535 |
|
|
endcase // case (sm_r)
|
536 |
|
|
|
537 |
|
|
if (ocd2stg3_inc_r) begin
|
538 |
|
|
stg3_ns = stg3_r + 6'h1;
|
539 |
|
|
up_ns = 1'b0;
|
540 |
|
|
end
|
541 |
|
|
if (ocd2stg3_dec_r) begin
|
542 |
|
|
stg3_ns = stg3_r - 6'h1;
|
543 |
|
|
up_ns = 1'b1;
|
544 |
|
|
end
|
545 |
|
|
if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin
|
546 |
|
|
po_done_ns = 1'b0;
|
547 |
|
|
two_ns = 2'b00;
|
548 |
|
|
end
|
549 |
|
|
|
550 |
|
|
if (~po_done_r)
|
551 |
|
|
if (po_rdy)
|
552 |
|
|
if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1;
|
553 |
|
|
else begin
|
554 |
|
|
two_ns = two_r + 2'b1;
|
555 |
|
|
if (up_r) begin
|
556 |
|
|
stg2_ns = stg2_r + 9'b1;
|
557 |
|
|
if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1;
|
558 |
|
|
end else begin
|
559 |
|
|
stg2_ns = stg2_r - 9'b1;
|
560 |
|
|
if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1;
|
561 |
|
|
end
|
562 |
|
|
end // else: !if(two_r == 2'b10)
|
563 |
|
|
|
564 |
|
|
if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 5'b1;
|
565 |
|
|
else if (oclk_center_write_resume_ns ^ oclk_center_write_resume_r) resume_wait_ns = 5'd15;
|
566 |
|
|
else if (cmplx_samples_done_ns & ~cmplx_samples_done_r ||
|
567 |
|
|
complex_oclkdelay_calib_start & reset_scan ||
|
568 |
|
|
poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 5'd31;
|
569 |
|
|
else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 5'd1;
|
570 |
|
|
|
571 |
|
|
end // always @ begin
|
572 |
|
|
|
573 |
|
|
endmodule // mig_7series_v2_3_ddr_phy_ocd_po_cntlr
|
574 |
|
|
|
575 |
|
|
// Local Variables:
|
576 |
|
|
// verilog-autolabel-prefix: "4'd"
|
577 |
|
|
// End:
|