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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_ck_addr_cmd_delay.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_wrlvl_off_delay #
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(
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parameter TCQ = 100,
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parameter tCK = 3636,
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parameter nCK_PER_CLK = 2,
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parameter CLK_PERIOD = 4,
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parameter PO_INITIAL_DLY= 46,
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parameter DQS_CNT_WIDTH = 3,
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parameter DQS_WIDTH = 8,
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parameter N_CTL_LANES = 3
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)
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(
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input clk,
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input rst,
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input pi_fine_dly_dec_done,
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input cmd_delay_start,
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// Control lane being shifted using Phaser_Out fine delay taps
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output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt,
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// Inc/dec Phaser_Out fine delay line
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output reg po_s2_incdec_f,
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output reg po_en_s2_f,
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// Inc/dec Phaser_Out coarse delay line
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output reg po_s2_incdec_c,
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output reg po_en_s2_c,
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// Completed adjusting delays for dq, dqs for tdqss
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output po_ck_addr_cmd_delay_done,
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// completed decrementing initialPO delays
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output po_dec_done,
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output phy_ctl_rdy_dly
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);
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localparam TAP_LIMIT = 63;
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// PO fine delay tap resolution change by frequency. tCK > 2500, need
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// twice the amount of taps
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// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY;
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// coarse delay tap is added DQ/DQS to meet the TDQSS specification.
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localparam TDQSS_DLY = (tCK > 2500 )? 2: 1;
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reg delay_done;
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reg delay_done_r1;
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reg delay_done_r2;
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reg delay_done_r3;
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reg delay_done_r4;
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reg [5:0] po_delay_cnt_r;
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reg po_cnt_inc;
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reg cmd_delay_start_r1;
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reg cmd_delay_start_r2;
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reg cmd_delay_start_r3;
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reg cmd_delay_start_r4;
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reg cmd_delay_start_r5;
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reg cmd_delay_start_r6;
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reg po_delay_done;
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reg po_delay_done_r1;
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reg po_delay_done_r2;
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reg po_delay_done_r3;
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reg po_delay_done_r4;
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reg pi_fine_dly_dec_done_r;
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reg po_en_stg2_c;
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reg po_en_stg2_f;
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reg po_stg2_incdec_c;
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reg po_stg2_f_incdec;
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reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r;
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reg [DQS_CNT_WIDTH:0] lane_cnt_po_r;
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reg [5:0] delay_cnt_r;
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always @(posedge clk) begin
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cmd_delay_start_r1 <= #TCQ cmd_delay_start;
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cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1;
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cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2;
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cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3;
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cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4;
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cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5;
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pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done;
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end
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assign phy_ctl_rdy_dly = cmd_delay_start_r6;
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// logic for decrementing initial fine delay taps for all PO
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// Decrement done for add, ctrl and data phaser outs
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assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4;
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always @(posedge clk)
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if (rst || ~cmd_delay_start_r6 || po_delay_done) begin
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po_stg2_f_incdec <= #TCQ 1'b0;
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po_en_stg2_f <= #TCQ 1'b0;
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end else if (po_delay_cnt_r > 6'd0) begin
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po_en_stg2_f <= #TCQ ~po_en_stg2_f;
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end
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always @(posedge clk)
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if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0))
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// set all the PO delays to 31. Decrement from 46 to 31.
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// Requirement comes from dqs_found logic
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po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31);
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else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0))
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po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1;
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always @(posedge clk)
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if (rst)
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lane_cnt_po_r <= #TCQ 'd0;
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else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1))
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lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1;
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always @(posedge clk)
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if (rst || ~cmd_delay_start_r6 )
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po_delay_done <= #TCQ 1'b0;
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else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0))
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po_delay_done <= #TCQ 1'b1;
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always @(posedge clk) begin
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po_delay_done_r1 <= #TCQ po_delay_done;
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po_delay_done_r2 <= #TCQ po_delay_done_r1;
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po_delay_done_r3 <= #TCQ po_delay_done_r2;
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po_delay_done_r4 <= #TCQ po_delay_done_r3;
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end
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// logic to select between all PO delays and data path delay.
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always @(posedge clk) begin
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po_s2_incdec_f <= #TCQ po_stg2_f_incdec;
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po_en_s2_f <= #TCQ po_en_stg2_f;
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end
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// Logic to add 1/4 taps amount of delay to data path for tdqss.
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// After all the initial PO delays are decremented the 1/4 delay will
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// be added. Coarse delay taps will be added here .
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// Delay added only to data path
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assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r
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: delay_done_r4;
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always @(posedge clk)
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if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin
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po_stg2_incdec_c <= #TCQ 1'b1;
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po_en_stg2_c <= #TCQ 1'b0;
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end else if (delay_cnt_r > 6'd0) begin
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po_en_stg2_c <= #TCQ ~po_en_stg2_c;
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end
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always @(posedge clk)
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if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0))
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delay_cnt_r <= #TCQ TDQSS_DLY;
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else if ( po_en_stg2_c && (delay_cnt_r > 6'd0))
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delay_cnt_r <= #TCQ delay_cnt_r - 1;
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always @(posedge clk)
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if (rst)
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lane_cnt_dqs_c_r <= #TCQ 'd0;
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else if ( po_en_stg2_c && (delay_cnt_r == 6'd1))
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lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1;
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always @(posedge clk)
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if (rst || ~pi_fine_dly_dec_done_r)
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delay_done <= #TCQ 1'b0;
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else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0))
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delay_done <= #TCQ 1'b1;
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always @(posedge clk) begin
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delay_done_r1 <= #TCQ delay_done;
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delay_done_r2 <= #TCQ delay_done_r1;
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delay_done_r3 <= #TCQ delay_done_r2;
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delay_done_r4 <= #TCQ delay_done_r3;
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end
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always @(posedge clk) begin
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po_s2_incdec_c <= #TCQ po_stg2_incdec_c;
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po_en_s2_c <= #TCQ po_en_stg2_c;
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ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r;
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end
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endmodule
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