1 |
2 |
ZTEX |
//*****************************************************************************
|
2 |
|
|
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
|
3 |
|
|
//
|
4 |
|
|
// This file contains confidential and proprietary information
|
5 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
6 |
|
|
// international copyright and other intellectual property
|
7 |
|
|
// laws.
|
8 |
|
|
//
|
9 |
|
|
// DISCLAIMER
|
10 |
|
|
// This disclaimer is not a license and does not grant any
|
11 |
|
|
// rights to the materials distributed herewith. Except as
|
12 |
|
|
// otherwise provided in a valid license issued to you by
|
13 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
14 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
15 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
16 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
17 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
18 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
19 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
20 |
|
|
// including negligence, or under any other theory of
|
21 |
|
|
// liability) for any loss or damage of any kind or nature
|
22 |
|
|
// related to, arising under or in connection with these
|
23 |
|
|
// materials, including for any direct, or any indirect,
|
24 |
|
|
// special, incidental, or consequential loss or damage
|
25 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
26 |
|
|
// loss or damage suffered as a result of any action brought
|
27 |
|
|
// by a third party) even if such damage or loss was
|
28 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
29 |
|
|
// possibility of the same.
|
30 |
|
|
//
|
31 |
|
|
// CRITICAL APPLICATIONS
|
32 |
|
|
// Xilinx products are not designed or intended to be fail-
|
33 |
|
|
// safe, or for use in any application requiring fail-safe
|
34 |
|
|
// performance, such as life-support or safety devices or
|
35 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
36 |
|
|
// applications related to the deployment of airbags, or any
|
37 |
|
|
// other applications that could lead to death, personal
|
38 |
|
|
// injury, or severe property or environmental damage
|
39 |
|
|
// (individually and collectively, "Critical
|
40 |
|
|
// Applications"). Customer assumes the sole risk and
|
41 |
|
|
// liability of any use of Xilinx products in Critical
|
42 |
|
|
// Applications, subject only to applicable laws and
|
43 |
|
|
// regulations governing limitations on product liability.
|
44 |
|
|
//
|
45 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
46 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
47 |
|
|
//
|
48 |
|
|
//*****************************************************************************
|
49 |
|
|
// ____ ____
|
50 |
|
|
// / /\/ /
|
51 |
|
|
// /___/ \ / Vendor: Xilinx
|
52 |
|
|
// \ \ \/ Version:%version
|
53 |
|
|
// \ \ Application: MIG
|
54 |
|
|
// / / Filename: mig_7series_v2_3_poc_meta.v
|
55 |
|
|
// /___/ /\ Date Last Modified: $$
|
56 |
|
|
// \ \ / \ Date Created:Fri 24 Jan 2014
|
57 |
|
|
// \___\/\___\
|
58 |
|
|
//
|
59 |
|
|
//Device: Virtex-7
|
60 |
|
|
//Design Name: DDR3 SDRAM
|
61 |
|
|
//Purpose: Phaser output calibration edge store.
|
62 |
|
|
//Reference:
|
63 |
|
|
//Revision History:
|
64 |
|
|
//*****************************************************************************
|
65 |
|
|
|
66 |
|
|
`timescale 1 ps / 1 ps
|
67 |
|
|
|
68 |
|
|
module mig_7series_v2_3_poc_edge_store #
|
69 |
|
|
(parameter TCQ = 100,
|
70 |
|
|
parameter TAPCNTRWIDTH = 7,
|
71 |
|
|
parameter TAPSPERKCLK = 112)
|
72 |
|
|
(/*AUTOARG*/
|
73 |
|
|
// Outputs
|
74 |
|
|
fall_lead, fall_trail, rise_lead, rise_trail,
|
75 |
|
|
// Inputs
|
76 |
|
|
clk, run_polarity, run_end, select0, select1, tap, run
|
77 |
|
|
);
|
78 |
|
|
|
79 |
|
|
input clk;
|
80 |
|
|
|
81 |
|
|
input run_polarity;
|
82 |
|
|
input run_end;
|
83 |
|
|
input select0;
|
84 |
|
|
input select1;
|
85 |
|
|
input [TAPCNTRWIDTH-1:0] tap;
|
86 |
|
|
input [TAPCNTRWIDTH-1:0] run;
|
87 |
|
|
|
88 |
|
|
wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run
|
89 |
|
|
: tap - run;
|
90 |
|
|
|
91 |
|
|
wire run_end_this = run_end && select0 && select1;
|
92 |
|
|
|
93 |
|
|
reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r;
|
94 |
|
|
output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail;
|
95 |
|
|
assign fall_lead = fall_lead_r;
|
96 |
|
|
assign fall_trail = fall_trail_r;
|
97 |
|
|
assign rise_lead = rise_lead_r;
|
98 |
|
|
assign rise_trail = rise_trail_r;
|
99 |
|
|
|
100 |
|
|
wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r;
|
101 |
|
|
wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]
|
102 |
|
|
: rise_trail_r;
|
103 |
|
|
wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r;
|
104 |
|
|
wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]
|
105 |
|
|
: fall_trail_r;
|
106 |
|
|
|
107 |
|
|
always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns;
|
108 |
|
|
always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns;
|
109 |
|
|
always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns;
|
110 |
|
|
always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns;
|
111 |
|
|
|
112 |
|
|
endmodule // mig_7series_v2_3_poc_edge_store
|
113 |
|
|
|
114 |
|
|
// Local Variables:
|
115 |
|
|
// verilog-library-directories:(".")
|
116 |
|
|
// verilog-library-extensions:(".v")
|
117 |
|
|
// End:
|