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//*****************************************************************************
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// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version:%version
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// \ \ Application: MIG
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// / / Filename: mig_7series_v2_3_poc_meta.v
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// /___/ /\ Date Last Modified: $$
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// \ \ / \ Date Created:Tue 15 Jan 2014
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// \___\/\___\
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//
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//Device: Virtex-7
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//Design Name: DDR3 SDRAM
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//Purpose: Phaser output calibration meta controller.
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//
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// Compute center of the window set up with with the ktap_left,
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// ktap_right dance (hereafter "the window"). Also compute center of the
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// edge (hereafter "the edge") to be aligned in the center
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// of this window.
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//
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// Following the ktap_left/right dance, the to be centered edge is
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// always left at the right edge of the window
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// if SCANFROMRIGHT == 1, and the left edge otherwise.
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//
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// An assumption is the rise(0) case has a window wider than the noise on the
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// edge. The noise case with the possibly narrow window
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// will always be shifted by 90. And the fall(180) case is shifted by
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// 90 twice. Hence when we start, we can assume the center of the
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// edge is to the right/left of the the window center.
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//
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// The actual hardware does not necessarily monotonically appear to
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// move the window centers. Because of noise, it is possible for the
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// centered edge to move opposite the expected direction with a tap increment.
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//
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// This problem is solved by computing the absolute difference between
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// the centers and the circular distance between the centers. These will
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// be the same until the difference transits through zero. Then the circular
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// difference will jump to almost the value of TAPSPERKCLK.
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//
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// The window center computation is done at 1/2 tap increments to maintain
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// resolution through the divide by 2 for centering.
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//
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// There is a corner case of when the shift is greater than 180 degress. In
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// this case the absolute difference and the circular difference will be
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// unequal at the beginning of the alignment. This is solved by latching
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// if they are equal at the end of each cycle. The completion must see
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// that they were equal in the previous cycle, but are not equal in this cycle.
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//
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// Since the phaser out steps are of unknown size, it is possible to overshoot
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// the center. The previous difference is recorded and if its less than the current
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// difference, poc_backup is driven high.
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_poc_meta #
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(parameter SCANFROMRIGHT = 0,
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parameter TCQ = 100,
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parameter TAPCNTRWIDTH = 7,
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parameter TAPSPERKCLK = 112)
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(/*AUTOARG*/
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// Outputs
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mmcm_edge_detect_done, poc_backup, mmcm_lbclk_edge_aligned,
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// Inputs
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rst, clk, mmcm_edge_detect_rdy, run, run_polarity, run_end,
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rise_lead_right, rise_trail_left, rise_lead_center,
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rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,
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use_noise_window, ktap_at_right_edge, ktap_at_left_edge
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);
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localparam NINETY = TAPSPERKCLK/4;
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function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a,
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input [1:0] b,
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input integer base);
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integer offset_ii;
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begin
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offset_ii = (a + b * NINETY) < base
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? (a + b * NINETY)
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: (a + b * NINETY - base);
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offset = offset_ii[TAPCNTRWIDTH-1:0];
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end
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endfunction // offset
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function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
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input [TAPCNTRWIDTH-1:0] b,
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input integer base);
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begin
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mod_sub = (a>=b) ? a-b : a+base-b;
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end
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endfunction // mod_sub
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function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left,
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input [TAPCNTRWIDTH-1:0] diff,
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input integer base);
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integer center_ii;
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begin
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center_ii = ({left, 1'b0} + diff < base * 2)
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? {left, 1'b0} + diff + 32'h0
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: {left, 1'b0} + diff - base * 2;
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center = center_ii[TAPCNTRWIDTH:0];
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end
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endfunction // center
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input rst;
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input clk;
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input mmcm_edge_detect_rdy;
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wire reset_run_ends = rst || ~mmcm_edge_detect_rdy;
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// This input used only for the SVA.
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input [TAPCNTRWIDTH-1:0] run;
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input run_end;
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reg run_end_r, run_end_r1, run_end_r2, run_end_r3;
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always @(posedge clk) run_end_r <= #TCQ run_end;
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always @(posedge clk) run_end_r1 <= #TCQ run_end_r;
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always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;
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always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;
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input run_polarity;
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reg run_polarity_held_ns, run_polarity_held_r;
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always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;
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always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;
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reg [1:0] run_ends_r;
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reg [1:0] run_ends_ns;
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always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;
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always @(*) begin
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run_ends_ns = run_ends_r;
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if (reset_run_ends) run_ends_ns = 2'b0;
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else case (run_ends_r)
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2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};
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2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};
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endcase // case (run_ends_r)
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end
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reg done_r;
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wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;
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always @(posedge clk) done_r <= #TCQ done_ns;
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output mmcm_edge_detect_done;
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assign mmcm_edge_detect_done = done_r;
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input [TAPCNTRWIDTH-1:0] rise_lead_right;
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input [TAPCNTRWIDTH-1:0] rise_trail_left;
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input [TAPCNTRWIDTH-1:0] rise_lead_center;
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input [TAPCNTRWIDTH-1:0] rise_trail_center;
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input [TAPCNTRWIDTH-1:0] rise_trail_right;
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input [TAPCNTRWIDTH-1:0] rise_lead_left;
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input [1:0] ninety_offsets;
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wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;
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wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);
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wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);
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reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;
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always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;
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always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;
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wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);
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reg [TAPCNTRWIDTH-1:0] edge_diff_r;
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always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;
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wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);
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reg [TAPCNTRWIDTH:0] edge_center_r;
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always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;
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input use_noise_window;
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wire [TAPCNTRWIDTH-1:0] left = use_noise_window ? rise_lead_left : rise_trail_left;
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wire [TAPCNTRWIDTH-1:0] right = use_noise_window ? rise_trail_right : rise_lead_right;
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wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);
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reg [TAPCNTRWIDTH-1:0] center_diff_r;
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always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;
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wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);
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reg [TAPCNTRWIDTH:0] window_center_r;
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always @(posedge clk) window_center_r <= #TCQ window_center_ns;
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localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;
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wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};
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wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};
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wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center
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? right_center - left_center
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: right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;
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reg [TAPCNTRWIDTH+1:0] diff_r;
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always @(posedge clk) diff_r <= #TCQ diff_ns;
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wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2
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? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r
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: diff_r;
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reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;
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always @(posedge clk) prev_r <= #TCQ prev_ns;
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always @(*) prev_ns = done_ns ? diff_r : prev_r;
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input ktap_at_right_edge;
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input ktap_at_left_edge;
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wire centering = !(ktap_at_right_edge || ktap_at_left_edge);
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wire diffs_eq = abs_diff == diff_r;
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reg diffs_eq_ns, diffs_eq_r;
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always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);
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always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;
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reg edge_aligned_r;
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reg prev_valid_ns, prev_valid_r;
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always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;
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always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;
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wire indicate_alignment = ~rst && centering && done_ns;
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wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);
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always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;
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reg poc_backup_r;
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wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;
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always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
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output poc_backup;
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assign poc_backup = poc_backup_r;
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output mmcm_lbclk_edge_aligned;
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assign mmcm_lbclk_edge_aligned = edge_aligned_r;
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endmodule // mig_7series_v2_3_poc_meta
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// Local Variables:
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// verilog-library-directories:(".")
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// verilog-library-extensions:(".v")
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// End:
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