1 |
2 |
ZTEX |
MIG: 20:56:23 : xml_input_file: mig_a.prj
|
2 |
|
|
MIG: 20:56:23 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
3 |
|
|
MIG: 20:56:23 : xml_input_file: mig_a.prj
|
4 |
|
|
MIG: 20:56:23 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
5 |
|
|
MIG: 20:56:24 : xml_input_file: mig_a.prj
|
6 |
|
|
MIG: 20:56:24 : Absolute path of xml_input_file: mig_a.prj
|
7 |
|
|
MIG: 20:56:24 : xml_input_file: mig_a.prj
|
8 |
|
|
MIG: 20:56:24 : Absolute path of xml_input_file: mig_a.prj
|
9 |
|
|
MIG: 20:56:24 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
10 |
|
|
MIG: 20:56:24 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
11 |
|
|
MIG: 20:56:24 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
12 |
|
|
MIG: 20:56:24 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
13 |
|
|
MIG: 20:56:24 : In updateAllModelParams
|
14 |
|
|
MIG: 20:56:24 : IGN: mig_7series_0 <==> mig_7series_0
|
15 |
|
|
MIG: 20:56:24 : IGN: <==> 400
|
16 |
|
|
MIG: 20:56:24 : XGUI hdlLanguage: Verilog
|
17 |
|
|
MIG: 20:56:24 : xgui vivado_mode: xpg_pa
|
18 |
|
|
MIG: 20:56:24 : xgui hdlLanguage: Verilog -- hdlExt: v
|
19 |
|
|
MIG: 20:56:24 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
|
20 |
|
|
MIG: 20:56:25 :
|
21 |
|
|
MIG: 20:56:25 : Inside fn mem: DDR3
|
22 |
|
|
MIG: 20:56:25 : QDRII+ Inside fn ui: 100000000
|
23 |
|
|
MIG: 20:56:25 : cntrl: memtype: DDR3
|
24 |
|
|
MIG: 20:56:25 :
|
25 |
|
|
MIG: 20:56:25 : MMCM_VCO single ctrl param_name: MMCM_VCO -- possibleMaxVcoVal: 800
|
26 |
|
|
MIG: 20:56:25 :
|
27 |
|
|
MIG: 20:56:25 :
|
28 |
|
|
MIG: 20:56:25 :
|
29 |
|
|
MIG: 20:56:25 :
|
30 |
|
|
MIG: 20:56:25 : polarity_value: 1
|
31 |
|
|
MIG: 20:56:25 :
|
32 |
|
|
MIG: 20:56:25 :
|
33 |
|
|
MIG: 20:56:25 : cntrl: memtype: DDR3
|
34 |
|
|
MIG: 20:56:26 :
|
35 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_BANK_WIDTH ==> 3
|
36 |
|
|
MIG: 20:56:26 :
|
37 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_CK_WIDTH ==> 1
|
38 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_COL_WIDTH ==> 10
|
39 |
|
|
MIG: 20:56:26 :
|
40 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_CS_WIDTH ==> 1
|
41 |
|
|
MIG: 20:56:26 :
|
42 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_nCS_PER_RANK ==> 1
|
43 |
|
|
MIG: 20:56:26 :
|
44 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_CKE_WIDTH ==> 1
|
45 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
|
46 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
|
47 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DQ_PER_DM ==> 8
|
48 |
|
|
MIG: 20:56:26 :
|
49 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_DM_WIDTH ==> 2
|
50 |
|
|
MIG: 20:56:26 :
|
51 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_DQ_WIDTH ==> 16
|
52 |
|
|
MIG: 20:56:26 :
|
53 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_DQS_WIDTH ==> 2
|
54 |
|
|
MIG: 20:56:26 :
|
55 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
|
56 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DRAM_WIDTH ==> 8
|
57 |
|
|
MIG: 20:56:26 :
|
58 |
|
|
MIG: 20:56:26 : Valid Param: ECC ==> OFF
|
59 |
|
|
MIG: 20:56:26 :
|
60 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_DATA_WIDTH ==> 16
|
61 |
|
|
MIG: 20:56:26 : Invalid Param: ECC_TEST ==> "OFF"
|
62 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
|
63 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
|
64 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_nBANK_MACHS ==> 4
|
65 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_RANKS ==> 1
|
66 |
|
|
MIG: 20:56:26 :
|
67 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_ODT_WIDTH ==> 1
|
68 |
|
|
MIG: 20:56:26 :
|
69 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_ROW_WIDTH ==> 14
|
70 |
|
|
MIG: 20:56:26 :
|
71 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_ADDR_WIDTH ==> 28
|
72 |
|
|
MIG: 20:56:26 :
|
73 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_USE_CS_PORT ==> 0
|
74 |
|
|
MIG: 20:56:26 :
|
75 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_USE_DM_PORT ==> 1
|
76 |
|
|
MIG: 20:56:26 :
|
77 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_USE_ODT_PORT ==> 1
|
78 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
|
79 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
|
80 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
|
81 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
|
82 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
|
83 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_AL ==> "0"
|
84 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_nAL ==> 0
|
85 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BURST_MODE ==> "8"
|
86 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
|
87 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CL ==> 6
|
88 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CWL ==> 5
|
89 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
|
90 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_RTT_NOM ==> "40"
|
91 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_RTT_WR ==> "OFF"
|
92 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
|
93 |
|
|
MIG: 20:56:26 :
|
94 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_REG_CTRL ==> OFF
|
95 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CA_MIRROR ==> "OFF"
|
96 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
|
97 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
|
98 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
|
99 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
|
100 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
|
101 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
|
102 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
|
103 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
|
104 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
|
105 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MMCM_VCO ==> 800
|
106 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MMCM_MULT_F ==> 8
|
107 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
|
108 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tCKE ==> 5000
|
109 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tFAW ==> 40000
|
110 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tPRDI ==> 1_000_000
|
111 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tRAS ==> 35000
|
112 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tRCD ==> 13750
|
113 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tREFI ==> 7800000
|
114 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tRFC ==> 160000
|
115 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tRP ==> 13750
|
116 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tRRD ==> 7500
|
117 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tRTP ==> 7500
|
118 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tWTR ==> 7500
|
119 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tZQI ==> 128_000_000
|
120 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tZQCS ==> 64
|
121 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
|
122 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_SIMULATION ==> "FALSE"
|
123 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
|
124 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
|
125 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
|
126 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
|
127 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
|
128 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
|
129 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
|
130 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
|
131 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
|
132 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
|
133 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
|
134 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
|
135 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
|
136 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
|
137 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
|
138 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
|
139 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CAS_MAP ==> 12'h020
|
140 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
|
141 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
|
142 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
|
143 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
|
144 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PARITY_MAP ==> 12'h000
|
145 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_RAS_MAP ==> 12'h021
|
146 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_WE_MAP ==> 12'h022
|
147 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
|
148 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
|
149 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
|
150 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
|
151 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
|
152 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
|
153 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
|
154 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
|
155 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
|
156 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
|
157 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
|
158 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
|
159 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
|
160 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
|
161 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
|
162 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
|
163 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
|
164 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
|
165 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
|
166 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
|
167 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
|
168 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
|
169 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
|
170 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
|
171 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
|
172 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
|
173 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
|
174 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
|
175 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_USER_REFRESH ==> "OFF"
|
176 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_WRLVL ==> "ON"
|
177 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_ORDERING ==> "NORM"
|
178 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
|
179 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
|
180 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
|
181 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_TCQ ==> 100
|
182 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
|
183 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
|
184 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
|
185 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
|
186 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
|
187 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
|
188 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
|
189 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
|
190 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
|
191 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
|
192 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
|
193 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
|
194 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
|
195 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_STARVE_LIMIT ==> 2
|
196 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
|
197 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
|
198 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
|
199 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_tCK ==> 2500
|
200 |
|
|
MIG: 20:56:26 :
|
201 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_nCK_PER_CLK ==> 4
|
202 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
|
203 |
|
|
MIG: 20:56:26 :
|
204 |
|
|
MIG: 20:56:26 : Valid Param: DDR3_DEBUG_PORT ==> OFF
|
205 |
|
|
MIG: 20:56:26 :
|
206 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
|
207 |
|
|
MIG: 20:56:26 : Invalid Param: DDR3_RST_ACT_LOW ==> 1
|
208 |
|
|
MIG: 20:56:26 :
|
209 |
|
|
MIG: 20:56:26 :
|
210 |
|
|
MIG: 20:56:26 :
|
211 |
|
|
MIG: 20:56:26 : Same Interface
|
212 |
|
|
MIG: 21:38:28 : xml_input_file: mig_a.prj
|
213 |
|
|
MIG: 21:38:28 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
214 |
|
|
MIG: 21:38:28 : xml_input_file: mig_a.prj
|
215 |
|
|
MIG: 21:38:28 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
216 |
|
|
MIG: 21:38:28 : In updateAllModelParams
|
217 |
|
|
MIG: 21:38:28 : ################# RUNNING MIG BATCH ###################
|
218 |
|
|
MIG: 21:38:28 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
|
219 |
|
|
MIG: 21:38:28 : synp_flow: -- synthesis_mode: Other
|
220 |
|
|
MIG: 21:38:28 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
221 |
|
|
MIG: 21:38:28 : vivado_mode: xpg_pa
|
222 |
|
|
MIG: 21:38:28 : locked false
|
223 |
|
|
MIG: 21:38:28 : HDL Language: Verilog
|
224 |
|
|
MIG: 21:38:28 : compInfo: true
|
225 |
|
|
MIG: 21:38:28 : Vivado Options xc7a200t fbg484 -2
|
226 |
|
|
MIG: 21:38:28 : 1: xc7a35t 2: csg324 3: -1
|
227 |
|
|
MIG: 21:38:28 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
228 |
|
|
MIG: 21:38:28 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
229 |
|
|
MIG: 21:38:28 : I am in catch area
|
230 |
|
|
MIG: 21:38:28 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
|
231 |
|
|
MIG: 21:38:42 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
232 |
|
|
MIG: 21:38:42 : Component_Name: mig_7series_0
|
233 |
|
|
MIG: 21:38:46 : ################# RUNNING MIG BATCH ###################
|
234 |
|
|
MIG: 21:38:46 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
|
235 |
|
|
MIG: 21:38:46 : synp_flow: -- synthesis_mode: Other
|
236 |
|
|
MIG: 21:38:46 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
237 |
|
|
MIG: 21:38:46 : vivado_mode: xpg_pa
|
238 |
|
|
MIG: 21:38:46 : locked false
|
239 |
|
|
MIG: 21:38:46 : HDL Language: Verilog
|
240 |
|
|
MIG: 21:38:46 : compInfo: false
|
241 |
|
|
MIG: 21:38:46 : Vivado Options xc7a200t fbg484 -2
|
242 |
|
|
MIG: 21:38:46 : 1: xc7a35t 2: csg324 3: -1
|
243 |
|
|
MIG: 21:38:46 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
244 |
|
|
MIG: 21:38:46 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
245 |
|
|
MIG: 21:38:46 : I am in catch area
|
246 |
|
|
MIG: 21:38:46 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
|
247 |
|
|
MIG: 21:39:05 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
248 |
|
|
MIG: 21:39:05 : Component_Name: mig_7series_0
|
249 |
|
|
MIG: 21:39:19 : xml_input_file: mig_a.prj
|
250 |
|
|
MIG: 21:39:19 : Absolute path of xml_input_file: mig_a.prj
|
251 |
|
|
MIG: 21:39:19 : xml_input_file: mig_a.prj
|
252 |
|
|
MIG: 21:39:19 : Absolute path of xml_input_file: mig_a.prj
|
253 |
|
|
MIG: 21:39:19 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
254 |
|
|
MIG: 21:39:19 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
255 |
|
|
MIG: 21:39:19 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
256 |
|
|
MIG: 21:39:19 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
257 |
|
|
MIG: 21:39:19 : In updateAllModelParams
|
258 |
|
|
MIG: 21:39:19 : ################# RUNNING MIG BATCH ###################
|
259 |
|
|
MIG: 21:39:19 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
|
260 |
|
|
MIG: 21:39:19 : synp_flow: -- synthesis_mode: Other
|
261 |
|
|
MIG: 21:39:19 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
262 |
|
|
MIG: 21:39:19 : vivado_mode: xpg_pa
|
263 |
|
|
MIG: 21:39:19 : locked false
|
264 |
|
|
MIG: 21:39:19 : HDL Language: Verilog
|
265 |
|
|
MIG: 21:39:19 : compInfo: true
|
266 |
|
|
MIG: 21:39:19 : Vivado Options xc7a200t fbg484 -2
|
267 |
|
|
MIG: 21:39:19 : 1: xc7a35t 2: csg324 3: -1
|
268 |
|
|
MIG: 21:39:19 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
269 |
|
|
MIG: 21:39:19 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
270 |
|
|
MIG: 21:39:19 : I am in catch area
|
271 |
|
|
MIG: 21:39:19 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
|
272 |
|
|
MIG: 21:39:34 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
273 |
|
|
MIG: 21:39:34 : Component_Name: mig_7series_0
|
274 |
|
|
MIG: 21:39:38 : Running customizer.xit
|
275 |
|
|
MIG: 21:39:38 : ################# RUNNING MIG INTERACTIVE ###################
|
276 |
|
|
MIG: 21:39:38 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0
|
277 |
|
|
MIG: 21:39:38 : synp_flow: -- synthesis_mode: Other
|
278 |
|
|
MIG: 21:39:38 : outputDirectory: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/_tmp/
|
279 |
|
|
MIG: 21:39:38 : vivado_mode: xpg_pa
|
280 |
|
|
MIG: 21:39:38 : locked false
|
281 |
|
|
MIG: 21:39:38 : HDL Language: Verilog
|
282 |
|
|
MIG: 21:39:38 : compInfo: false
|
283 |
|
|
MIG: 21:39:38 : Vivado Options xc7a200t fbg484 -2
|
284 |
|
|
MIG: 21:39:38 : 1: xc7a35t 2: csg324 3: -1
|
285 |
|
|
MIG: 21:39:38 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
286 |
|
|
MIG: 21:39:38 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
287 |
|
|
MIG: 21:39:38 : I am in catch area
|
288 |
|
|
MIG: 21:39:38 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.out ...
|
289 |
|
|
MIG: 21:41:00 : Prasad before: xmlPropertyPrj -- mig_a.prj
|
290 |
|
|
MIG: 21:41:00 : Prasad After: xmlPropertyPrj -- mig_b.prj
|
291 |
|
|
MIG: 21:41:00 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/mig_b.prj
|
292 |
|
|
MIG: 21:41:00 : Component_Name: mig_7series_0
|
293 |
|
|
MIG: 21:41:00 : Moving mig_7series_0.veo ...
|
294 |
|
|
MIG: 21:41:00 : Moving mig_7series_0 ...
|
295 |
|
|
MIG: 21:41:00 : Moving mig_7series_0_xmdf.tcl ...
|
296 |
|
|
MIG: 21:41:00 : Moving log.txt ...
|
297 |
|
|
MIG: 21:41:00 : Sending back 0
|
298 |
|
|
MIG: 21:41:02 : xml_input_file: mig_b.prj
|
299 |
|
|
MIG: 21:41:02 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
300 |
|
|
MIG: 21:41:02 : xml_input_file: mig_b.prj
|
301 |
|
|
MIG: 21:41:02 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
302 |
|
|
MIG: 21:41:02 : In updateAllModelParams
|
303 |
|
|
MIG: 21:41:02 : IGN: mig_7series_0 <==> mig_7series_0
|
304 |
|
|
MIG: 21:41:02 : IGN: <==>
|
305 |
|
|
MIG: 21:41:02 : XGUI hdlLanguage: Verilog
|
306 |
|
|
MIG: 21:41:02 : xgui vivado_mode: xpg_pa
|
307 |
|
|
MIG: 21:41:02 : xgui hdlLanguage: Verilog -- hdlExt: v
|
308 |
|
|
MIG: 21:41:02 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
|
309 |
|
|
MIG: 21:41:03 : 1
|
310 |
|
|
MIG: 21:41:03 : Inside fn mem: DDR3
|
311 |
|
|
MIG: 21:41:03 : QDRII+ Inside fn ui: 100000000
|
312 |
|
|
MIG: 21:41:03 : cntrl: memtype: DDR3
|
313 |
|
|
MIG: 21:41:03 : 800
|
314 |
|
|
MIG: 21:41:03 : MMCM_VCO single ctrl param_name: MMCM_VCO -- possibleMaxVcoVal: 800
|
315 |
|
|
MIG: 21:41:03 :
|
316 |
|
|
MIG: 21:41:03 :
|
317 |
|
|
MIG: 21:41:03 : 100000000
|
318 |
|
|
MIG: 21:41:03 :
|
319 |
|
|
MIG: 21:41:03 : polarity_value: 1
|
320 |
|
|
MIG: 21:41:03 :
|
321 |
|
|
MIG: 21:41:03 : EXTERNAL
|
322 |
|
|
MIG: 21:41:03 : cntrl: memtype: DDR3
|
323 |
|
|
MIG: 21:41:03 :
|
324 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_BANK_WIDTH ==> 3
|
325 |
|
|
MIG: 21:41:03 :
|
326 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_CK_WIDTH ==> 1
|
327 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_COL_WIDTH ==> 10
|
328 |
|
|
MIG: 21:41:03 :
|
329 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_CS_WIDTH ==> 1
|
330 |
|
|
MIG: 21:41:03 :
|
331 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_nCS_PER_RANK ==> 1
|
332 |
|
|
MIG: 21:41:03 :
|
333 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_CKE_WIDTH ==> 1
|
334 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
|
335 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
|
336 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DQ_PER_DM ==> 8
|
337 |
|
|
MIG: 21:41:03 : 2
|
338 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_DM_WIDTH ==> 2
|
339 |
|
|
MIG: 21:41:03 : 16
|
340 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_DQ_WIDTH ==> 16
|
341 |
|
|
MIG: 21:41:03 : 2
|
342 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_DQS_WIDTH ==> 2
|
343 |
|
|
MIG: 21:41:03 :
|
344 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
|
345 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DRAM_WIDTH ==> 8
|
346 |
|
|
MIG: 21:41:03 :
|
347 |
|
|
MIG: 21:41:03 : Valid Param: ECC ==> OFF
|
348 |
|
|
MIG: 21:41:03 : 16
|
349 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_DATA_WIDTH ==> 16
|
350 |
|
|
MIG: 21:41:03 : Invalid Param: ECC_TEST ==> "OFF"
|
351 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
|
352 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
|
353 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_nBANK_MACHS ==> 4
|
354 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_RANKS ==> 1
|
355 |
|
|
MIG: 21:41:03 :
|
356 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_ODT_WIDTH ==> 1
|
357 |
|
|
MIG: 21:41:03 :
|
358 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_ROW_WIDTH ==> 14
|
359 |
|
|
MIG: 21:41:03 : 28
|
360 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_ADDR_WIDTH ==> 28
|
361 |
|
|
MIG: 21:41:03 : 0
|
362 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_USE_CS_PORT ==> 0
|
363 |
|
|
MIG: 21:41:03 :
|
364 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_USE_DM_PORT ==> 1
|
365 |
|
|
MIG: 21:41:03 :
|
366 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_USE_ODT_PORT ==> 1
|
367 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
|
368 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
|
369 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
|
370 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
|
371 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
|
372 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_AL ==> "0"
|
373 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_nAL ==> 0
|
374 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BURST_MODE ==> "8"
|
375 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
|
376 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CL ==> 6
|
377 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CWL ==> 5
|
378 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
|
379 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_RTT_NOM ==> "40"
|
380 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_RTT_WR ==> "OFF"
|
381 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
|
382 |
|
|
MIG: 21:41:03 :
|
383 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_REG_CTRL ==> OFF
|
384 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CA_MIRROR ==> "OFF"
|
385 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
|
386 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
|
387 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
|
388 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
|
389 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
|
390 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
|
391 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
|
392 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
|
393 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
|
394 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MMCM_VCO ==> 800
|
395 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MMCM_MULT_F ==> 8
|
396 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
|
397 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tCKE ==> 5000
|
398 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tFAW ==> 40000
|
399 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tPRDI ==> 1_000_000
|
400 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tRAS ==> 35000
|
401 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tRCD ==> 13750
|
402 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tREFI ==> 7800000
|
403 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tRFC ==> 160000
|
404 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tRP ==> 13750
|
405 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tRRD ==> 7500
|
406 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tRTP ==> 7500
|
407 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tWTR ==> 7500
|
408 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tZQI ==> 128_000_000
|
409 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tZQCS ==> 64
|
410 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
|
411 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_SIMULATION ==> "FALSE"
|
412 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
|
413 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
|
414 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
|
415 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
|
416 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
|
417 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
|
418 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
|
419 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
|
420 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
|
421 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
|
422 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
|
423 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
|
424 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
|
425 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
|
426 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
|
427 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
|
428 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CAS_MAP ==> 12'h023
|
429 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
|
430 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
|
431 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
|
432 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
|
433 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PARITY_MAP ==> 12'h000
|
434 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_RAS_MAP ==> 12'h022
|
435 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_WE_MAP ==> 12'h028
|
436 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
|
437 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
|
438 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
|
439 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
|
440 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
|
441 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
|
442 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
|
443 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
|
444 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
|
445 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
|
446 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
|
447 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
|
448 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
|
449 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
|
450 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
|
451 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
|
452 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
|
453 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
|
454 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
|
455 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
|
456 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
|
457 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
|
458 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
|
459 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
|
460 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
|
461 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
|
462 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
|
463 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
|
464 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_USER_REFRESH ==> "OFF"
|
465 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_WRLVL ==> "ON"
|
466 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_ORDERING ==> "NORM"
|
467 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
|
468 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
|
469 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
|
470 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_TCQ ==> 100
|
471 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
|
472 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
|
473 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
|
474 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
|
475 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
|
476 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
|
477 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
|
478 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
|
479 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
|
480 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
|
481 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
|
482 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
|
483 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
|
484 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_STARVE_LIMIT ==> 2
|
485 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
|
486 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
|
487 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
|
488 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_tCK ==> 2500
|
489 |
|
|
MIG: 21:41:03 : 4
|
490 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_nCK_PER_CLK ==> 4
|
491 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
|
492 |
|
|
MIG: 21:41:03 :
|
493 |
|
|
MIG: 21:41:03 : Valid Param: DDR3_DEBUG_PORT ==> OFF
|
494 |
|
|
MIG: 21:41:03 :
|
495 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
|
496 |
|
|
MIG: 21:41:03 : Invalid Param: DDR3_RST_ACT_LOW ==> 1
|
497 |
|
|
MIG: 21:41:03 : NOBUF
|
498 |
|
|
MIG: 21:41:03 : NOBUF
|
499 |
|
|
MIG: 21:41:03 :
|
500 |
|
|
MIG: 21:41:03 : Same Interface
|
501 |
|
|
MIG: 21:41:39 : Running synthesis.xit
|
502 |
|
|
MIG: 21:41:39 : IGN: mig_7series_0 <==> mig_7series_0
|
503 |
|
|
MIG: 21:41:39 : IGN: <==>
|
504 |
|
|
MIG: 21:41:39 : Running vlog_synth_rpr.xit
|
505 |
|
|
MIG: 21:41:39 : IGN: mig_7series_0 <==> mig_7series_0
|
506 |
|
|
MIG: 21:41:39 : IGN: <==>
|
507 |
|
|
MIG: 21:41:39 : Running simulation.xit
|
508 |
|
|
MIG: 21:41:39 : IGN: mig_7series_0 <==> mig_7series_0
|
509 |
|
|
MIG: 21:41:39 : IGN: <==>
|
510 |
|
|
MIG: 21:41:39 : Running vlog_sim_rpr.xit .. PRASAD DBG1
|
511 |
|
|
MIG: 21:41:39 : IGN: mig_7series_0 <==> mig_7series_0
|
512 |
|
|
MIG: 21:41:39 : IGN: <==>
|
513 |
|
|
MIG: 21:41:39 : Running implementation.xit
|
514 |
|
|
MIG: 21:41:39 : IGN: mig_7series_0 <==> mig_7series_0
|
515 |
|
|
MIG: 21:41:39 : IGN: <==>
|
516 |
|
|
MIG: 21:42:57 : xml_input_file: mig_b.prj
|
517 |
|
|
MIG: 21:42:58 : Absolute path of xml_input_file: mig_b.prj
|
518 |
|
|
MIG: 21:42:58 : xml_input_file: mig_b.prj
|
519 |
|
|
MIG: 21:42:58 : Absolute path of xml_input_file: mig_b.prj
|
520 |
|
|
MIG: 21:42:58 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
521 |
|
|
MIG: 21:42:58 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
522 |
|
|
MIG: 21:42:58 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
523 |
|
|
MIG: 21:42:58 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
524 |
|
|
MIG: 21:42:58 : In updateAllModelParams
|
525 |
|
|
MIG: 21:42:58 : IGN: mig_7series_0 <==> mig_7series_0
|
526 |
|
|
MIG: 21:42:58 : IGN: <==>
|
527 |
|
|
MIG: 21:42:58 : XGUI hdlLanguage: Verilog
|
528 |
|
|
MIG: 21:42:58 : xgui vivado_mode: xpg_pa
|
529 |
|
|
MIG: 21:42:58 : xgui hdlLanguage: Verilog -- hdlExt: v
|
530 |
|
|
MIG: 21:42:58 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
|
531 |
|
|
MIG: 21:42:59 :
|
532 |
|
|
MIG: 21:42:59 : Inside fn mem: DDR3
|
533 |
|
|
MIG: 21:42:59 : QDRII+ Inside fn ui: 100000000
|
534 |
|
|
MIG: 21:42:59 : cntrl: memtype: DDR3
|
535 |
|
|
MIG: 21:42:59 :
|
536 |
|
|
MIG: 21:42:59 : MMCM_VCO single ctrl param_name: MMCM_VCO -- possibleMaxVcoVal: 800
|
537 |
|
|
MIG: 21:42:59 :
|
538 |
|
|
MIG: 21:42:59 :
|
539 |
|
|
MIG: 21:42:59 :
|
540 |
|
|
MIG: 21:42:59 :
|
541 |
|
|
MIG: 21:42:59 : polarity_value: 1
|
542 |
|
|
MIG: 21:42:59 :
|
543 |
|
|
MIG: 21:42:59 :
|
544 |
|
|
MIG: 21:42:59 : cntrl: memtype: DDR3
|
545 |
|
|
MIG: 21:42:59 :
|
546 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_BANK_WIDTH ==> 3
|
547 |
|
|
MIG: 21:42:59 :
|
548 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_CK_WIDTH ==> 1
|
549 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_COL_WIDTH ==> 10
|
550 |
|
|
MIG: 21:42:59 :
|
551 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_CS_WIDTH ==> 1
|
552 |
|
|
MIG: 21:42:59 :
|
553 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_nCS_PER_RANK ==> 1
|
554 |
|
|
MIG: 21:42:59 :
|
555 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_CKE_WIDTH ==> 1
|
556 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
|
557 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
|
558 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DQ_PER_DM ==> 8
|
559 |
|
|
MIG: 21:42:59 :
|
560 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_DM_WIDTH ==> 2
|
561 |
|
|
MIG: 21:42:59 :
|
562 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_DQ_WIDTH ==> 16
|
563 |
|
|
MIG: 21:42:59 :
|
564 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_DQS_WIDTH ==> 2
|
565 |
|
|
MIG: 21:42:59 :
|
566 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
|
567 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DRAM_WIDTH ==> 8
|
568 |
|
|
MIG: 21:42:59 :
|
569 |
|
|
MIG: 21:42:59 : Valid Param: ECC ==> OFF
|
570 |
|
|
MIG: 21:42:59 :
|
571 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_DATA_WIDTH ==> 16
|
572 |
|
|
MIG: 21:42:59 : Invalid Param: ECC_TEST ==> "OFF"
|
573 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
|
574 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
|
575 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_nBANK_MACHS ==> 4
|
576 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_RANKS ==> 1
|
577 |
|
|
MIG: 21:42:59 :
|
578 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_ODT_WIDTH ==> 1
|
579 |
|
|
MIG: 21:42:59 :
|
580 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_ROW_WIDTH ==> 14
|
581 |
|
|
MIG: 21:42:59 :
|
582 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_ADDR_WIDTH ==> 28
|
583 |
|
|
MIG: 21:42:59 :
|
584 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_USE_CS_PORT ==> 0
|
585 |
|
|
MIG: 21:42:59 :
|
586 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_USE_DM_PORT ==> 1
|
587 |
|
|
MIG: 21:42:59 :
|
588 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_USE_ODT_PORT ==> 1
|
589 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
|
590 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
|
591 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
|
592 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
|
593 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
|
594 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_AL ==> "0"
|
595 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_nAL ==> 0
|
596 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BURST_MODE ==> "8"
|
597 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
|
598 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CL ==> 6
|
599 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CWL ==> 5
|
600 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
|
601 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_RTT_NOM ==> "40"
|
602 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_RTT_WR ==> "OFF"
|
603 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
|
604 |
|
|
MIG: 21:42:59 :
|
605 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_REG_CTRL ==> OFF
|
606 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CA_MIRROR ==> "OFF"
|
607 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
|
608 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
|
609 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
|
610 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
|
611 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
|
612 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
|
613 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
|
614 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
|
615 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
|
616 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MMCM_VCO ==> 800
|
617 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MMCM_MULT_F ==> 8
|
618 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
|
619 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tCKE ==> 5000
|
620 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tFAW ==> 40000
|
621 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tPRDI ==> 1_000_000
|
622 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tRAS ==> 35000
|
623 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tRCD ==> 13750
|
624 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tREFI ==> 7800000
|
625 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tRFC ==> 160000
|
626 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tRP ==> 13750
|
627 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tRRD ==> 7500
|
628 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tRTP ==> 7500
|
629 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tWTR ==> 7500
|
630 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tZQI ==> 128_000_000
|
631 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tZQCS ==> 64
|
632 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
|
633 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_SIMULATION ==> "FALSE"
|
634 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
|
635 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
|
636 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
|
637 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
|
638 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
|
639 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
|
640 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
|
641 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
|
642 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
|
643 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
|
644 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
|
645 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
|
646 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
|
647 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
|
648 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
|
649 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
|
650 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CAS_MAP ==> 12'h023
|
651 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
|
652 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
|
653 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
|
654 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
|
655 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PARITY_MAP ==> 12'h000
|
656 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_RAS_MAP ==> 12'h022
|
657 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_WE_MAP ==> 12'h028
|
658 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
|
659 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
|
660 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
|
661 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
|
662 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
|
663 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
|
664 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
|
665 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
|
666 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
|
667 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
|
668 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
|
669 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
|
670 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
|
671 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
|
672 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
|
673 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
|
674 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
|
675 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
|
676 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
|
677 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
|
678 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
|
679 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
|
680 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
|
681 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
|
682 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
|
683 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
|
684 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
|
685 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
|
686 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_USER_REFRESH ==> "OFF"
|
687 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_WRLVL ==> "ON"
|
688 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_ORDERING ==> "NORM"
|
689 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
|
690 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
|
691 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
|
692 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_TCQ ==> 100
|
693 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
|
694 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
|
695 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
|
696 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
|
697 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
|
698 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
|
699 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
|
700 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
|
701 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
|
702 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
|
703 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
|
704 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
|
705 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
|
706 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_STARVE_LIMIT ==> 2
|
707 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
|
708 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
|
709 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
|
710 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_tCK ==> 2500
|
711 |
|
|
MIG: 21:42:59 :
|
712 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_nCK_PER_CLK ==> 4
|
713 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
|
714 |
|
|
MIG: 21:42:59 :
|
715 |
|
|
MIG: 21:42:59 : Valid Param: DDR3_DEBUG_PORT ==> OFF
|
716 |
|
|
MIG: 21:42:59 :
|
717 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
|
718 |
|
|
MIG: 21:42:59 : Invalid Param: DDR3_RST_ACT_LOW ==> 1
|
719 |
|
|
MIG: 21:42:59 :
|
720 |
|
|
MIG: 21:42:59 :
|
721 |
|
|
MIG: 21:42:59 :
|
722 |
|
|
MIG: 21:42:59 : Same Interface
|
723 |
|
|
MIG: 21:43:04 : Running customizer.xit
|
724 |
|
|
MIG: 21:43:04 : ################# RUNNING MIG INTERACTIVE ###################
|
725 |
|
|
MIG: 21:43:04 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0
|
726 |
|
|
MIG: 21:43:04 : synp_flow: -- synthesis_mode: Other
|
727 |
|
|
MIG: 21:43:04 : outputDirectory: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/_tmp/
|
728 |
|
|
MIG: 21:43:04 : vivado_mode: xpg_pa
|
729 |
|
|
MIG: 21:43:04 : locked false
|
730 |
|
|
MIG: 21:43:04 : HDL Language: Verilog
|
731 |
|
|
MIG: 21:43:04 : compInfo: false
|
732 |
|
|
MIG: 21:43:04 : Vivado Options xc7a200t fbg484 -2
|
733 |
|
|
MIG: 21:43:04 : 1: xc7a200t 2: fbg484 3: -2
|
734 |
|
|
MIG: 21:43:04 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
735 |
|
|
MIG: 21:43:04 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
736 |
|
|
MIG: 21:43:04 : I am in catch area
|
737 |
|
|
MIG: 21:43:04 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.out ...
|
738 |
|
|
MIG: 21:44:20 : Prasad before: xmlPropertyPrj -- mig_b.prj
|
739 |
|
|
MIG: 21:44:20 : Prasad After: xmlPropertyPrj -- mig_a.prj
|
740 |
|
|
MIG: 21:44:20 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/mig_a.prj
|
741 |
|
|
MIG: 21:44:20 : Component_Name: mig_7series_0
|
742 |
|
|
MIG: 21:44:20 : Moving mig_7series_0.veo ...
|
743 |
|
|
MIG: 21:44:20 : Moving mig_7series_0 ...
|
744 |
|
|
MIG: 21:44:20 : Moving mig_7series_0_xmdf.tcl ...
|
745 |
|
|
MIG: 21:44:20 : Moving log.txt ...
|
746 |
|
|
MIG: 21:44:20 : Sending back 0
|
747 |
|
|
MIG: 21:44:22 : xml_input_file: mig_a.prj
|
748 |
|
|
MIG: 21:44:22 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
749 |
|
|
MIG: 21:44:22 : xml_input_file: mig_a.prj
|
750 |
|
|
MIG: 21:44:22 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
751 |
|
|
MIG: 21:44:22 : In updateAllModelParams
|
752 |
|
|
MIG: 21:44:22 : IGN: mig_7series_0 <==> mig_7series_0
|
753 |
|
|
MIG: 21:44:22 : IGN: <==>
|
754 |
|
|
MIG: 21:44:22 : XGUI hdlLanguage: Verilog
|
755 |
|
|
MIG: 21:44:22 : xgui vivado_mode: xpg_pa
|
756 |
|
|
MIG: 21:44:22 : xgui hdlLanguage: Verilog -- hdlExt: v
|
757 |
|
|
MIG: 21:44:22 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
|
758 |
|
|
MIG: 21:44:23 :
|
759 |
|
|
MIG: 21:44:23 : Inside fn mem: DDR3
|
760 |
|
|
MIG: 21:44:23 : QDRII+ Inside fn ui: 100000000
|
761 |
|
|
MIG: 21:44:23 : cntrl: memtype: DDR3
|
762 |
|
|
MIG: 21:44:23 :
|
763 |
|
|
MIG: 21:44:23 : MMCM_VCO single ctrl param_name: MMCM_VCO -- possibleMaxVcoVal: 800
|
764 |
|
|
MIG: 21:44:23 :
|
765 |
|
|
MIG: 21:44:23 :
|
766 |
|
|
MIG: 21:44:23 :
|
767 |
|
|
MIG: 21:44:23 :
|
768 |
|
|
MIG: 21:44:23 : polarity_value: 1
|
769 |
|
|
MIG: 21:44:23 :
|
770 |
|
|
MIG: 21:44:23 :
|
771 |
|
|
MIG: 21:44:23 : cntrl: memtype: DDR3
|
772 |
|
|
MIG: 21:44:23 :
|
773 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_BANK_WIDTH ==> 3
|
774 |
|
|
MIG: 21:44:23 :
|
775 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_CK_WIDTH ==> 1
|
776 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_COL_WIDTH ==> 10
|
777 |
|
|
MIG: 21:44:23 :
|
778 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_CS_WIDTH ==> 1
|
779 |
|
|
MIG: 21:44:23 :
|
780 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_nCS_PER_RANK ==> 1
|
781 |
|
|
MIG: 21:44:23 :
|
782 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_CKE_WIDTH ==> 1
|
783 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
|
784 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
|
785 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DQ_PER_DM ==> 8
|
786 |
|
|
MIG: 21:44:23 :
|
787 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_DM_WIDTH ==> 2
|
788 |
|
|
MIG: 21:44:23 :
|
789 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_DQ_WIDTH ==> 16
|
790 |
|
|
MIG: 21:44:23 :
|
791 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_DQS_WIDTH ==> 2
|
792 |
|
|
MIG: 21:44:23 :
|
793 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
|
794 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DRAM_WIDTH ==> 8
|
795 |
|
|
MIG: 21:44:23 :
|
796 |
|
|
MIG: 21:44:23 : Valid Param: ECC ==> OFF
|
797 |
|
|
MIG: 21:44:23 :
|
798 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_DATA_WIDTH ==> 16
|
799 |
|
|
MIG: 21:44:23 : Invalid Param: ECC_TEST ==> "OFF"
|
800 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
|
801 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
|
802 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_nBANK_MACHS ==> 4
|
803 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_RANKS ==> 1
|
804 |
|
|
MIG: 21:44:23 :
|
805 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_ODT_WIDTH ==> 1
|
806 |
|
|
MIG: 21:44:23 :
|
807 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_ROW_WIDTH ==> 14
|
808 |
|
|
MIG: 21:44:23 :
|
809 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_ADDR_WIDTH ==> 28
|
810 |
|
|
MIG: 21:44:23 :
|
811 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_USE_CS_PORT ==> 0
|
812 |
|
|
MIG: 21:44:23 :
|
813 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_USE_DM_PORT ==> 1
|
814 |
|
|
MIG: 21:44:23 :
|
815 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_USE_ODT_PORT ==> 1
|
816 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
|
817 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
|
818 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
|
819 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
|
820 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
|
821 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_AL ==> "0"
|
822 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_nAL ==> 0
|
823 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BURST_MODE ==> "8"
|
824 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
|
825 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CL ==> 6
|
826 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CWL ==> 5
|
827 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
|
828 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_RTT_NOM ==> "40"
|
829 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_RTT_WR ==> "OFF"
|
830 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
|
831 |
|
|
MIG: 21:44:23 :
|
832 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_REG_CTRL ==> OFF
|
833 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CA_MIRROR ==> "OFF"
|
834 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
|
835 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
|
836 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
|
837 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
|
838 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
|
839 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
|
840 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
|
841 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
|
842 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
|
843 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MMCM_VCO ==> 800
|
844 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MMCM_MULT_F ==> 8
|
845 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
|
846 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tCKE ==> 5000
|
847 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tFAW ==> 40000
|
848 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tPRDI ==> 1_000_000
|
849 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tRAS ==> 35000
|
850 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tRCD ==> 13750
|
851 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tREFI ==> 7800000
|
852 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tRFC ==> 160000
|
853 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tRP ==> 13750
|
854 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tRRD ==> 7500
|
855 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tRTP ==> 7500
|
856 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tWTR ==> 7500
|
857 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tZQI ==> 128_000_000
|
858 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tZQCS ==> 64
|
859 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
|
860 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_SIMULATION ==> "FALSE"
|
861 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
|
862 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
|
863 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
|
864 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
|
865 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
|
866 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
|
867 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
|
868 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
|
869 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
|
870 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
|
871 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
|
872 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
|
873 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
|
874 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
|
875 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
|
876 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
|
877 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CAS_MAP ==> 12'h023
|
878 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
|
879 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
|
880 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
|
881 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
|
882 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PARITY_MAP ==> 12'h000
|
883 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_RAS_MAP ==> 12'h022
|
884 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_WE_MAP ==> 12'h028
|
885 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
|
886 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
|
887 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
|
888 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
|
889 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
|
890 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
|
891 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
|
892 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
|
893 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
|
894 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
|
895 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
|
896 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
|
897 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
|
898 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
|
899 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
|
900 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
|
901 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
|
902 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
|
903 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
|
904 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
|
905 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
|
906 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
|
907 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
|
908 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
|
909 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
|
910 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
|
911 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
|
912 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
|
913 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_USER_REFRESH ==> "OFF"
|
914 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_WRLVL ==> "ON"
|
915 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_ORDERING ==> "NORM"
|
916 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
|
917 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
|
918 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
|
919 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_TCQ ==> 100
|
920 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
|
921 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
|
922 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
|
923 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
|
924 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
|
925 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
|
926 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
|
927 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
|
928 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
|
929 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
|
930 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
|
931 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
|
932 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
|
933 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_STARVE_LIMIT ==> 2
|
934 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
|
935 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
|
936 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
|
937 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_tCK ==> 2500
|
938 |
|
|
MIG: 21:44:23 :
|
939 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_nCK_PER_CLK ==> 4
|
940 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
|
941 |
|
|
MIG: 21:44:23 :
|
942 |
|
|
MIG: 21:44:23 : Valid Param: DDR3_DEBUG_PORT ==> OFF
|
943 |
|
|
MIG: 21:44:23 :
|
944 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
|
945 |
|
|
MIG: 21:44:23 : Invalid Param: DDR3_RST_ACT_LOW ==> 1
|
946 |
|
|
MIG: 21:44:23 :
|
947 |
|
|
MIG: 21:44:23 :
|
948 |
|
|
MIG: 21:44:23 :
|
949 |
|
|
MIG: 21:44:23 : Same Interface
|
950 |
|
|
MIG: 21:44:27 : ################# RUNNING MIG BATCH ###################
|
951 |
|
|
MIG: 21:44:27 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
|
952 |
|
|
MIG: 21:44:27 : synp_flow: -- synthesis_mode: Other
|
953 |
|
|
MIG: 21:44:27 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
954 |
|
|
MIG: 21:44:27 : vivado_mode: xpg_pa
|
955 |
|
|
MIG: 21:44:27 : locked false
|
956 |
|
|
MIG: 21:44:27 : HDL Language: Verilog
|
957 |
|
|
MIG: 21:44:27 : compInfo: false
|
958 |
|
|
MIG: 21:44:27 : Vivado Options xc7a200t fbg484 -2
|
959 |
|
|
MIG: 21:44:27 : 1: xc7a200t 2: fbg484 3: -2
|
960 |
|
|
MIG: 21:44:27 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
961 |
|
|
MIG: 21:44:27 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
962 |
|
|
MIG: 21:44:27 : I am in catch area
|
963 |
|
|
MIG: 21:44:27 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
|
964 |
|
|
MIG: 21:44:44 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
965 |
|
|
MIG: 21:44:44 : Component_Name: mig_7series_0
|
966 |
|
|
MIG: 21:44:44 : Moving mig_7series_0_xmdf.tcl ...
|
967 |
|
|
MIG: 21:44:44 : Moving mig_7series_0 ...
|
968 |
|
|
MIG: 21:44:44 : Moving mig_7series_0.veo ...
|
969 |
|
|
MIG: 21:44:44 : Moving log.txt ...
|
970 |
|
|
MIG: 21:45:59 : Running synthesis.xit
|
971 |
|
|
MIG: 21:45:59 : ################# RUNNING MIG BATCH ###################
|
972 |
|
|
MIG: 21:45:59 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
|
973 |
|
|
MIG: 21:45:59 : synp_flow: -- synthesis_mode: Other
|
974 |
|
|
MIG: 21:45:59 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
975 |
|
|
MIG: 21:45:59 : vivado_mode: xpg_pa
|
976 |
|
|
MIG: 21:45:59 : locked false
|
977 |
|
|
MIG: 21:45:59 : HDL Language: Verilog
|
978 |
|
|
MIG: 21:45:59 : compInfo: false
|
979 |
|
|
MIG: 21:45:59 : Vivado Options xc7a200t fbg484 -2
|
980 |
|
|
MIG: 21:45:59 : 1: xc7a200t 2: fbg484 3: -2
|
981 |
|
|
MIG: 21:45:59 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
982 |
|
|
MIG: 21:45:59 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
983 |
|
|
MIG: 21:45:59 : I am in catch area
|
984 |
|
|
MIG: 21:45:59 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
|
985 |
|
|
MIG: 21:46:17 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
986 |
|
|
MIG: 21:46:17 : Component_Name: mig_7series_0
|
987 |
|
|
MIG: 21:46:17 : Moving mig_7series_0_xmdf.tcl ...
|
988 |
|
|
MIG: 21:46:17 : Moving mig_7series_0 ...
|
989 |
|
|
MIG: 21:46:17 : Moving mig_7series_0.veo ...
|
990 |
|
|
MIG: 21:46:17 : Running vlog_synth_rpr.xit
|
991 |
|
|
MIG: 21:46:17 : IGN: mig_7series_0 <==> mig_7series_0
|
992 |
|
|
MIG: 21:46:17 : IGN: <==> 400
|
993 |
|
|
MIG: 21:46:17 : Running simulation.xit
|
994 |
|
|
MIG: 21:46:17 : ################# RUNNING MIG BATCH ###################
|
995 |
|
|
MIG: 21:46:17 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
|
996 |
|
|
MIG: 21:46:17 : synp_flow: -- synthesis_mode: Other
|
997 |
|
|
MIG: 21:46:17 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
998 |
|
|
MIG: 21:46:17 : vivado_mode: xpg_pa
|
999 |
|
|
MIG: 21:46:17 : locked false
|
1000 |
|
|
MIG: 21:46:17 : HDL Language: Verilog
|
1001 |
|
|
MIG: 21:46:17 : compInfo: false
|
1002 |
|
|
MIG: 21:46:17 : Vivado Options xc7a200t fbg484 -2
|
1003 |
|
|
MIG: 21:46:17 : 1: xc7a200t 2: fbg484 3: -2
|
1004 |
|
|
MIG: 21:46:17 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
|
1005 |
|
|
MIG: 21:46:17 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
|
1006 |
|
|
MIG: 21:46:17 : I am in catch area
|
1007 |
|
|
MIG: 21:46:17 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
|
1008 |
|
|
MIG: 21:46:35 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1009 |
|
|
MIG: 21:46:35 : Component_Name: mig_7series_0
|
1010 |
|
|
MIG: 21:46:35 : Moving mig_7series_0_xmdf.tcl ...
|
1011 |
|
|
MIG: 21:46:35 : Moving mig_7series_0 ...
|
1012 |
|
|
MIG: 21:46:35 : Moving mig_7series_0.veo ...
|
1013 |
|
|
MIG: 21:46:35 : Running vlog_sim_rpr.xit .. PRASAD DBG1
|
1014 |
|
|
MIG: 21:46:35 : IGN: mig_7series_0 <==> mig_7series_0
|
1015 |
|
|
MIG: 21:46:35 : IGN: <==> 400
|
1016 |
|
|
MIG: 21:46:35 : Running implementation.xit
|
1017 |
|
|
MIG: 21:46:35 : IGN: mig_7series_0 <==> mig_7series_0
|
1018 |
|
|
MIG: 21:46:35 : IGN: <==> 400
|
1019 |
|
|
MIG: 22:08:59 : xml_input_file: mig_a.prj
|
1020 |
|
|
MIG: 22:08:59 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1021 |
|
|
MIG: 22:08:59 : xml_input_file: mig_a.prj
|
1022 |
|
|
MIG: 22:08:59 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1023 |
|
|
MIG: 22:09:01 : xml_input_file: mig_a.prj
|
1024 |
|
|
MIG: 22:09:01 : Absolute path of xml_input_file: mig_a.prj
|
1025 |
|
|
MIG: 22:09:01 : xml_input_file: mig_a.prj
|
1026 |
|
|
MIG: 22:09:01 : Absolute path of xml_input_file: mig_a.prj
|
1027 |
|
|
MIG: 22:09:01 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1028 |
|
|
MIG: 22:09:01 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1029 |
|
|
MIG: 22:09:01 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1030 |
|
|
MIG: 22:09:01 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
|
1031 |
|
|
MIG: 22:09:01 : In updateAllModelParams
|
1032 |
|
|
MIG: 22:09:01 : IGN: mig_7series_0 <==> mig_7series_0
|
1033 |
|
|
MIG: 22:09:01 : IGN: <==> 400
|
1034 |
|
|
MIG: 22:09:01 : XGUI hdlLanguage: Verilog
|
1035 |
|
|
MIG: 22:09:01 : xgui vivado_mode: xpg_pa
|
1036 |
|
|
MIG: 22:09:01 : xgui hdlLanguage: Verilog -- hdlExt: v
|
1037 |
|
|
MIG: 22:09:01 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
|
1038 |
|
|
MIG: 22:09:02 :
|
1039 |
|
|
MIG: 22:09:02 : Inside fn mem: DDR3
|
1040 |
|
|
MIG: 22:09:02 : QDRII+ Inside fn ui: 100000000
|
1041 |
|
|
MIG: 22:09:02 : cntrl: memtype: DDR3
|
1042 |
|
|
MIG: 22:09:02 :
|
1043 |
|
|
MIG: 22:09:02 : MMCM_VCO single ctrl param_name: MMCM_VCO -- possibleMaxVcoVal: 800
|
1044 |
|
|
MIG: 22:09:02 :
|
1045 |
|
|
MIG: 22:09:02 :
|
1046 |
|
|
MIG: 22:09:02 :
|
1047 |
|
|
MIG: 22:09:02 :
|
1048 |
|
|
MIG: 22:09:02 : polarity_value: 1
|
1049 |
|
|
MIG: 22:09:02 :
|
1050 |
|
|
MIG: 22:09:02 :
|
1051 |
|
|
MIG: 22:09:02 : cntrl: memtype: DDR3
|
1052 |
|
|
MIG: 22:09:02 :
|
1053 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_BANK_WIDTH ==> 3
|
1054 |
|
|
MIG: 22:09:02 :
|
1055 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_CK_WIDTH ==> 1
|
1056 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_COL_WIDTH ==> 10
|
1057 |
|
|
MIG: 22:09:02 :
|
1058 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_CS_WIDTH ==> 1
|
1059 |
|
|
MIG: 22:09:02 :
|
1060 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_nCS_PER_RANK ==> 1
|
1061 |
|
|
MIG: 22:09:02 :
|
1062 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_CKE_WIDTH ==> 1
|
1063 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
|
1064 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
|
1065 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DQ_PER_DM ==> 8
|
1066 |
|
|
MIG: 22:09:02 :
|
1067 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_DM_WIDTH ==> 2
|
1068 |
|
|
MIG: 22:09:02 :
|
1069 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_DQ_WIDTH ==> 16
|
1070 |
|
|
MIG: 22:09:02 :
|
1071 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_DQS_WIDTH ==> 2
|
1072 |
|
|
MIG: 22:09:02 :
|
1073 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
|
1074 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DRAM_WIDTH ==> 8
|
1075 |
|
|
MIG: 22:09:02 :
|
1076 |
|
|
MIG: 22:09:02 : Valid Param: ECC ==> OFF
|
1077 |
|
|
MIG: 22:09:02 :
|
1078 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_DATA_WIDTH ==> 16
|
1079 |
|
|
MIG: 22:09:02 : Invalid Param: ECC_TEST ==> "OFF"
|
1080 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
|
1081 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
|
1082 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_nBANK_MACHS ==> 4
|
1083 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_RANKS ==> 1
|
1084 |
|
|
MIG: 22:09:02 :
|
1085 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_ODT_WIDTH ==> 1
|
1086 |
|
|
MIG: 22:09:02 :
|
1087 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_ROW_WIDTH ==> 14
|
1088 |
|
|
MIG: 22:09:02 :
|
1089 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_ADDR_WIDTH ==> 28
|
1090 |
|
|
MIG: 22:09:02 :
|
1091 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_USE_CS_PORT ==> 0
|
1092 |
|
|
MIG: 22:09:02 :
|
1093 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_USE_DM_PORT ==> 1
|
1094 |
|
|
MIG: 22:09:02 :
|
1095 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_USE_ODT_PORT ==> 1
|
1096 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
|
1097 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
|
1098 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
|
1099 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
|
1100 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
|
1101 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_AL ==> "0"
|
1102 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_nAL ==> 0
|
1103 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BURST_MODE ==> "8"
|
1104 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
|
1105 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CL ==> 6
|
1106 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CWL ==> 5
|
1107 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
|
1108 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_RTT_NOM ==> "40"
|
1109 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_RTT_WR ==> "OFF"
|
1110 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
|
1111 |
|
|
MIG: 22:09:02 :
|
1112 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_REG_CTRL ==> OFF
|
1113 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CA_MIRROR ==> "OFF"
|
1114 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
|
1115 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
|
1116 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
|
1117 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
|
1118 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
|
1119 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
|
1120 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
|
1121 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
|
1122 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
|
1123 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MMCM_VCO ==> 800
|
1124 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MMCM_MULT_F ==> 8
|
1125 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
|
1126 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tCKE ==> 5000
|
1127 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tFAW ==> 40000
|
1128 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tPRDI ==> 1_000_000
|
1129 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tRAS ==> 35000
|
1130 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tRCD ==> 13750
|
1131 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tREFI ==> 7800000
|
1132 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tRFC ==> 160000
|
1133 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tRP ==> 13750
|
1134 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tRRD ==> 7500
|
1135 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tRTP ==> 7500
|
1136 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tWTR ==> 7500
|
1137 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tZQI ==> 128_000_000
|
1138 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tZQCS ==> 64
|
1139 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
|
1140 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_SIMULATION ==> "FALSE"
|
1141 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
|
1142 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
|
1143 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
|
1144 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
|
1145 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
|
1146 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
|
1147 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
|
1148 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
|
1149 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
|
1150 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
|
1151 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
|
1152 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
|
1153 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
|
1154 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
|
1155 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
|
1156 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
|
1157 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CAS_MAP ==> 12'h023
|
1158 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
|
1159 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
|
1160 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
|
1161 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
|
1162 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PARITY_MAP ==> 12'h000
|
1163 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_RAS_MAP ==> 12'h022
|
1164 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_WE_MAP ==> 12'h028
|
1165 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
|
1166 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
|
1167 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
|
1168 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1169 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1170 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1171 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1172 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1173 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1174 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1175 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1176 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1177 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1178 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1179 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1180 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1181 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1182 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1183 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
|
1184 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
|
1185 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
|
1186 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
|
1187 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
|
1188 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
|
1189 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
|
1190 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
|
1191 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
|
1192 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
|
1193 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_USER_REFRESH ==> "OFF"
|
1194 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_WRLVL ==> "ON"
|
1195 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_ORDERING ==> "NORM"
|
1196 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
|
1197 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
|
1198 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
|
1199 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_TCQ ==> 100
|
1200 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
|
1201 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
|
1202 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
|
1203 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
|
1204 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
|
1205 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
|
1206 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
|
1207 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
|
1208 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
|
1209 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
|
1210 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
|
1211 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
|
1212 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
|
1213 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_STARVE_LIMIT ==> 2
|
1214 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
|
1215 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
|
1216 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
|
1217 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_tCK ==> 2500
|
1218 |
|
|
MIG: 22:09:02 :
|
1219 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_nCK_PER_CLK ==> 4
|
1220 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
|
1221 |
|
|
MIG: 22:09:02 :
|
1222 |
|
|
MIG: 22:09:02 : Valid Param: DDR3_DEBUG_PORT ==> OFF
|
1223 |
|
|
MIG: 22:09:02 :
|
1224 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
|
1225 |
|
|
MIG: 22:09:02 : Invalid Param: DDR3_RST_ACT_LOW ==> 1
|
1226 |
|
|
MIG: 22:09:02 :
|
1227 |
|
|
MIG: 22:09:02 :
|
1228 |
|
|
MIG: 22:09:02 :
|
1229 |
|
|
MIG: 22:09:02 : Same Interface
|