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ZTEX |
library ieee;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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--
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-- Top level module: glues everything together.
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--
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entity memfifo is
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port (
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fxclk_in : in std_logic;
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ifclk_in : in std_logic;
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reset : in std_logic;
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mode : in std_logic_vector(1 downto 0);
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-- debug
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led1 : out std_logic_vector(9 downto 0);
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led2 : out std_logic_vector(19 downto 0);
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SW8 : in std_logic;
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SW10 : in std_logic;
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-- ddr3
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ddr3_dq : inout std_logic_vector(15 downto 0);
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ddr3_dqs_n : inout std_logic_vector(1 downto 0);
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ddr3_dqs_p : inout std_logic_vector(1 downto 0);
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ddr3_addr : out std_logic_vector(13 downto 0);
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ddr3_ba : out std_logic_vector(2 downto 0);
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ddr3_ras_n : out std_logic;
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ddr3_cas_n : out std_logic;
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ddr3_we_n : out std_logic;
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ddr3_reset_n : out std_logic;
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ddr3_ck_p : out std_logic_vector(0 downto 0);
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ddr3_ck_n : out std_logic_vector(0 downto 0);
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ddr3_cke : out std_logic_vector(0 downto 0);
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ddr3_dm : out std_logic_vector(1 downto 0);
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ddr3_odt : out std_logic_vector(0 downto 0);
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-- ez-usb
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fd : inout std_logic_vector(15 downto 0);
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SLWR : out std_logic;
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SLRD : out std_logic;
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SLOE : out std_logic;
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FIFOADDR0 : out std_logic;
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FIFOADDR1 : out std_logic;
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PKTEND : out std_logic;
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FLAGA : in std_logic;
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FLAGB : in std_logic
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);
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end memfifo;
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architecture RTL of memfifo is
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component dram_fifo
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generic (
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-- fifo parameters, see "7 Series Memory Resources" user guide (ug743)
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ALMOST_EMPTY_OFFSET1 : INTEGER := 16;
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ALMOST_EMPTY_OFFSET2 : INTEGER := 16;
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ALMOST_FULL_OFFSET1 : INTEGER := 16;
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ALMOST_FULL_OFFSET2 : INTEGER := 16;
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FIRST_WORD_FALL_THROUGH : String := "TRUE";
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-- clock dividers for PLL outputs not used for memory interface, VCO frequency is 1200 MHz
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CLKOUT2_DIVIDE : INTEGER := 1;
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CLKOUT3_DIVIDE : INTEGER := 1;
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CLKOUT4_DIVIDE : INTEGER := 1;
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CLKOUT5_DIVIDE : INTEGER := 1;
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CLKOUT2_PHASE : INTEGER := 0;
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CLKOUT3_PHASE : INTEGER := 0;
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CLKOUT4_PHASE : INTEGER := 0;
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CLKOUT5_PHASE : INTEGER := 0
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);
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port (
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fxclk_in : in std_logic; -- 48 MHz input clock pin
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reset : in std_logic; -- reset in
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reset_out : out std_logic; -- reset output
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-- PLL clock outputs not used for memory interface
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clkout2 : out std_logic;
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clkout3 : out std_logic;
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clkout4 : out std_logic;
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clkout5 : out std_logic;
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-- ddr3 pins
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ddr3_dq : inout std_logic_vector(15 downto 0);
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ddr3_dqs_n : inout std_logic_vector(1 downto 0);
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ddr3_dqs_p : inout std_logic_vector(1 downto 0);
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ddr3_addr : out std_logic_vector(13 downto 0);
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ddr3_ba : out std_logic_vector(2 downto 0);
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ddr3_ras_n : out std_logic;
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ddr3_cas_n : out std_logic;
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ddr3_we_n : out std_logic;
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ddr3_reset_n : out std_logic;
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ddr3_ck_p : out std_logic_vector(0 downto 0);
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ddr3_ck_n : out std_logic_vector(0 downto 0);
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ddr3_cke : out std_logic_vector(0 downto 0);
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ddr3_dm : out std_logic_vector(1 downto 0);
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ddr3_odt : out std_logic_vector(0 downto 0);
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-- input fifo interface, see "7 Series Memory Resources" user guide (ug743)
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DI : in std_logic_vector(127 downto 0);
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FULL : out std_logic;
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ALMOSTFULL1 : out std_logic;
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ALMOSTFULL2 : out std_logic;
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WRERR : out std_logic;
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WRCLK : in std_logic;
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WREN : in std_logic;
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-- output fifo interface, see "7 Series Memory Resources" user guide (ug743)
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DO : out std_logic_vector(127 downto 0);
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EMPTY : out std_logic;
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ALMOSTEMPTY1 : out std_logic;
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ALMOSTEMPTY2 : out std_logic;
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RDERR : out std_logic;
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RDCLK : in std_logic;
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RDEN : in std_logic;
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-- free memory
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mem_free_out : out std_logic_vector(24 downto 0);
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-- for debugging
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status : out std_logic_vector(9 downto 0)
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);
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end component;
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component ezusb_io
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generic (
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OUTEP : INTEGER := 2; -- EP for FPGA -> EZ-USB transfers
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INEP : INTEGER := 6 -- EP for EZ-USB -> FPGA transfers
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);
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port (
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ifclk : out std_logic;
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reset : in std_logic; -- asynchronous reset input
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reset_out : out std_logic; -- synchronous reset output
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-- pins
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ifclk_in : in std_logic;
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fd : inout std_logic_vector(15 downto 0);
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SLWR : out std_logic;
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PKTEND : out std_logic;
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SLRD : out std_logic;
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SLOE : out std_logic;
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FIFOADDR : out std_logic_vector(1 downto 0);
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EMPTY_FLAG : in std_logic;
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FULL_FLAG : in std_logic;
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-- signals for FPGA -> EZ-USB transfer
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DI : in std_logic_vector(15 downto 0); -- data written to EZ-USB
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DI_valid : in std_logic; -- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
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DI_ready : out std_logic; -- 1 if new data are accepted
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DI_enable : in std_logic; -- setting to 0 disables FPGA -> EZ-USB transfers
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pktend_timeout : in std_logic_vector(15 downto 0); -- timeout in multiples of 65536 clocks before a short packet committed
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-- setting to 0 disables this feature
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-- signals for EZ-USB -> FPGA transfer
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DO : out std_logic_vector(15 downto 0); -- data read from EZ-USB
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DO_valid : out std_logic; -- 1 indicated valid data
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DO_ready : in std_logic; -- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
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-- set to 0 to disable data reads
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-- debug output
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status : out std_logic_vector(3 downto 0)
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);
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end component;
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signal reset2 : std_logic;
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signal reset_mem : std_logic;
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signal reset_usb : std_logic;
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signal ifclk : std_logic;
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signal reset_ifclk : std_logic;
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signal mem_free : std_logic_vector(24 downto 0);
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signal status : std_logic_vector(9 downto 0);
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signal if_status : std_logic_vector(3 downto 0);
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signal mode_buf : std_logic_vector(1 downto 0);
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-- input fifo
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signal DI : std_logic_vector(127 downto 0);
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signal FULL : std_logic;
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signal WRERR : std_logic;
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signal USB_DO_valid : std_logic;
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signal DO_ready : std_logic;
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signal WREN : std_logic;
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signal wrerr_buf : std_logic;
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signal USB_DO : std_logic_vector(15 downto 0);
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signal in_data : std_logic_vector(127 downto 0);
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signal wr_cnt : std_logic_vector(3 downto 0);
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signal test_cnt : std_logic_vector(6 downto 0);
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signal test_cs : std_logic_vector(13 downto 0);
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signal in_valid : std_logic;
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signal test_sync : std_logic;
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signal clk_div : std_logic_vector(1 downto 0);
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-- output fifo
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signal DO : std_logic_vector(127 downto 0);
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signal EMPTY : std_logic;
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signal RDERR : std_logic;
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signal USB_DI_ready : std_logic;
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signal RDEN : std_logic;
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signal rderr_buf : std_logic;
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signal USB_DI_valid : std_logic;
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signal rd_buf : std_logic_vector(127 downto 0);
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signal rd_cnt : std_logic_vector(2 downto 0);
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begin
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dram_fifo_inst : dram_fifo
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generic map (
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FIRST_WORD_FALL_THROUGH => "TRUE", -- Sets the FIFO FWFT to FALSE, TRUE
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ALMOST_EMPTY_OFFSET2 => 8
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)
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port map (
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fxclk_in => fxclk_in, -- 48 MHz input clock pin
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reset => reset2,
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reset_out => reset_mem, -- reset output
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clkout2 => open, -- PLL clock outputs not used for memory interface
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clkout3 => open,
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clkout4 => open,
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clkout5 => open,
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-- Memory interface ports
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ddr3_dq => ddr3_dq,
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ddr3_dqs_n => ddr3_dqs_n,
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ddr3_dqs_p => ddr3_dqs_p,
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ddr3_addr => ddr3_addr,
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ddr3_ba => ddr3_ba,
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ddr3_ras_n => ddr3_ras_n,
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ddr3_cas_n => ddr3_cas_n,
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ddr3_we_n => ddr3_we_n,
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ddr3_reset_n => ddr3_reset_n,
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ddr3_ck_p => ddr3_ck_p,
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ddr3_ck_n => ddr3_ck_n,
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ddr3_cke => ddr3_cke,
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ddr3_dm => ddr3_dm,
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ddr3_odt => ddr3_odt,
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-- input fifo interface, see "7 Series Memory Resources" user guide (ug743)
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DI => DI,
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FULL => FULL, -- 1-bit output: Full flag
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ALMOSTFULL1 => open, -- 1-bit output: Almost full flag
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ALMOSTFULL2 => open, -- 1-bit output: Almost full flag
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WRERR => WRERR, -- 1-bit output: Write error
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WREN => WREN, -- 1-bit input: Write enable
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WRCLK => ifclk, -- 1-bit input: Rising edge write clock.
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-- output fifo interface, see "7 Series Memory Resources" user guide (ug743)
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DO => DO,
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EMPTY => EMPTY, -- 1-bit output: Empty flag
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ALMOSTEMPTY1 => open, -- 1-bit output: Almost empty flag
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ALMOSTEMPTY2 => open, -- 1-bit output: Almost empty flag
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RDERR => RDERR, -- 1-bit output: Read error
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RDCLK => ifclk, -- 1-bit input: Read clock
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RDEN => RDEN, -- 1-bit input: Read enable
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-- free memory
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mem_free_out => mem_free,
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-- for debugging
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status => status
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);
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ezusb_io_inst : ezusb_io
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generic map (
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OUTEP => 2, -- EP for FPGA -> EZ-USB transfers
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INEP => 6 -- EP for EZ-USB -> FPGA transfers
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)
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port map (
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ifclk => ifclk,
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reset => reset, -- asynchronous reset input
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reset_out => reset_usb, -- synchronous reset output
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-- pins
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ifclk_in => ifclk_in,
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fd => fd,
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SLWR => SLWR,
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SLRD => SLRD,
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SLOE => SLOE,
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PKTEND => PKTEND,
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FIFOADDR(0)=> FIFOADDR0,
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FIFOADDR(1)=> FIFOADDR1,
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EMPTY_FLAG => FLAGA,
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FULL_FLAG => FLAGB,
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-- signals for FPGA -> EZ-USB transfer
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DI => rd_buf(15 downto 0), -- data written to EZ-USB
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DI_valid => USB_DI_valid, -- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
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DI_ready => USB_DI_ready, -- 1 if new data are accepted
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DI_enable => '1', -- setting to 0 disables FPGA -> EZ-USB transfers
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pktend_timeout => conv_std_logic_vector(90,16), -- timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed
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-- setting to 0 disables this feature
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-- signals for EZ-USB -> FPGA transfer
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DO => USB_DO, -- data read from EZ-USB
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DO_valid => USB_DO_valid, -- 1 indicated valid data
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DO_ready => DO_ready, -- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
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-- debug output
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status => if_status
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);
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reset2 <= reset or reset_usb;
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DO_ready <= '1' when ( (mode_buf="00") and (reset_ifclk='0') and (FULL='0') ) else '0';
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-- debug board LEDs
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led1 <= status when (SW10='1') else (EMPTY & FULL & wrerr_buf & rderr_buf & if_status & FLAGB & FLAGA);
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led2(0) <= '1' when mem_free /= ( '1' & conv_std_logic_vector(0,24) ) else '0';
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led2(1) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(30,5) else '0';
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led2(2) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(29,5) else '0';
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led2(3) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(27,5) else '0';
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led2(4) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(25,5) else '0';
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led2(5) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(24,5) else '0';
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led2(6) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(22,5) else '0';
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led2(7) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(20,5) else '0';
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led2(8) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(19,5) else '0';
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led2(9) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(17,5) else '0';
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led2(10) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(15,5) else '0';
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led2(11) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(13,5) else '0';
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led2(12) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(12,5) else '0';
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led2(13) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(10,5) else '0';
|
306 |
|
|
led2(14) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(8,5) else '0';
|
307 |
|
|
led2(15) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(7,5) else '0';
|
308 |
|
|
led2(16) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(5,5) else '0';
|
309 |
|
|
led2(17) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(3,5) else '0';
|
310 |
|
|
led2(18) <= '1' when mem_free(23 downto 19) < conv_std_logic_vector(2,5) else '0';
|
311 |
|
|
led2(19) <= '1' when mem_free = conv_std_logic_vector(0,25) else '0';
|
312 |
|
|
|
313 |
|
|
test_sync <= '1' when ( (wr_cnt="1110") or (wr_cnt(0)='1') ) else '0';
|
314 |
|
|
|
315 |
|
|
dpifclk: process
|
316 |
|
|
begin
|
317 |
|
|
wait until ( ifclk'EVENT and (ifclk = '1') );
|
318 |
|
|
|
319 |
|
|
-- reset
|
320 |
|
|
reset_ifclk <= (reset or reset_usb) or reset_mem;
|
321 |
|
|
if ( reset_ifclk = '1' ) then
|
322 |
|
|
rderr_buf <= '0';
|
323 |
|
|
wrerr_buf <= '0';
|
324 |
|
|
else
|
325 |
|
|
rderr_buf <= rderr_buf or RDERR;
|
326 |
|
|
wrerr_buf <= wrerr_buf or WRERR;
|
327 |
|
|
end if;
|
328 |
|
|
|
329 |
|
|
-- FPGA -> EZ-USB FIFO
|
330 |
|
|
if ( reset_ifclk = '1' ) then
|
331 |
|
|
rd_cnt <= (others => '0');
|
332 |
|
|
USB_DI_valid <= '0';
|
333 |
|
|
else
|
334 |
|
|
if ( USB_DI_ready = '1' ) then
|
335 |
|
|
USB_DI_valid <= not EMPTY;
|
336 |
|
|
if ( EMPTY = '0' ) then
|
337 |
|
|
if ( rd_cnt = "000" ) then
|
338 |
|
|
rd_buf <= DO;
|
339 |
|
|
else
|
340 |
|
|
rd_buf(111 downto 0) <= rd_buf(127 downto 16);
|
341 |
|
|
end if;
|
342 |
|
|
rd_cnt <= rd_cnt + 1;
|
343 |
|
|
end if;
|
344 |
|
|
end if;
|
345 |
|
|
end if;
|
346 |
|
|
|
347 |
|
|
if ( (reset_ifclk = '0') and (USB_DI_ready = '1') and (EMPTY = '0') and (rd_cnt = "000")) then
|
348 |
|
|
RDEN <= '1';
|
349 |
|
|
else
|
350 |
|
|
RDEN <= '0';
|
351 |
|
|
end if;
|
352 |
|
|
|
353 |
|
|
-- data source
|
354 |
|
|
if ( reset_ifclk = '1' ) then
|
355 |
|
|
in_data <= (others => '0');
|
356 |
|
|
in_valid <= '0';
|
357 |
|
|
wr_cnt <= (others => '0');
|
358 |
|
|
test_cnt <=(others => '0');
|
359 |
|
|
test_cs <= conv_std_logic_vector(47,14);
|
360 |
|
|
WREN <= '0';
|
361 |
|
|
clk_div <= "11";
|
362 |
|
|
else
|
363 |
|
|
if ( FULL = '0' ) then
|
364 |
|
|
if ( in_valid = '1' ) then
|
365 |
|
|
DI <= in_data;
|
366 |
|
|
end if;
|
367 |
|
|
if ( mode_buf = "00" ) then
|
368 |
|
|
if ( USB_DO_valid = '1' ) then
|
369 |
|
|
in_data <= USB_DO & in_data(127 downto 16);
|
370 |
|
|
if ( wr_cnt(2 downto 0) = "111") then
|
371 |
|
|
in_valid <= '1';
|
372 |
|
|
else
|
373 |
|
|
in_valid <= '0';
|
374 |
|
|
end if;
|
375 |
|
|
wr_cnt <= wr_cnt + 1;
|
376 |
|
|
else
|
377 |
|
|
in_valid <= '0';
|
378 |
|
|
end if;
|
379 |
|
|
else
|
380 |
|
|
if ( clk_div = "00" ) then
|
381 |
|
|
if ( ( wr_cnt = "1111" ) ) then
|
382 |
|
|
test_cs <= conv_std_logic_vector(47,14);
|
383 |
|
|
in_data(126 downto 120) <= test_cs(6 downto 0) xor test_cs(13 downto 7);
|
384 |
|
|
in_valid <= '1';
|
385 |
|
|
else
|
386 |
|
|
test_cnt <= test_cnt + conv_std_logic_vector(111,7);
|
387 |
|
|
test_cs <= test_cs + ( test_sync & test_cnt );
|
388 |
|
|
in_data(126 downto 120 ) <= test_cnt;
|
389 |
|
|
in_valid <= '0';
|
390 |
|
|
end if;
|
391 |
|
|
in_data(127 ) <= test_sync;
|
392 |
|
|
in_data(119 downto 0 ) <= in_data(127 downto 8 );
|
393 |
|
|
wr_cnt <= wr_cnt + 1;
|
394 |
|
|
else
|
395 |
|
|
in_valid <= '0';
|
396 |
|
|
end if;
|
397 |
|
|
end if;
|
398 |
|
|
if ( (mode_buf = "01") or ( (mode_buf = "11") and (SW8='1') ) ) then
|
399 |
|
|
clk_div <= "00";
|
400 |
|
|
else
|
401 |
|
|
clk_div <= clk_div + 1;
|
402 |
|
|
end if;
|
403 |
|
|
end if;
|
404 |
|
|
end if;
|
405 |
|
|
if ( (reset_ifclk ='0') and (in_valid = '1') and (FULL='0') ) then
|
406 |
|
|
WREN <='1';
|
407 |
|
|
else
|
408 |
|
|
WREN <='0';
|
409 |
|
|
end if;
|
410 |
|
|
mode_buf <= mode;
|
411 |
|
|
end process dpifclk;
|
412 |
|
|
|
413 |
|
|
end RTL;
|
414 |
|
|
|