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ZTEX |
/*%
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ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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This Source Code Form is subject to the terms of the Mozilla Public
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License, v. 2.0. If a copy of the MPL was not distributed with this file,
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You can obtain one at http://mozilla.org/MPL/2.0/.
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Alternatively, the contents of this file may be used under the terms
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of the GNU General Public License Version 3, as described below:
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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Template for default firmware.
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*/
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#undef GPIO_SIMPLE_BITMAP0
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#define GPIO_SIMPLE_BITMAP0 ( ( 1 << GPIO_GPIO0 ) | ( 1 << GPIO_GPIO1 ) | ( 1 << GPIO_RESET ) | ( 1 << GPIO_CLK ) | ( 1 << GPIO_DATA ) | ( 1 << GPIO_STOP ) )
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#undef GPIO_SIMPLE_BITMAP1
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#define GPIO_SIMPLE_BITMAP1 ( ( 1 << (GPIO_GPIO2-32) ) | ( 1 << (GPIO_GPIO3-32) ) )
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CyU3PDmaChannel dma_out_handle, dma_in_handle, dma_fpga_conf_handle;
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CyBool_t communication_started = CyFalse;
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// undocumented: PIB_SOCKET_0 .. SOCKET_3 must be connected to GPIF threads 0..3, but other sockets can be connected to any thread
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#define EZUSB_IO_IN_SOCKET CY_U3P_PIB_SOCKET_1
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#define EZUSB_IO_OUT_SOCKET CY_U3P_PIB_SOCKET_0
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#define EZUSB_IO_FPGA_CONF_SOCKET CY_U3P_PIB_SOCKET_5
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/*
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re-using input channel for FPGA configuration fails in super speed mode due to a bug in Cypress SDK, see
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http://www.cypress.com/forum/usb-30-super-speed/dma-channel-gpif-reset-problem-super-speed-mode
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#define ZTEX_FPGA_CONF_FAST_EP OUT_ENDPOINT
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#define ZTEX_FPGA_CONF_FAST_IFACE 0
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#define ZTEX_FPGA_CONF_FAST_SOCKET EZUSB_IO_IN_SOCKET
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*/
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// workaround: create a own channel for FPGA configuration
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#ifndef ZTEX_FPGA_CONF_FAST_IFACE
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#define ZTEX_FPGA_CONF_FAST_IFACE 1
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#define ZTEX_FPGA_CONF_FAST_SOCKET CY_U3P_PIB_SOCKET_5
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#endif
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/* endpount / dma macros
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OUT_ENDPOINT : host --> EZUSB --> FPGA
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* interface 0
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* bulk size: 16*1024
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* buffer size: 16K
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* buffer count: 4
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* PIB socket: 1
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IN_ENDPOINT : FPGA --> EZUSB --> host
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* interface 0
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* bulk size: 16*1024
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* buffer size: 16K
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* buffer count: 4
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* PIB socket: 0
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ZTEX_FPGA_CONF_FAST_EP : FPGA configuration
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* interface 1
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* bulk size: 1*1024
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* buffer size: 1K
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* buffer count: 2
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* PIB socket: 5
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*/
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#define EP_SETUP_DEFAULT \
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INTERFACE(0, \
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EP_BULK(OUT_ENDPOINT, OUT, 16, \
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DMA(dma_in_handle, CY_U3P_DMA_TYPE_AUTO, 16, 4, EZUSB_IO_IN_SOCKET, \
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CB(0,0) \
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) \
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) \
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EP_BULK(IN_ENDPOINT, IN, 16, \
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DMA(dma_out_handle, CY_U3P_DMA_TYPE_AUTO, 16, 4, EZUSB_IO_OUT_SOCKET, ) \
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) \
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)
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#undef EP_SETUP
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#ifdef ZTEX_FPGA_CONF_FAST_EP
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#define EP_SETUP EP_SETUP_DEFAULT \
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INTERFACE(1, \
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EP_BULK(ZTEX_FPGA_CONF_FAST_EP, OUT, 1, \
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DMA(dma_fpga_conf_handle, CY_U3P_DMA_TYPE_AUTO, 1, 2 , ZTEX_FPGA_CONF_FAST_SOCKET, \
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CB(0,0) \
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) \
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) \
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)
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#else
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#define EP_SETUP EP_SETUP_DEFAULT
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#endif
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#include "ztex-lsi.c"
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#include "ztex.c"
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#include "ztex-ezusb-io1.c"
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void run () {
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uint16_t snd_errors, rcv_errors;
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uint16_t last_snd_errors = 0;
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uint16_t last_rcv_errors = 0;
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ztex_log ( "Info: Starting default Firmware" );
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while (1) {
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snd_errors = ZTEX_USB3_SND_ERROR_COUNT;
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rcv_errors = ZTEX_USB3_RCV_ERROR_COUNT;
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if ( (snd_errors != last_snd_errors) || (rcv_errors != last_rcv_errors) ) {
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ZTEX_LOG("snd errors: %d, rcv errors: %d", snd_errors, rcv_errors);
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last_snd_errors = snd_errors;
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last_rcv_errors = rcv_errors;
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}
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/* if ( CyU3PDmaChannelIsValid(&dma_in_handle) ) {
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uint32_t p,c;
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CyU3PDmaState_t s;
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CyU3PDmaChannelGetStatus(&dma_in_handle, &s, &p,&c);
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ZTEX_LOG("Info: Input DMA status status=%d, prod=%d, cons=%d",s,p,c);
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} */
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CyU3PThreadSleep (500);
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}
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}
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void usb_start() {
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// start communication if cable is connected and FPGA is running
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if ( ZTEX_FPGA_CONFIGURED ) {
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ztex_log ( "Info: Starting communication" );
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communication_started = CyTrue;
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// start lsi, reset is active
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ztex_lsi_start();
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// load GPIF
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ztex_ezusb_io1_start( EZUSB_IO_IN_SOCKET, EZUSB_IO_OUT_SOCKET );
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// start transfers
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ZTEX_REC(CyU3PDmaChannelSetXfer (&dma_in_handle, 0));
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ZTEX_REC(CyU3PDmaChannelSetXfer (&dma_out_handle, 0));
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ztex_gpio_set(GPIO_RESET, CyFalse);
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ztex_gpio_set(ZTEX_GPIO_LED, CyTrue);
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}
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}
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void usb_stop() {
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/* if ( CyU3PDmaChannelIsValid(&dma_in_handle) ) {
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uint32_t p,c;
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CyU3PDmaState_t s;
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CyU3PDmaChannelGetStatus(&dma_in_handle, &s, &p,&c);
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ZTEX_LOG("Info: Input DMA status status=%d, prod=%d, cons=%d",s,p,c);
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} */
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if ( communication_started ) {
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ztex_log ( "Info: Stopping communication" );
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communication_started = CyFalse;
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ztex_ezusb_io1_stop();
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ztex_lsi_stop();
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ztex_gpio_set(ZTEX_GPIO_LED, CyFalse);
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}
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}
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/*
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* Main function
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*/
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int main (void)
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{
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ztex_pib_clock.clkDiv = 4; // normal setting: 104 MHz @ 26 MHz external clock
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// ztex_pib_clock.clkDiv = 6; // conservative setting: 69.33MHz @ 26 MHz external clock
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ztex_app_thread_run = run;
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ztex_usb_start = usb_start;
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ztex_usb_stop = usb_stop;
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ztex_interface_string[0] = "ZTEX Default Interface";
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ztex_interface_string[1] = "FPGA configuration interface";
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ztex_main(); // starts the OS and never returns
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return 0; // makes the compiler happy
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}
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