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ZTEX |
/*%
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ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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This Source Code Form is subject to the terms of the Mozilla Public
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License, v. 2.0. If a copy of the MPL was not distributed with this file,
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You can obtain one at http://mozilla.org/MPL/2.0/.
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Alternatively, the contents of this file may be used under the terms
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of the GNU General Public License Version 3, as described below:
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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Implements the low speed interface of default firmware.
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*/
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/*
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The following macros (containing GPIO numbers) must be defined:
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GPIO_RESET
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GPIO_GPIO0
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GPIO_GPIO1
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GPIO_GPIO2
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GPIO_GPIO3
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GPIO_CLK
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GPIO_DATA
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GPIO_STOP
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This macros (containing Endpoint numbers) may be defined:
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OUT_ENDPOINT
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IN_ENDPOINT
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*/
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#ifndef _ZTEX_LSI_
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#define _ZTEX_LSI_
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#endif // _ZTEX_LSI_
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#ifdef _ZTEX_INCLUDE_2_
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#ifndef _ZTEX_LSI_2_
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#define _ZTEX_LSI_2_
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#ifndef OUT_ENDPOINT
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#define OUT_ENDPOINT 255
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#endif
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#ifndef IN_NDPOINT
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#define IN_NDPOINT 255
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#endif
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#define LSI_VERSION 1
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#define LSI_SUB_VERSION 4
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CyBool_t next_clk;
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#define LSI_CLOCK { ztex_gpio_set(GPIO_CLK, next_clk); next_clk=!next_clk; }
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// VC 0x60
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// value != 0: reset signal is left active
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uint8_t vc_default_reset(uint16_t value, uint16_t index, uint16_t length ) {
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if ( length>0 ) {
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CyU3PUsbGetEP0Data (length, ztex_ep0buf, NULL); // there should be no data
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} else {
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CyU3PUsbAckSetup();
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}
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ztex_gpio_set(GPIO_RESET, CyTrue);
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if ( value ) return 0;
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CyU3PThreadSleep(1);
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ztex_gpio_set(GPIO_RESET, CyFalse);
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return 0;
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}
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// VR 0x61
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// index: mask
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// value: value
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uint8_t vr_default_gpio_ctl(uint16_t value, uint16_t index, uint16_t length ) {
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if (index & 1) ztex_gpio_set(GPIO_GPIO0, (value & 1) == 0);
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if (index & 2) ztex_gpio_set(GPIO_GPIO1, (value & 2) == 0);
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if (index & 4) ztex_gpio_set(GPIO_GPIO2, (value & 4) == 0);
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if (index & 8) ztex_gpio_set(GPIO_GPIO3, (value & 8) == 0);
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ztex_ep0buf[0] = ~(0xf0 | (ztex_gpio_get(GPIO_GPIO3)<<3) | (ztex_gpio_get(GPIO_GPIO2)<<2) | (ztex_gpio_get(GPIO_GPIO1)<<1) | ztex_gpio_get(GPIO_GPIO0) );
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ZTEX_REC_RET ( CyU3PUsbSendEP0Data( length, ztex_ep0buf ) );
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return 0;
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}
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// VC 0x62
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// data format is 4 byte data (little endian) + 1 byte address
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uint8_t vc_default_lsi_write(uint16_t value, uint16_t index, uint16_t length ) {
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ZTEX_REC_RET ( CyU3PUsbGetEP0Data (length, ztex_ep0buf, NULL) );
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LSI_CLOCK;
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for (int i=0; i+4<length; i+=5) {
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ztex_gpio_set(GPIO_STOP, CyFalse);
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for (int j=0; j<5; j++ ) {
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uint8_t b = ztex_ep0buf[i+j];
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for ( int k=0; k<8; k++ ) {
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ztex_gpio_set(GPIO_DATA, b & 1);
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LSI_CLOCK;
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b>>=1;
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}
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}
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ztex_gpio_set(GPIO_DATA, CyFalse);
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ztex_gpio_set(GPIO_STOP, CyTrue);
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LSI_CLOCK;
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}
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ztex_gpio_set(GPIO_STOP, CyFalse);
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return 0;
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}
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// VR 0x63
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// data format is 4 byte data (little endian)
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// FX3 and FPGA clock are asynchronous and there is no acknowledgment. For this reason
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// minimum recommended for the ZTEX LSI core is 20 MHz. For much slower clock this interface
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// may be to fast.
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uint8_t vr_default_lsi_read(uint16_t value, uint16_t index, uint16_t length ) {
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LSI_CLOCK;
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for (int i=0; i+3<length; i+=4) {
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ztex_gpio_set(GPIO_STOP, CyFalse);
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uint8_t b = index++;
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for (int k=0; k<8; k++) {
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ztex_gpio_set(GPIO_DATA, b & 1);
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LSI_CLOCK;
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b>>=1;
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}
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ztex_gpio_set(GPIO_DATA, CyTrue);
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ztex_gpio_set(GPIO_STOP, CyTrue);
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LSI_CLOCK;
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for (int j=0; j<64; j++ ) {} // give FPGA some extra time to load data
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for (int j=0; j<4; j++ ) {
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b=0;
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for (int k=0; k<8; k++) {
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b = ( b >> 1 ) | ( ztex_gpio_get(GPIO_DATA) << 7);
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LSI_CLOCK;
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}
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ztex_ep0buf[i+j] = b;
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}
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}
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ztex_gpio_set(GPIO_STOP, CyFalse);
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ZTEX_REC_RET ( CyU3PUsbSendEP0Data( length, ztex_ep0buf ) );
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return 0;
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}
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// VR 0x64
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uint8_t vr_default_info(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_ep0buf[0] = LSI_VERSION;
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ztex_ep0buf[1] = OUT_ENDPOINT; // OUT Endpoint
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ztex_ep0buf[2] = IN_ENDPOINT; // IN Endpoint
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ztex_ep0buf[3] = LSI_SUB_VERSION;
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ztex_ep0buf[4] = 0; // reserved for future use
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ztex_ep0buf[5] = 0; // reserved for future use
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ztex_ep0buf[6] = 0; // reserved for future use
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ztex_ep0buf[7] = 0; // reserved for future use
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if (length>8) length = 8;
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ZTEX_REC_RET( CyU3PUsbSendEP0Data( length, ztex_ep0buf ) );
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return 0;
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}
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void ztex_lsi_init () {
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ztex_register_vendor_cmd(0x60, vc_default_reset);
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ztex_register_vendor_req(0x61, vr_default_gpio_ctl);
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ztex_register_vendor_cmd(0x62, vc_default_lsi_write);
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ztex_register_vendor_req(0x63, vr_default_lsi_read);
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ztex_register_vendor_req(0x64, vr_default_info);
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}
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// reset signal is left active
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void ztex_lsi_start() {
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ztex_gpio_set_output(GPIO_RESET, CyTrue);
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ztex_gpio_set_open_drain(GPIO_GPIO0, CyTrue);
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ztex_gpio_set_open_drain(GPIO_GPIO1, CyTrue);
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ztex_gpio_set_open_drain(GPIO_GPIO2, CyTrue);
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ztex_gpio_set_open_drain(GPIO_GPIO3, CyTrue);
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ztex_gpio_set_output(GPIO_CLK, CyFalse); next_clk=CyTrue;
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ztex_gpio_set_open_drain(GPIO_DATA, CyTrue);
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ztex_gpio_set_output(GPIO_STOP, CyFalse);
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}
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void ztex_lsi_stop() {
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ztex_gpio_set_input(GPIO_RESET);
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ztex_gpio_set_input(GPIO_GPIO0);
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ztex_gpio_set_input(GPIO_GPIO1);
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ztex_gpio_set_input(GPIO_GPIO2);
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ztex_gpio_set_input(GPIO_GPIO3);
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ztex_gpio_set_input(GPIO_CLK);
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ztex_gpio_set_input(GPIO_DATA);
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ztex_gpio_set_input(GPIO_STOP);
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}
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#endif // _ZTEX_LSI_2_
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#endif // _ZTEX_INCLUDE_2_
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