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ZTEX |
/*%
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ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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This Source Code Form is subject to the terms of the Mozilla Public
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License, v. 2.0. If a copy of the MPL was not distributed with this file,
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You can obtain one at http://mozilla.org/MPL/2.0/.
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Alternatively, the contents of this file may be used under the terms
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of the GNU General Public License Version 3, as described below:
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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Board specific functions for ZTEX-USB FPGA Module 2.18
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*/
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#ifndef _ZTEX_CONF_UFM_2_18_C1_
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#define _ZTEX_CONF_UFM_2_18_C1_
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#include "cyu3pib.h"
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// product ID's for ZTEX USB-FPGA Module 2.18 are 10.42.*.*
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#undef ZTEX_PRODUCT_ID_0
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#define ZTEX_PRODUCT_ID_0 (10)
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#undef ZTEX_PRODUCT_ID_1
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#define ZTEX_PRODUCT_ID_1 (42)
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/*
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This macro defines the Product string. Limited to 31 characters.
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*/
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#undef ZTEX_PRODUCT_STRING
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#define ZTEX_PRODUCT_STRING "ZTEX USB-FPGA Module 2.18"
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#define ENABLE_SPORT0
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// GPIO's
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#define ZTEX_GPIO_MODE0 50
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#define ZTEX_GPIO_MODE1 45
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#define ZTEX_GPIO_LED 52
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#define ZTEX_GPIO_FPGA_RESET 51
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#define ZTEX_GPIO_FPGA_INIT_B 37
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#define ZTEX_GPIO_FPGA_RDWR_B 38
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#define ZTEX_GPIO_FPGA_CSI_B 39
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#define ZTEX_GPIO_FPGA_DONE 40
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#define ZTEX_GPIO_OTG_EN 57
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#undef ZTEX_GPIO_SIMPLE_BITMAP0
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#undef ZTEX_GPIO_SIMPLE_BITMAP1
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#define ZTEX_GPIO_SIMPLE_BITMAP0 0
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#define ZTEX_GPIO_SIMPLE_BITMAP1 ( 1 << (ZTEX_GPIO_MODE0-32) | 1 << (ZTEX_GPIO_MODE1-32) | 1 << (ZTEX_GPIO_LED-32) \
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| 1 << (ZTEX_GPIO_FPGA_RESET-32) | 1 << (ZTEX_GPIO_FPGA_DONE-32) | 1 << (ZTEX_GPIO_FPGA_INIT_B-32) | 1 << (ZTEX_GPIO_FPGA_RDWR_B-32) | 1 << (ZTEX_GPIO_FPGA_CSI_B-32) \
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| 1 << (ZTEX_GPIO_OTG_EN-32) \
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)
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#define ZTEX_FPGA_CONFIGURED ( ztex_gpio_get(ZTEX_GPIO_FPGA_DONE) )
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#define _ZTEX_BOARD_
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#define _ZTEX_FPGA_
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void ztex_disable_flash();
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#endif // _ZTEX_CONF_UFM_2_18_C1_
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#ifdef _ZTEX_INCLUDE_2_
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#ifndef _ZTEX_CONF_UFM_2_18_C2_
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#define _ZTEX_CONF_UFM_2_18_C2_
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#include "ztex-fpgaconf1.c"
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/* USB system is restarted after FPGA reset and after successful FPGA configuration.
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(de)initialization code should be written to ztex_usb_stop() and ztex_usb_start().
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See ztex-default.c (Template for default firmware) for recommended usage.
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*/
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uint8_t ztex_fpga_cs = 0; // check sum
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uint32_t ztex_fpga_bytes = 0; // transferred bytes
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uint8_t ztex_fpga_init_b = 0; // init b
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uint8_t ztex_fpga_config_started = 0;
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void ztex_usb_start_main();
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void ztex_usb_stop_main();
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/* *********************************************************************
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***** ztex_cpld_set *************************************************
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********************************************************************* */
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void ztex_cpld_set( CyBool_t enable_flash, CyBool_t reset_fpga) {
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ztex_gpio_set(ZTEX_GPIO_MODE0, !enable_flash);
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ztex_gpio_set(ZTEX_GPIO_FPGA_RESET, !reset_fpga);
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ztex_gpio_set(ZTEX_GPIO_MODE1, CyFalse);
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if ( reset_fpga ) return;
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ztex_gpio_set(ZTEX_GPIO_MODE1, CyTrue);
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}
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/* *********************************************************************
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***** ztex_disable_flash ********************************************
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********************************************************************* */
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// disables flash after soft reset
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void ztex_disable_flash() {
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ztex_cpld_set(CyFalse, CyFalse);
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}
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/* *********************************************************************
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***** ztex_enable_flash *********************************************
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********************************************************************* */
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// enables flash after soft reset
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void ztex_enable_flash() {
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ztex_cpld_set(CyTrue, CyFalse);
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}
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/* *********************************************************************
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***** ztex_spi_FX3_flash ********************************************
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********************************************************************* */
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// SPI Master: FX3, slave: Flash
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void ztex_spi_FX3_flash() {
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ztex_cpld_set(CyTrue, CyFalse);
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}
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/* *********************************************************************
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***** ztex_spi_FX3_FPGA *********************************************
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********************************************************************* */
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// SPI Master: FX3, slave: FPGA
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void ztex_spi_FX3_FPGA() {
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ztex_gpio_set(ZTEX_GPIO_MODE0, CyFalse);
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ztex_gpio_set(ZTEX_GPIO_MODE0, CyTrue);
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}
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/* *********************************************************************
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***** ztex_spi_FPGA_Flash *******************************************
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********************************************************************* */
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// SPI Master: FPGA, slave: Flash
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void ztex_spi_FPGA_Flash() {
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ztex_gpio_set(ZTEX_GPIO_MODE0, CyTrue);
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ztex_gpio_set(ZTEX_GPIO_MODE0, CyFalse);
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}
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/* *********************************************************************
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***** ztex_fpga_configured ******************************************
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********************************************************************* */
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CyBool_t ztex_fpga_configured() {
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return ztex_gpio_get(ZTEX_GPIO_FPGA_DONE);
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}
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/* *********************************************************************
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***** ztex_fpga_reset ***********************************************
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********************************************************************* */
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void ztex_fpga_reset() {
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if ( ZTEX_FPGA_CONFIGURED || ztex_fpga_config_started ) { // restart USB and reset pib clock
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ZTEX_LOG("Info: Preparing USB for FPGA configuration");
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ztex_usb_stop_main();
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ztex_pib_clock2 = &ztex_fpgaconf1_pib_clock;
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ztex_cpld_set(CyTrue, CyTrue);
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ztex_usb_start_main();
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ztex_fpga_config_started = 0;
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}
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ztex_cpld_set(CyTrue, CyTrue);
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ztex_gpio_set_output(ZTEX_GPIO_FPGA_RDWR_B, CyFalse);
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ztex_gpio_set_output(ZTEX_GPIO_FPGA_CSI_B, CyFalse);
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CyU3PThreadSleep (20);
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ztex_cpld_set(CyTrue, CyFalse);
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}
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/* *********************************************************************
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***** ztex_fpga_config_start ****************************************
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********************************************************************* */
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// socket should be 0 for configuration from CPU
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void ztex_fpga_config_start(CyU3PDmaSocketId_t socket) {
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uint8_t mode = socket > 0 ? 1 : 2;
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if ( ztex_fpga_config_started == mode ) return; // already started in correct mode
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ztex_fpga_reset();
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ztex_fpga_config_started = mode;
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ztex_fpgaconf1_start(socket); // start gpif
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if ( socket > 0) { // start auto transfers
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CyU3PDmaChannel* dma_p = CyU3PDmaChannelGetHandle(socket);
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if ( dma_p != NULL ) ZTEX_REC(CyU3PDmaChannelSetXfer (dma_p, 0));
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}
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uint8_t i = 0;
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while ( (!ztex_gpio_get(ZTEX_GPIO_FPGA_INIT_B)) && i<255 ) {
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CyU3PThreadSleep (1);
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i++;
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}
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ztex_fpga_init_b = ztex_gpio_get(ZTEX_GPIO_FPGA_INIT_B) ? 200 : 100;
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ztex_fpga_cs = 0;
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ztex_fpga_bytes = 0;
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}
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/* *********************************************************************
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***** ztex_fpga_config_done *****************************************
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********************************************************************* */
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void ztex_fpga_config_done(CyBool_t fromFlash) {
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ztex_fpga_init_b += ztex_gpio_get(ZTEX_GPIO_FPGA_INIT_B) ? 22 : 11;
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if ( ztex_fpga_config_started == 2) ztex_fpgaconf1_send(ztex_ep0buf,16); // some extra clock's
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ztex_fpgaconf1_stop(); // stop gpif
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ztex_fpga_config_started = 0;
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if ( fromFlash ) ZTEX_REC( CyU3PPibDeInit() );
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if ( ZTEX_FPGA_CONFIGURED ) {
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ztex_gpio_set_input(ZTEX_GPIO_FPGA_RDWR_B);
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ztex_gpio_set_input(ZTEX_GPIO_FPGA_CSI_B);
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ZTEX_LOG("Info: Preparing USB for application");
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if ( ! fromFlash ) ztex_usb_stop_main(); // restart USB and reset PIB clock
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ztex_pib_clock2 = &ztex_pib_clock;
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if ( ! fromFlash ) ztex_usb_start_main();
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}
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}
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/* *********************************************************************
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***** vr_fpga_info **************************************************
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********************************************************************* */
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// VR 0x30
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uint8_t vr_fpga_info(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_ep0buf[0] = ZTEX_FPGA_CONFIGURED ? 0 : 1;
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ztex_ep0buf[1] = ztex_fpga_cs;
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ztex_ep0buf[2] = ztex_fpga_bytes;
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ztex_ep0buf[3] = ztex_fpga_bytes >> 8;
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ztex_ep0buf[4] = ztex_fpga_bytes >> 16;
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ztex_ep0buf[5] = ztex_fpga_bytes >> 24;
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ztex_ep0buf[6] = ztex_fpga_init_b;
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ztex_ep0buf[7] = 0; // flash configuration result
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ztex_ep0buf[8] = 0; // bit order = not swapped
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ZTEX_REC_RET( CyU3PUsbSendEP0Data( 9, ztex_ep0buf ) );
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return 0;
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}
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/* *********************************************************************
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***** vc_fpga_reset *************************************************
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********************************************************************* */
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// VC 0x31
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uint8_t vc_fpga_reset(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_fpga_reset();
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CyU3PUsbAckSetup();
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return 0;
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}
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/* *********************************************************************
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***** vc_fpga_send **************************************************
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********************************************************************* */
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// VC 0x32
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uint8_t vc_fpga_send(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_fpga_config_start(0);
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if ( length > 0 ) {
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ZTEX_REC_RET ( CyU3PUsbGetEP0Data (length, ztex_ep0buf, NULL) );
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for (uint16_t i = 0; i<length; i++)
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ztex_fpga_cs += ztex_ep0buf[i];
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ztex_fpga_bytes += length;
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ztex_fpgaconf1_send(ztex_ep0buf,length);
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}
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else {
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CyU3PUsbAckSetup();
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}
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if ( length == 0 || ((length & 63) != 0) ) ztex_fpga_config_done(CyFalse);
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return 0;
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}
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#ifdef ZTEX_FPGA_CONF_FAST_EP
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// ZTEX_FPGA_CONF_FAST_IFACE and ZTEX_FPGA_CONF_FAST_SOCKET must be defined too
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/* *********************************************************************
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***** vc_fpga_fast_info *********************************************
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********************************************************************* */
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// VR 0x33
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uint8_t vr_fpga_fast_info(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_ep0buf[0] = ZTEX_FPGA_CONF_FAST_EP;
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ztex_ep0buf[1] = ZTEX_FPGA_CONF_FAST_IFACE;
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ZTEX_REC_RET( CyU3PUsbSendEP0Data( 2, ztex_ep0buf ) );
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return 0;
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}
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/* *********************************************************************
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***** vc_fpga_fast_start ********************************************
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********************************************************************* */
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// VR 0x34
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uint8_t vc_fpga_fast_start(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_fpga_config_start(ZTEX_FPGA_CONF_FAST_SOCKET);
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CyU3PUsbAckSetup();
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return 0;
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}
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/* *********************************************************************
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***** vc_fpga_fast_finish *******************************************
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********************************************************************* */
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// VR 0x35
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uint8_t vc_fpga_fast_finish(uint16_t value, uint16_t index, uint16_t length ) {
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ztex_fpga_config_done(CyFalse);
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CyU3PUsbAckSetup();
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return 0;
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}
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#endif
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/* *********************************************************************
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***** ztex_board_init ***********************************************
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********************************************************************* */
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void ztex_board_init() {
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ztex_log ( "Info: Initializing USB-FPGA Module 2.18" );
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ztex_disable_flash_boot = ztex_disable_flash;
|
330 |
|
|
ztex_fpga_config_started = 0;
|
331 |
|
|
|
332 |
|
|
ztex_gpio_set_output(ZTEX_GPIO_LED, CyFalse);
|
333 |
|
|
ztex_gpio_set_output(ZTEX_GPIO_MODE0, CyTrue);
|
334 |
|
|
ztex_gpio_set_output(ZTEX_GPIO_MODE1, CyTrue);
|
335 |
|
|
|
336 |
|
|
ztex_gpio_set_input(ZTEX_GPIO_FPGA_DONE);
|
337 |
|
|
ztex_gpio_set_output(ZTEX_GPIO_FPGA_RESET, CyTrue);
|
338 |
|
|
ztex_gpio_set_input(ZTEX_GPIO_FPGA_INIT_B); CyU3PGpioSetIoMode(ZTEX_GPIO_FPGA_INIT_B, CY_U3P_GPIO_IO_MODE_WPU);
|
339 |
|
|
|
340 |
|
|
ztex_gpio_set_output(ZTEX_GPIO_OTG_EN, CyFalse);
|
341 |
|
|
|
342 |
|
|
ztex_enable_flash();
|
343 |
|
|
|
344 |
|
|
ztex_register_vendor_req(0x30, vr_fpga_info);
|
345 |
|
|
ztex_register_vendor_cmd(0x31, vc_fpga_reset);
|
346 |
|
|
ztex_register_vendor_cmd(0x32, vc_fpga_send);
|
347 |
|
|
#ifdef ZTEX_FPGA_CONF_FAST_EP
|
348 |
|
|
ztex_register_vendor_req(0x33, vr_fpga_fast_info);
|
349 |
|
|
ztex_register_vendor_cmd(0x34, vc_fpga_fast_start);
|
350 |
|
|
ztex_register_vendor_cmd(0x35, vc_fpga_fast_finish);
|
351 |
|
|
#endif
|
352 |
|
|
|
353 |
|
|
// select pib clock settings
|
354 |
|
|
ztex_pib_clock2 = ZTEX_FPGA_CONFIGURED ? &ztex_pib_clock : &ztex_fpgaconf1_pib_clock;
|
355 |
|
|
}
|
356 |
|
|
|
357 |
|
|
/* *********************************************************************
|
358 |
|
|
***** ztex_flash_config *********************************************
|
359 |
|
|
********************************************************************* */
|
360 |
|
|
#ifndef DISABLE_FLASH_CONFIG
|
361 |
|
|
#define _ZTEX_FLASH_CONFIG_FUNC_ { ztex_flash_config(); }
|
362 |
|
|
void ztex_flash_config() {
|
363 |
|
|
uint8_t buf[6];
|
364 |
|
|
uint16_t bs_start, bs_size;
|
365 |
|
|
if ( ZTEX_FPGA_CONFIGURED || !ztex_config_data_valid || !ztex_flash.enabled ) return;
|
366 |
|
|
if ( ztex_mac_eeprom_read ( 26, buf, 6 ) ) return;
|
367 |
|
|
|
368 |
|
|
bs_start = ((buf[4] + 15) & 0xf0) | (buf[5] << 8); // in 4k sectors
|
369 |
|
|
bs_size = buf[0] | (buf[1] << 8); // in 4k sectors
|
370 |
|
|
|
371 |
|
|
if (bs_size == 0) return;
|
372 |
|
|
|
373 |
|
|
ZTEX_REC( CyU3PPibInit(CyTrue, &ztex_fpgaconf1_pib_clock) ); // init PIB
|
374 |
|
|
ztex_fpga_config_start(0);
|
375 |
|
|
|
376 |
|
|
for (int i=0; i<bs_size; i++) {
|
377 |
|
|
if ( ztex_flash_read(ztex_ep0buf, (bs_start+i)<<12, 4096) ) {
|
378 |
|
|
ztex_log ( "Error uploading bitstream from Flash: Flash read error" );
|
379 |
|
|
ztex_fpga_config_done(CyTrue);
|
380 |
|
|
return;
|
381 |
|
|
}
|
382 |
|
|
if ( ztex_fpgaconf1_send(ztex_ep0buf, 4096) ) {
|
383 |
|
|
ztex_log ( "Error uploading bitstream from Flash: Bitstream write error" );
|
384 |
|
|
ztex_fpga_config_done(CyTrue);
|
385 |
|
|
return;
|
386 |
|
|
}
|
387 |
|
|
}
|
388 |
|
|
|
389 |
|
|
ztex_fpga_config_done(CyTrue);
|
390 |
|
|
|
391 |
|
|
if ( ZTEX_FPGA_CONFIGURED ) {
|
392 |
|
|
ztex_log ( "Info: Uploaded bitstream from Flash" );
|
393 |
|
|
}
|
394 |
|
|
else {
|
395 |
|
|
ztex_log ( "Error uploading bitstream from Flash: Done pin does not go high" );
|
396 |
|
|
}
|
397 |
|
|
}
|
398 |
|
|
#endif
|
399 |
|
|
|
400 |
|
|
/* *********************************************************************
|
401 |
|
|
***** ztex_board_stop ***********************************************
|
402 |
|
|
********************************************************************* */
|
403 |
|
|
void ztex_board_stop() {
|
404 |
|
|
if ( ztex_fpga_config_started ) { // USB is stopped during configuration
|
405 |
|
|
ztex_fpgaconf1_stop();
|
406 |
|
|
ztex_fpga_config_started = 0;
|
407 |
|
|
}
|
408 |
|
|
}
|
409 |
|
|
|
410 |
|
|
/* *********************************************************************
|
411 |
|
|
***** ztex_enable_otg_supply ****************************************
|
412 |
|
|
********************************************************************* */
|
413 |
|
|
void ztex_enable_otg_supply() {
|
414 |
|
|
ztex_gpio_set(ZTEX_GPIO_OTG_EN, CyTrue);
|
415 |
|
|
|
416 |
|
|
}
|
417 |
|
|
|
418 |
|
|
/* *********************************************************************
|
419 |
|
|
***** ztex_disable_otg_supply ***************************************
|
420 |
|
|
********************************************************************* */
|
421 |
|
|
void ztex_disable_otg_supply() {
|
422 |
|
|
ztex_gpio_set(ZTEX_GPIO_OTG_EN, CyFalse);
|
423 |
|
|
}
|
424 |
|
|
|
425 |
|
|
#endif // _ZTEX_CONF_UFM_2_18_C2_
|
426 |
|
|
#endif // _ZTEX_INCLUDE_2_
|
427 |
|
|
|