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ZTEX |
/*%
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ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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This Source Code Form is subject to the terms of the Mozilla Public
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License, v. 2.0. If a copy of the MPL was not distributed with this file,
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You can obtain one at http://mozilla.org/MPL/2.0/.
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Alternatively, the contents of this file may be used under the terms
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of the GNU General Public License Version 3, as described below:
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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Main include file. See the examples for usage.
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*/
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#include "cyu3system.h"
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#include "cyu3os.h"
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#include "cyu3dma.h"
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#include "cyu3error.h"
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#include "cyu3usb.h"
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#include "cyu3uart.h"
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#include "cyu3pib.h"
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#define ZTEX_VENDOR_REQ_MAX 50 // maximum amount of vendor requests
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#define ZTEX_VENDOR_CMD_MAX 50 // maximum amount of vendor commands
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typedef uint8_t (*ztex_vendor_func) (uint16_t value, uint16_t index, uint16_t length );
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// global configuration
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uint32_t ztex_app_thread_stack = 0x1000; // stack size of application thread
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uint32_t ztex_app_thread_prio = 8; // priority of application thread, should be 7..15
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void (*ztex_app_thread_run)() = 0;
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void (*ztex_usb_start)() = 0; // called when USB connection is started
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void (*ztex_usb_stop)() = 0; // called when USB connection is stopped
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CyBool_t ztex_allow_lpm = CyFalse; // whether to allow low power mode transitions
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// strings for interfaces 0..7, can be overwritten by user
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char* ztex_interface_string[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
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/*
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PIB clock settings for user application.
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*/
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CyU3PPibClock_t ztex_pib_clock = {
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.clkDiv = 6, // 69.33 MHz @ 26 MHz external clock
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.clkSrc = CY_U3P_SYS_CLK,
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.isHalfDiv = CyFalse,
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.isDllEnable = CyTrue
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};
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/*
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PIB clock settings which are currently used.
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They may be under control of a board specific module, e.g. to load
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different clock settings for FPGA configuration.
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*/
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CyU3PPibClock_t *ztex_pib_clock2 = &ztex_pib_clock;
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// called to clean up a transfer when a clear stall request is received, see
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void ep_cleanup_default_handler(uint16_t);
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void (*ztex_ep_cleanup_handler)(uint16_t) = ep_cleanup_default_handler;
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// system stuff
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uint8_t ztex_usb_is_connected = 0;
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// super speed error counters
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#define ZTEX_USB3_SND_ERROR_COUNT (*((uint16_t*) 0xe0033014))
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#define ZTEX_USB3_RCV_ERROR_COUNT (*((uint16_t*) 0xe0033016))
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#ifndef EP_SETUP_FPGACONF
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#define EP_SETUP_FPGACONF
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#endif
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#define EP_SETUP_ALL EP_SETUP EP_SETUP_FPGACONF
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#include "ztex-descriptors.c"
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#include "ztex-debug.c"
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#include "ztex-usb.c"
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#include "ztex-ep0.c"
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#include "ztex-gpio.c"
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// SPI Flash support
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#ifdef ENABLE_SPI_FLASH
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#define ENABLE_SPI
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#include "ztex-flash.c"
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#endif
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// SD Flash support
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#ifdef ENABLE_SD_FLASH
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#include "ztex-sd.c"
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#endif
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#ifdef ENABLE_I2C
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#include "ztex-i2c.c"
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#endif
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#define _ZTEX_INCLUDE_2_
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#ifdef _ZTEX_CONF_UFM_2_02_C1_
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#include "ztex-ufm-2_02.c"
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#endif
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#ifdef _ZTEX_CONF_UFM_2_14_C1_
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#include "ztex-ufm-2_14.c"
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#endif
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#ifdef _ZTEX_CONF_UFM_2_18_C1_
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#include "ztex-ufm-2_18.c"
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#endif
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#ifdef _ZTEX_LSI_
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#include "ztex-lsi.c"
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#endif
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void ztex_usb_start_main() {
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ztex_usb_start_usb();
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if ( ztex_usb_start != 0)
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ztex_usb_start();
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CyU3PUSBSpeed_t usbSpeed = CyU3PUsbGetSpeed();
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ZTEX_LOG ("Info: USB setup finished: %s", usbSpeed == CY_U3P_SUPER_SPEED ? "super speed" : usbSpeed == CY_U3P_HIGH_SPEED ? "high speed" : usbSpeed == CY_U3P_FULL_SPEED ? "full speed" : "not connected" );
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ztex_usb_is_connected = 1;
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}
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void ztex_usb_stop_main() {
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ztex_usb_is_connected = 0;
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if ( ztex_usb_stop != 0)
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ztex_usb_stop();
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#ifdef ENABLE_SPI_FLASH
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ztex_usb_stop_flash();
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#endif
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#ifdef ENABLE_SD_FLASH
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ztex_usb_stop_sd();
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#endif
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#ifdef _ZTEX_BOARD_
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ztex_board_stop();
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#endif
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ztex_usb_stop_usb();
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ztex_log ("Info: USB disconnected.");
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}
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/*
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Default handler to clean up a transfer. Since we do no known how endpoints
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are associated we reset the whole connection. This may no be what is
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expected by the host.
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*/
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void ep_cleanup_default_handler(uint16_t ep) {
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ztex_usb_stop_main();
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CyU3PThreadSleep (1); // Give a chance for the main thread loop to run
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ztex_usb_start_main();
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};
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// USB event handler
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void ztex_usb_event_handler ( CyU3PUsbEventType_t evtype, uint16_t evdata) {
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// ZTEX_LOG("Event: %d",evtype);
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switch (evtype)
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{
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case CY_U3P_USB_EVENT_SETCONF:
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// stop the connection before restarting
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if (ztex_usb_is_connected) {
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ztex_usb_stop_main();
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}
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// start the connection
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ztex_usb_start_main();
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break;
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case CY_U3P_USB_EVENT_RESET:
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case CY_U3P_USB_EVENT_DISCONNECT:
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// stops the connection
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if (ztex_usb_is_connected) {
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ztex_usb_stop_main();
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}
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break;
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default:
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break;
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}
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}
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// LPM (link power management request). Return value CyTrue allows transitions to low power modes.
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CyBool_t ztex_lpm_handler ( CyU3PUsbLinkPowerMode link_mode)
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{
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return ztex_allow_lpm;
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}
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CyU3PThread ztex_app_thread; // ztex application thread structure
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// entry function for the application thread
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void ztex_app_thread_entry (uint32_t input)
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{
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ztex_debug_init();
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ZTEX_REC(CyU3PUsbStart()); // start USB functionality
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CyU3PUsbRegisterSetupCallback(ztex_ep0_handler, CyTrue); // register EP0 handler
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CyU3PUsbRegisterLPMRequestCallback(ztex_lpm_handler); // register link power management handler
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CyU3PUsbRegisterEventCallback(ztex_usb_event_handler); // register USB event handler
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// Set the USB registers
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_SS_DEVICE_DESCR, 0, (uint8_t *)ztex_usb3_device_descriptor) ); // Super speed device descriptor
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_HS_DEVICE_DESCR, 0, (uint8_t *)ztex_usb2_device_descriptor) ); // High speed device descriptor
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_SS_BOS_DESCR, 0, (uint8_t *)ztex_bos_descriptor) ); // BOS descriptor
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_DEVQUAL_DESCR, 0, (uint8_t *)ztex_device_qualifier_descriptor) ); // Device qualifier descriptor
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_SS_CONFIG_DESCR, 0, (uint8_t *)ztex_usb3_config_descriptor) ); // Super speed configuration descriptor
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_HS_CONFIG_DESCR, 0, (uint8_t *)ztex_usb2_config_descriptor) ); // High speed configuration descriptor
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ZTEX_REC( CyU3PUsbSetDesc(CY_U3P_USB_SET_FS_CONFIG_DESCR, 0, (uint8_t *)ztex_usb1_config_descriptor) ); // Full speed configuration descriptor
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CyU3PUsbSetDesc(CY_U3P_USB_SET_STRING_DESCR, 0, (uint8_t *)ztex_lang_string_descriptor); // String descriptor 0 must not be handled by ep0_handler for an undocumented reason
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ztex_gpio_init();
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#ifdef _ZTEX_BOARD_
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ztex_board_init();
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#endif
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#ifdef ENABLE_SPI_FLASH
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ztex_flash_init();
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#endif
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#ifdef ENABLE_SD_FLASH
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ztex_sd_init();
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#endif
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#ifdef ENABLE_I2C
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ztex_i2c_init();
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#endif
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#ifdef _ZTEX_LSI_
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ztex_lsi_init();
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#endif
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#ifdef _ZTEX_FLASH_CONFIG_FUNC_
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_ZTEX_FLASH_CONFIG_FUNC_
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#endif
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// Connect the USB Pins with super speed operation enabled.
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ZTEX_REC( CyU3PConnectState(CyTrue, CyTrue) );
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if ( ztex_app_thread_run != 0)
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ztex_app_thread_run();
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for (;;)
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{
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CyU3PThreadSleep (1000);
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}
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}
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/* This function is expected and called by OS. */
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void CyFxApplicationDefine()
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{
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/* create and start the application thread */
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if ( CyU3PThreadCreate(&ztex_app_thread, // ztex application thread structure
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"21:ztex_app_thread", // thread ID and name
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ztex_app_thread_entry, // entry function
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0, // no input parameter
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CyU3PMemAlloc(ztex_app_thread_stack), // allocate stack memory
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ztex_app_thread_stack, // stack size
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ztex_app_thread_prio, // thread priority
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ztex_app_thread_prio, // preempt threshold
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CYU3P_NO_TIME_SLICE, // no time slice as recommended
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CYU3P_AUTO_START // start the thread immediately
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) != 0
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) ztex_ec = 105;
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}
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/*
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* Main function. Configures the IO-Matrix and starts the OS
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*/
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void ztex_main (void)
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{
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ztex_ec = 101;
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/* Initialize the device */
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CyU3PSysClockConfig_t clock_cfg;
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clock_cfg.setSysClk400 = CyFalse;
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clock_cfg.cpuClkDiv = 2;
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clock_cfg.dmaClkDiv = 2;
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clock_cfg.mmioClkDiv = 2;
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clock_cfg.useStandbyClk = CyFalse;
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clock_cfg.clkSrc = CY_U3P_SYS_CLK;
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if ( CyU3PDeviceInit(&clock_cfg) != CY_U3P_SUCCESS ) ztex_ec = 102;
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/* Initialize the caches. Enable both Instruction and Data Caches. */
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if ( CyU3PDeviceCacheControl(CyTrue, CyTrue, CyTrue) != CY_U3P_SUCCESS ) ztex_ec = 103;
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CyU3PIoMatrixConfig_t io_cfg;
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CyU3PMemSet((uint8_t *)&io_cfg, 0, sizeof(io_cfg));
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io_cfg.isDQ32Bit = CyFalse;
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#ifdef ENABLE_SPORT0
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io_cfg.s0Mode = CY_U3P_SPORT_4BIT;
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#else
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io_cfg.s0Mode = CY_U3P_SPORT_INACTIVE;
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#endif
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io_cfg.s1Mode = CY_U3P_SPORT_INACTIVE;
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#ifdef ENABLE_UART
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io_cfg.useUart = CyTrue;
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#else
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io_cfg.useUart = CyFalse;
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#endif
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#ifdef ENABLE_I2C
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io_cfg.useI2C = CyTrue;
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#else
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io_cfg.useI2C = CyFalse;
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#endif
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io_cfg.useI2S = CyFalse;
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#ifdef ENABLE_SPI
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io_cfg.useSpi = CyTrue;
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#else
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io_cfg.useSpi = CyFalse;
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#endif
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io_cfg.lppMode = CY_U3P_IO_MATRIX_LPP_DEFAULT;
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/* No GPIOs are enabled. */
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io_cfg.gpioSimpleEn[0] = ( ZTEX_GPIO_SIMPLE_BITMAP0 | GPIO_SIMPLE_BITMAP0 ) & ( ~(ZTEX_GPIO_COMPLEX_BITMAP0 | GPIO_COMPLEX_BITMAP0 ) );
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io_cfg.gpioSimpleEn[1] = ( ZTEX_GPIO_SIMPLE_BITMAP1 | GPIO_SIMPLE_BITMAP1 ) & ( ~(ZTEX_GPIO_COMPLEX_BITMAP1 | GPIO_COMPLEX_BITMAP1 ) );
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io_cfg.gpioComplexEn[0] = ZTEX_GPIO_COMPLEX_BITMAP0 | GPIO_COMPLEX_BITMAP0;
|
334 |
|
|
io_cfg.gpioComplexEn[1] = ZTEX_GPIO_COMPLEX_BITMAP1 | GPIO_COMPLEX_BITMAP1;
|
335 |
|
|
if (CyU3PDeviceConfigureIOMatrix (&io_cfg) != CY_U3P_SUCCESS) ztex_ec = 104;
|
336 |
|
|
|
337 |
|
|
/* This is a non returnable call for initializing the RTOS kernel */
|
338 |
|
|
ztex_ec = 0;
|
339 |
|
|
CyU3PKernelEntry ();
|
340 |
|
|
}
|
341 |
|
|
|