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melman701 |
## Generated SDC file "test_usb_ft232h.out.sdc"
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## Copyright (C) 2017 Intel Corporation. All rights reserved.
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## Your use of Intel Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Intel Program License
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## Subscription Agreement, the Intel Quartus Prime License Agreement,
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## the Intel MegaCore Function License Agreement, or other
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## applicable license agreement, including, without limitation,
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## that your use is for the sole purpose of programming logic
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## devices manufactured by Intel and sold by Intel or its
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## authorized distributors. Please refer to the applicable
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## agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus Prime"
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## VERSION "Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition"
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## DATE "Thu Apr 6 13:43:18 2017"
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##
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## DEVICE "EP4CE22E22C8"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
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create_clock -name {CLOCK_IN} -period 61.035 -waveform { 0.000 30.517 } [get_ports {CLOCK_IN}]
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create_clock -name {USB_CLK} -period 16.666 -waveform { 0.000 8.333 } [get_ports {USB_CLK}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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create_generated_clock -name {inst1|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 25 -divide_by 4 -master_clock {inst|altpll_component|auto_generated|pll1|clk[0]} [get_pins {inst1|altpll_component|auto_generated|pll1|clk[0]}]
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create_generated_clock -name {inst1|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 25 -divide_by 4 -phase -90.000 -master_clock {inst|altpll_component|auto_generated|pll1|clk[0]} [get_pins {inst1|altpll_component|auto_generated|pll1|clk[1]}]
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create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 125 -divide_by 128 -master_clock {CLOCK_IN} [get_pins {inst|altpll_component|auto_generated|pll1|clk[0]}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] 0.020
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set_clock_uncertainty -rise_from [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst1|altpll_component|auto_generated|pll1|clk[0]}] 0.020
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set_clock_uncertainty -rise_from [get_clocks {USB_CLK}] -rise_to [get_clocks {USB_CLK}] 0.020
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set_clock_uncertainty -rise_from [get_clocks {USB_CLK}] -fall_to [get_clocks {USB_CLK}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {USB_CLK}] -rise_to [get_clocks {USB_CLK}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {USB_CLK}] -fall_to [get_clocks {USB_CLK}] 0.020
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set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 0.020
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set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 0.020
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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set_clock_groups -physically_exclusive -group [get_clocks {USB_CLK}]
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set_clock_groups -logically_exclusive -group [get_clocks {CLOCK_IN}]
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set_clock_groups -logically_exclusive -group [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
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set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
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set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
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set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_3f9:dffpipe22|dffe23a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_0f9:dffpipe13|dffe14a*}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_2f9:dffpipe14|dffe15a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_1f9:dffpipe5|dffe6a*}]
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set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}]
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set_false_path -from [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_nios2_oci_break:the_sopc_cpu_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_tck:the_sopc_cpu_cpu_debug_slave_tck|*sr*}]
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set_false_path -from [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_nios2_oci_debug:the_sopc_cpu_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_tck:the_sopc_cpu_cpu_debug_slave_tck|*sr[33]}]
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set_false_path -from [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_nios2_oci_debug:the_sopc_cpu_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_tck:the_sopc_cpu_cpu_debug_slave_tck|*sr[0]}]
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set_false_path -from [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_nios2_oci_debug:the_sopc_cpu_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_tck:the_sopc_cpu_cpu_debug_slave_tck|*sr[34]}]
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set_false_path -from [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_nios2_ocimem:the_sopc_cpu_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_tck:the_sopc_cpu_cpu_debug_slave_tck|*sr*}]
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set_false_path -from [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_tck:the_sopc_cpu_cpu_debug_slave_tck|*sr*}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_sysclk:the_sopc_cpu_cpu_debug_slave_sysclk|*jdo*}]
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set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_debug_slave_wrapper:the_sopc_cpu_cpu_debug_slave_wrapper|sopc_cpu_cpu_debug_slave_sysclk:the_sopc_cpu_cpu_debug_slave_sysclk|ir*}]
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set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*sopc_cpu_cpu:*|sopc_cpu_cpu_nios2_oci:the_sopc_cpu_cpu_nios2_oci|sopc_cpu_cpu_nios2_oci_debug:the_sopc_cpu_cpu_nios2_oci_debug|monitor_go}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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