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ultra_embe |
//-----------------------------------------------------------------
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// USB Full Speed Host
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// V0.5
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// Ultra-Embedded.com
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// Copyright 2015-2019
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//
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// Email: admin@ultra-embedded.com
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//
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// License: GPL
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// If you would like a version with a more permissive license for
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// use in closed source commercial applications please contact me
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// for details.
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//-----------------------------------------------------------------
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//
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// This file is open source HDL; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// This file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this file; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Generated File
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//-----------------------------------------------------------------
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`include "usbh_host_defs.v"
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//-----------------------------------------------------------------
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// Module: USB Host IP
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//-----------------------------------------------------------------
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module usbh_host
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(
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// Inputs
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input clk_i
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,input rst_i
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,input cfg_awvalid_i
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,input [31:0] cfg_awaddr_i
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,input cfg_wvalid_i
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,input [31:0] cfg_wdata_i
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,input [3:0] cfg_wstrb_i
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,input cfg_bready_i
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,input cfg_arvalid_i
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,input [31:0] cfg_araddr_i
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,input cfg_rready_i
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,input [7:0] utmi_data_in_i
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,input utmi_txready_i
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,input utmi_rxvalid_i
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,input utmi_rxactive_i
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,input utmi_rxerror_i
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,input [1:0] utmi_linestate_i
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// Outputs
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,output cfg_awready_o
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,output cfg_wready_o
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,output cfg_bvalid_o
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,output [1:0] cfg_bresp_o
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,output cfg_arready_o
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,output cfg_rvalid_o
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,output [31:0] cfg_rdata_o
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,output [1:0] cfg_rresp_o
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,output intr_o
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,output [7:0] utmi_data_out_o
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,output utmi_txvalid_o
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,output [1:0] utmi_op_mode_o
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,output [1:0] utmi_xcvrselect_o
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,output utmi_termselect_o
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,output utmi_dppulldown_o
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,output utmi_dmpulldown_o
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);
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//-----------------------------------------------------------------
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// Retime write data
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//-----------------------------------------------------------------
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reg [31:0] wr_data_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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wr_data_q <= 32'b0;
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else
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wr_data_q <= cfg_wdata_i;
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//-----------------------------------------------------------------
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// Request Logic
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//-----------------------------------------------------------------
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wire read_en_w = cfg_arvalid_i & cfg_arready_o;
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wire write_en_w = cfg_awvalid_i & cfg_awready_o;
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//-----------------------------------------------------------------
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// Accept Logic
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//-----------------------------------------------------------------
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assign cfg_arready_o = ~cfg_rvalid_o;
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assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i;
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assign cfg_wready_o = cfg_awready_o;
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//-----------------------------------------------------------------
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// Register usb_ctrl
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//-----------------------------------------------------------------
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reg usb_ctrl_wr_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_wr_q <= 1'b0;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_wr_q <= 1'b1;
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else
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usb_ctrl_wr_q <= 1'b0;
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// usb_ctrl_phy_dmpulldown [internal]
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reg usb_ctrl_phy_dmpulldown_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_phy_dmpulldown_q <= 1'd`USB_CTRL_PHY_DMPULLDOWN_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_phy_dmpulldown_q <= cfg_wdata_i[`USB_CTRL_PHY_DMPULLDOWN_R];
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wire usb_ctrl_phy_dmpulldown_out_w = usb_ctrl_phy_dmpulldown_q;
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// usb_ctrl_phy_dppulldown [internal]
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reg usb_ctrl_phy_dppulldown_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_phy_dppulldown_q <= 1'd`USB_CTRL_PHY_DPPULLDOWN_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_phy_dppulldown_q <= cfg_wdata_i[`USB_CTRL_PHY_DPPULLDOWN_R];
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wire usb_ctrl_phy_dppulldown_out_w = usb_ctrl_phy_dppulldown_q;
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// usb_ctrl_phy_termselect [internal]
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reg usb_ctrl_phy_termselect_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_phy_termselect_q <= 1'd`USB_CTRL_PHY_TERMSELECT_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_phy_termselect_q <= cfg_wdata_i[`USB_CTRL_PHY_TERMSELECT_R];
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wire usb_ctrl_phy_termselect_out_w = usb_ctrl_phy_termselect_q;
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// usb_ctrl_phy_xcvrselect [internal]
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reg [1:0] usb_ctrl_phy_xcvrselect_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_phy_xcvrselect_q <= 2'd`USB_CTRL_PHY_XCVRSELECT_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_phy_xcvrselect_q <= cfg_wdata_i[`USB_CTRL_PHY_XCVRSELECT_R];
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wire [1:0] usb_ctrl_phy_xcvrselect_out_w = usb_ctrl_phy_xcvrselect_q;
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// usb_ctrl_phy_opmode [internal]
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reg [1:0] usb_ctrl_phy_opmode_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_phy_opmode_q <= 2'd`USB_CTRL_PHY_OPMODE_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_phy_opmode_q <= cfg_wdata_i[`USB_CTRL_PHY_OPMODE_R];
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wire [1:0] usb_ctrl_phy_opmode_out_w = usb_ctrl_phy_opmode_q;
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// usb_ctrl_tx_flush [auto_clr]
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reg usb_ctrl_tx_flush_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_tx_flush_q <= 1'd`USB_CTRL_TX_FLUSH_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_tx_flush_q <= cfg_wdata_i[`USB_CTRL_TX_FLUSH_R];
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else
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usb_ctrl_tx_flush_q <= 1'd`USB_CTRL_TX_FLUSH_DEFAULT;
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wire usb_ctrl_tx_flush_out_w = usb_ctrl_tx_flush_q;
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// usb_ctrl_enable_sof [internal]
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reg usb_ctrl_enable_sof_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_ctrl_enable_sof_q <= 1'd`USB_CTRL_ENABLE_SOF_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_CTRL))
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usb_ctrl_enable_sof_q <= cfg_wdata_i[`USB_CTRL_ENABLE_SOF_R];
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wire usb_ctrl_enable_sof_out_w = usb_ctrl_enable_sof_q;
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//-----------------------------------------------------------------
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// Register usb_status
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//-----------------------------------------------------------------
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reg usb_status_wr_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_status_wr_q <= 1'b0;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_STATUS))
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usb_status_wr_q <= 1'b1;
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else
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usb_status_wr_q <= 1'b0;
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//-----------------------------------------------------------------
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// Register usb_irq_ack
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//-----------------------------------------------------------------
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reg usb_irq_ack_wr_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_ack_wr_q <= 1'b0;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_ACK))
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usb_irq_ack_wr_q <= 1'b1;
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else
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usb_irq_ack_wr_q <= 1'b0;
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// usb_irq_ack_device_detect [auto_clr]
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reg usb_irq_ack_device_detect_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_ack_device_detect_q <= 1'd`USB_IRQ_ACK_DEVICE_DETECT_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_ACK))
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usb_irq_ack_device_detect_q <= cfg_wdata_i[`USB_IRQ_ACK_DEVICE_DETECT_R];
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else
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usb_irq_ack_device_detect_q <= 1'd`USB_IRQ_ACK_DEVICE_DETECT_DEFAULT;
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wire usb_irq_ack_device_detect_out_w = usb_irq_ack_device_detect_q;
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// usb_irq_ack_err [auto_clr]
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reg usb_irq_ack_err_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_ack_err_q <= 1'd`USB_IRQ_ACK_ERR_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_ACK))
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usb_irq_ack_err_q <= cfg_wdata_i[`USB_IRQ_ACK_ERR_R];
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else
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usb_irq_ack_err_q <= 1'd`USB_IRQ_ACK_ERR_DEFAULT;
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wire usb_irq_ack_err_out_w = usb_irq_ack_err_q;
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// usb_irq_ack_done [auto_clr]
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reg usb_irq_ack_done_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_ack_done_q <= 1'd`USB_IRQ_ACK_DONE_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_ACK))
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usb_irq_ack_done_q <= cfg_wdata_i[`USB_IRQ_ACK_DONE_R];
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else
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usb_irq_ack_done_q <= 1'd`USB_IRQ_ACK_DONE_DEFAULT;
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wire usb_irq_ack_done_out_w = usb_irq_ack_done_q;
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// usb_irq_ack_sof [auto_clr]
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reg usb_irq_ack_sof_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_ack_sof_q <= 1'd`USB_IRQ_ACK_SOF_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_ACK))
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usb_irq_ack_sof_q <= cfg_wdata_i[`USB_IRQ_ACK_SOF_R];
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else
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usb_irq_ack_sof_q <= 1'd`USB_IRQ_ACK_SOF_DEFAULT;
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wire usb_irq_ack_sof_out_w = usb_irq_ack_sof_q;
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//-----------------------------------------------------------------
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// Register usb_irq_sts
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//-----------------------------------------------------------------
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reg usb_irq_sts_wr_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_sts_wr_q <= 1'b0;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_STS))
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usb_irq_sts_wr_q <= 1'b1;
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else
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usb_irq_sts_wr_q <= 1'b0;
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//-----------------------------------------------------------------
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// Register usb_irq_mask
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//-----------------------------------------------------------------
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reg usb_irq_mask_wr_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_mask_wr_q <= 1'b0;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_MASK))
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usb_irq_mask_wr_q <= 1'b1;
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else
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usb_irq_mask_wr_q <= 1'b0;
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319 |
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// usb_irq_mask_device_detect [internal]
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reg usb_irq_mask_device_detect_q;
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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usb_irq_mask_device_detect_q <= 1'd`USB_IRQ_MASK_DEVICE_DETECT_DEFAULT;
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else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_MASK))
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usb_irq_mask_device_detect_q <= cfg_wdata_i[`USB_IRQ_MASK_DEVICE_DETECT_R];
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328 |
|
|
wire usb_irq_mask_device_detect_out_w = usb_irq_mask_device_detect_q;
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
// usb_irq_mask_err [internal]
|
332 |
|
|
reg usb_irq_mask_err_q;
|
333 |
|
|
|
334 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
335 |
|
|
if (rst_i)
|
336 |
|
|
usb_irq_mask_err_q <= 1'd`USB_IRQ_MASK_ERR_DEFAULT;
|
337 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_MASK))
|
338 |
|
|
usb_irq_mask_err_q <= cfg_wdata_i[`USB_IRQ_MASK_ERR_R];
|
339 |
|
|
|
340 |
|
|
wire usb_irq_mask_err_out_w = usb_irq_mask_err_q;
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
// usb_irq_mask_done [internal]
|
344 |
|
|
reg usb_irq_mask_done_q;
|
345 |
|
|
|
346 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
347 |
|
|
if (rst_i)
|
348 |
|
|
usb_irq_mask_done_q <= 1'd`USB_IRQ_MASK_DONE_DEFAULT;
|
349 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_MASK))
|
350 |
|
|
usb_irq_mask_done_q <= cfg_wdata_i[`USB_IRQ_MASK_DONE_R];
|
351 |
|
|
|
352 |
|
|
wire usb_irq_mask_done_out_w = usb_irq_mask_done_q;
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
// usb_irq_mask_sof [internal]
|
356 |
|
|
reg usb_irq_mask_sof_q;
|
357 |
|
|
|
358 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
359 |
|
|
if (rst_i)
|
360 |
|
|
usb_irq_mask_sof_q <= 1'd`USB_IRQ_MASK_SOF_DEFAULT;
|
361 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_IRQ_MASK))
|
362 |
|
|
usb_irq_mask_sof_q <= cfg_wdata_i[`USB_IRQ_MASK_SOF_R];
|
363 |
|
|
|
364 |
|
|
wire usb_irq_mask_sof_out_w = usb_irq_mask_sof_q;
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
//-----------------------------------------------------------------
|
368 |
|
|
// Register usb_xfer_data
|
369 |
|
|
//-----------------------------------------------------------------
|
370 |
|
|
reg usb_xfer_data_wr_q;
|
371 |
|
|
|
372 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
373 |
|
|
if (rst_i)
|
374 |
|
|
usb_xfer_data_wr_q <= 1'b0;
|
375 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_DATA))
|
376 |
|
|
usb_xfer_data_wr_q <= 1'b1;
|
377 |
|
|
else
|
378 |
|
|
usb_xfer_data_wr_q <= 1'b0;
|
379 |
|
|
|
380 |
|
|
// usb_xfer_data_tx_len [internal]
|
381 |
|
|
reg [15:0] usb_xfer_data_tx_len_q;
|
382 |
|
|
|
383 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
384 |
|
|
if (rst_i)
|
385 |
|
|
usb_xfer_data_tx_len_q <= 16'd`USB_XFER_DATA_TX_LEN_DEFAULT;
|
386 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_DATA))
|
387 |
|
|
usb_xfer_data_tx_len_q <= cfg_wdata_i[`USB_XFER_DATA_TX_LEN_R];
|
388 |
|
|
|
389 |
|
|
wire [15:0] usb_xfer_data_tx_len_out_w = usb_xfer_data_tx_len_q;
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
//-----------------------------------------------------------------
|
393 |
|
|
// Register usb_xfer_token
|
394 |
|
|
//-----------------------------------------------------------------
|
395 |
|
|
reg usb_xfer_token_wr_q;
|
396 |
|
|
|
397 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
398 |
|
|
if (rst_i)
|
399 |
|
|
usb_xfer_token_wr_q <= 1'b0;
|
400 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
401 |
|
|
usb_xfer_token_wr_q <= 1'b1;
|
402 |
|
|
else
|
403 |
|
|
usb_xfer_token_wr_q <= 1'b0;
|
404 |
|
|
|
405 |
|
|
// usb_xfer_token_start [clearable]
|
406 |
|
|
reg usb_xfer_token_start_q;
|
407 |
|
|
|
408 |
|
|
wire usb_xfer_token_start_ack_in_w;
|
409 |
|
|
|
410 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
411 |
|
|
if (rst_i)
|
412 |
|
|
usb_xfer_token_start_q <= 1'b0;
|
413 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
414 |
|
|
usb_xfer_token_start_q <= cfg_wdata_i[`USB_XFER_TOKEN_START_R];
|
415 |
|
|
else if (usb_xfer_token_start_ack_in_w)
|
416 |
|
|
usb_xfer_token_start_q <= 1'b0;
|
417 |
|
|
|
418 |
|
|
wire usb_xfer_token_start_out_w = usb_xfer_token_start_q;
|
419 |
|
|
|
420 |
|
|
|
421 |
|
|
// usb_xfer_token_in [internal]
|
422 |
|
|
reg usb_xfer_token_in_q;
|
423 |
|
|
|
424 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
425 |
|
|
if (rst_i)
|
426 |
|
|
usb_xfer_token_in_q <= 1'd`USB_XFER_TOKEN_IN_DEFAULT;
|
427 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
428 |
|
|
usb_xfer_token_in_q <= cfg_wdata_i[`USB_XFER_TOKEN_IN_R];
|
429 |
|
|
|
430 |
|
|
wire usb_xfer_token_in_out_w = usb_xfer_token_in_q;
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
// usb_xfer_token_ack [internal]
|
434 |
|
|
reg usb_xfer_token_ack_q;
|
435 |
|
|
|
436 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
437 |
|
|
if (rst_i)
|
438 |
|
|
usb_xfer_token_ack_q <= 1'd`USB_XFER_TOKEN_ACK_DEFAULT;
|
439 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
440 |
|
|
usb_xfer_token_ack_q <= cfg_wdata_i[`USB_XFER_TOKEN_ACK_R];
|
441 |
|
|
|
442 |
|
|
wire usb_xfer_token_ack_out_w = usb_xfer_token_ack_q;
|
443 |
|
|
|
444 |
|
|
|
445 |
|
|
// usb_xfer_token_pid_datax [internal]
|
446 |
|
|
reg usb_xfer_token_pid_datax_q;
|
447 |
|
|
|
448 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
449 |
|
|
if (rst_i)
|
450 |
|
|
usb_xfer_token_pid_datax_q <= 1'd`USB_XFER_TOKEN_PID_DATAX_DEFAULT;
|
451 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
452 |
|
|
usb_xfer_token_pid_datax_q <= cfg_wdata_i[`USB_XFER_TOKEN_PID_DATAX_R];
|
453 |
|
|
|
454 |
|
|
wire usb_xfer_token_pid_datax_out_w = usb_xfer_token_pid_datax_q;
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
// usb_xfer_token_pid_bits [internal]
|
458 |
|
|
reg [7:0] usb_xfer_token_pid_bits_q;
|
459 |
|
|
|
460 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
461 |
|
|
if (rst_i)
|
462 |
|
|
usb_xfer_token_pid_bits_q <= 8'd`USB_XFER_TOKEN_PID_BITS_DEFAULT;
|
463 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
464 |
|
|
usb_xfer_token_pid_bits_q <= cfg_wdata_i[`USB_XFER_TOKEN_PID_BITS_R];
|
465 |
|
|
|
466 |
|
|
wire [7:0] usb_xfer_token_pid_bits_out_w = usb_xfer_token_pid_bits_q;
|
467 |
|
|
|
468 |
|
|
|
469 |
|
|
// usb_xfer_token_dev_addr [internal]
|
470 |
|
|
reg [6:0] usb_xfer_token_dev_addr_q;
|
471 |
|
|
|
472 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
473 |
|
|
if (rst_i)
|
474 |
|
|
usb_xfer_token_dev_addr_q <= 7'd`USB_XFER_TOKEN_DEV_ADDR_DEFAULT;
|
475 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
476 |
|
|
usb_xfer_token_dev_addr_q <= cfg_wdata_i[`USB_XFER_TOKEN_DEV_ADDR_R];
|
477 |
|
|
|
478 |
|
|
wire [6:0] usb_xfer_token_dev_addr_out_w = usb_xfer_token_dev_addr_q;
|
479 |
|
|
|
480 |
|
|
|
481 |
|
|
// usb_xfer_token_ep_addr [internal]
|
482 |
|
|
reg [3:0] usb_xfer_token_ep_addr_q;
|
483 |
|
|
|
484 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
485 |
|
|
if (rst_i)
|
486 |
|
|
usb_xfer_token_ep_addr_q <= 4'd`USB_XFER_TOKEN_EP_ADDR_DEFAULT;
|
487 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_XFER_TOKEN))
|
488 |
|
|
usb_xfer_token_ep_addr_q <= cfg_wdata_i[`USB_XFER_TOKEN_EP_ADDR_R];
|
489 |
|
|
|
490 |
|
|
wire [3:0] usb_xfer_token_ep_addr_out_w = usb_xfer_token_ep_addr_q;
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
//-----------------------------------------------------------------
|
494 |
|
|
// Register usb_rx_stat
|
495 |
|
|
//-----------------------------------------------------------------
|
496 |
|
|
reg usb_rx_stat_wr_q;
|
497 |
|
|
|
498 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
499 |
|
|
if (rst_i)
|
500 |
|
|
usb_rx_stat_wr_q <= 1'b0;
|
501 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_RX_STAT))
|
502 |
|
|
usb_rx_stat_wr_q <= 1'b1;
|
503 |
|
|
else
|
504 |
|
|
usb_rx_stat_wr_q <= 1'b0;
|
505 |
|
|
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
|
509 |
|
|
|
510 |
|
|
|
511 |
|
|
|
512 |
|
|
//-----------------------------------------------------------------
|
513 |
|
|
// Register usb_wr_data
|
514 |
|
|
//-----------------------------------------------------------------
|
515 |
|
|
reg usb_wr_data_wr_q;
|
516 |
|
|
|
517 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
518 |
|
|
if (rst_i)
|
519 |
|
|
usb_wr_data_wr_q <= 1'b0;
|
520 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_WR_DATA))
|
521 |
|
|
usb_wr_data_wr_q <= 1'b1;
|
522 |
|
|
else
|
523 |
|
|
usb_wr_data_wr_q <= 1'b0;
|
524 |
|
|
|
525 |
|
|
// usb_wr_data_data [external]
|
526 |
|
|
wire [7:0] usb_wr_data_data_out_w = wr_data_q[`USB_WR_DATA_DATA_R];
|
527 |
|
|
|
528 |
|
|
|
529 |
|
|
//-----------------------------------------------------------------
|
530 |
|
|
// Register usb_rd_data
|
531 |
|
|
//-----------------------------------------------------------------
|
532 |
|
|
reg usb_rd_data_wr_q;
|
533 |
|
|
|
534 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
535 |
|
|
if (rst_i)
|
536 |
|
|
usb_rd_data_wr_q <= 1'b0;
|
537 |
|
|
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_RD_DATA))
|
538 |
|
|
usb_rd_data_wr_q <= 1'b1;
|
539 |
|
|
else
|
540 |
|
|
usb_rd_data_wr_q <= 1'b0;
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
wire [15:0] usb_status_sof_time_in_w;
|
544 |
|
|
wire usb_status_rx_error_in_w;
|
545 |
|
|
wire [1:0] usb_status_linestate_bits_in_w;
|
546 |
|
|
wire usb_irq_sts_device_detect_in_w;
|
547 |
|
|
wire usb_irq_sts_err_in_w;
|
548 |
|
|
wire usb_irq_sts_done_in_w;
|
549 |
|
|
wire usb_irq_sts_sof_in_w;
|
550 |
|
|
wire usb_rx_stat_start_pend_in_w;
|
551 |
|
|
wire usb_rx_stat_crc_err_in_w;
|
552 |
|
|
wire usb_rx_stat_resp_timeout_in_w;
|
553 |
|
|
wire usb_rx_stat_idle_in_w;
|
554 |
|
|
wire [7:0] usb_rx_stat_resp_bits_in_w;
|
555 |
|
|
wire [15:0] usb_rx_stat_count_bits_in_w;
|
556 |
|
|
wire [7:0] usb_rd_data_data_in_w;
|
557 |
|
|
|
558 |
|
|
|
559 |
|
|
//-----------------------------------------------------------------
|
560 |
|
|
// Read mux
|
561 |
|
|
//-----------------------------------------------------------------
|
562 |
|
|
reg [31:0] data_r;
|
563 |
|
|
|
564 |
|
|
always @ *
|
565 |
|
|
begin
|
566 |
|
|
data_r = 32'b0;
|
567 |
|
|
|
568 |
|
|
case (cfg_araddr_i[7:0])
|
569 |
|
|
|
570 |
|
|
`USB_CTRL:
|
571 |
|
|
begin
|
572 |
|
|
data_r[`USB_CTRL_PHY_DMPULLDOWN_R] = usb_ctrl_phy_dmpulldown_q;
|
573 |
|
|
data_r[`USB_CTRL_PHY_DPPULLDOWN_R] = usb_ctrl_phy_dppulldown_q;
|
574 |
|
|
data_r[`USB_CTRL_PHY_TERMSELECT_R] = usb_ctrl_phy_termselect_q;
|
575 |
|
|
data_r[`USB_CTRL_PHY_XCVRSELECT_R] = usb_ctrl_phy_xcvrselect_q;
|
576 |
|
|
data_r[`USB_CTRL_PHY_OPMODE_R] = usb_ctrl_phy_opmode_q;
|
577 |
|
|
data_r[`USB_CTRL_ENABLE_SOF_R] = usb_ctrl_enable_sof_q;
|
578 |
|
|
end
|
579 |
|
|
`USB_STATUS:
|
580 |
|
|
begin
|
581 |
|
|
data_r[`USB_STATUS_SOF_TIME_R] = usb_status_sof_time_in_w;
|
582 |
|
|
data_r[`USB_STATUS_RX_ERROR_R] = usb_status_rx_error_in_w;
|
583 |
|
|
data_r[`USB_STATUS_LINESTATE_BITS_R] = usb_status_linestate_bits_in_w;
|
584 |
|
|
end
|
585 |
|
|
`USB_IRQ_STS:
|
586 |
|
|
begin
|
587 |
|
|
data_r[`USB_IRQ_STS_DEVICE_DETECT_R] = usb_irq_sts_device_detect_in_w;
|
588 |
|
|
data_r[`USB_IRQ_STS_ERR_R] = usb_irq_sts_err_in_w;
|
589 |
|
|
data_r[`USB_IRQ_STS_DONE_R] = usb_irq_sts_done_in_w;
|
590 |
|
|
data_r[`USB_IRQ_STS_SOF_R] = usb_irq_sts_sof_in_w;
|
591 |
|
|
end
|
592 |
|
|
`USB_IRQ_MASK:
|
593 |
|
|
begin
|
594 |
|
|
data_r[`USB_IRQ_MASK_DEVICE_DETECT_R] = usb_irq_mask_device_detect_q;
|
595 |
|
|
data_r[`USB_IRQ_MASK_ERR_R] = usb_irq_mask_err_q;
|
596 |
|
|
data_r[`USB_IRQ_MASK_DONE_R] = usb_irq_mask_done_q;
|
597 |
|
|
data_r[`USB_IRQ_MASK_SOF_R] = usb_irq_mask_sof_q;
|
598 |
|
|
end
|
599 |
|
|
`USB_XFER_DATA:
|
600 |
|
|
begin
|
601 |
|
|
data_r[`USB_XFER_DATA_TX_LEN_R] = usb_xfer_data_tx_len_q;
|
602 |
|
|
end
|
603 |
|
|
`USB_XFER_TOKEN:
|
604 |
|
|
begin
|
605 |
|
|
data_r[`USB_XFER_TOKEN_IN_R] = usb_xfer_token_in_q;
|
606 |
|
|
data_r[`USB_XFER_TOKEN_ACK_R] = usb_xfer_token_ack_q;
|
607 |
|
|
data_r[`USB_XFER_TOKEN_PID_DATAX_R] = usb_xfer_token_pid_datax_q;
|
608 |
|
|
data_r[`USB_XFER_TOKEN_PID_BITS_R] = usb_xfer_token_pid_bits_q;
|
609 |
|
|
data_r[`USB_XFER_TOKEN_DEV_ADDR_R] = usb_xfer_token_dev_addr_q;
|
610 |
|
|
data_r[`USB_XFER_TOKEN_EP_ADDR_R] = usb_xfer_token_ep_addr_q;
|
611 |
|
|
end
|
612 |
|
|
`USB_RX_STAT:
|
613 |
|
|
begin
|
614 |
|
|
data_r[`USB_RX_STAT_START_PEND_R] = usb_rx_stat_start_pend_in_w;
|
615 |
|
|
data_r[`USB_RX_STAT_CRC_ERR_R] = usb_rx_stat_crc_err_in_w;
|
616 |
|
|
data_r[`USB_RX_STAT_RESP_TIMEOUT_R] = usb_rx_stat_resp_timeout_in_w;
|
617 |
|
|
data_r[`USB_RX_STAT_IDLE_R] = usb_rx_stat_idle_in_w;
|
618 |
|
|
data_r[`USB_RX_STAT_RESP_BITS_R] = usb_rx_stat_resp_bits_in_w;
|
619 |
|
|
data_r[`USB_RX_STAT_COUNT_BITS_R] = usb_rx_stat_count_bits_in_w;
|
620 |
|
|
end
|
621 |
|
|
`USB_RD_DATA:
|
622 |
|
|
begin
|
623 |
|
|
data_r[`USB_RD_DATA_DATA_R] = usb_rd_data_data_in_w;
|
624 |
|
|
end
|
625 |
|
|
default :
|
626 |
|
|
data_r = 32'b0;
|
627 |
|
|
endcase
|
628 |
|
|
end
|
629 |
|
|
|
630 |
|
|
//-----------------------------------------------------------------
|
631 |
|
|
// RVALID
|
632 |
|
|
//-----------------------------------------------------------------
|
633 |
|
|
reg rvalid_q;
|
634 |
|
|
|
635 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
636 |
|
|
if (rst_i)
|
637 |
|
|
rvalid_q <= 1'b0;
|
638 |
|
|
else if (read_en_w)
|
639 |
|
|
rvalid_q <= 1'b1;
|
640 |
|
|
else if (cfg_rready_i)
|
641 |
|
|
rvalid_q <= 1'b0;
|
642 |
|
|
|
643 |
|
|
assign cfg_rvalid_o = rvalid_q;
|
644 |
|
|
|
645 |
|
|
//-----------------------------------------------------------------
|
646 |
|
|
// Retime read response
|
647 |
|
|
//-----------------------------------------------------------------
|
648 |
|
|
reg [31:0] rd_data_q;
|
649 |
|
|
|
650 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
651 |
|
|
if (rst_i)
|
652 |
|
|
rd_data_q <= 32'b0;
|
653 |
|
|
else if (!cfg_rvalid_o || cfg_rready_i)
|
654 |
|
|
rd_data_q <= data_r;
|
655 |
|
|
|
656 |
|
|
assign cfg_rdata_o = rd_data_q;
|
657 |
|
|
assign cfg_rresp_o = 2'b0;
|
658 |
|
|
|
659 |
|
|
//-----------------------------------------------------------------
|
660 |
|
|
// BVALID
|
661 |
|
|
//-----------------------------------------------------------------
|
662 |
|
|
reg bvalid_q;
|
663 |
|
|
|
664 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
665 |
|
|
if (rst_i)
|
666 |
|
|
bvalid_q <= 1'b0;
|
667 |
|
|
else if (write_en_w)
|
668 |
|
|
bvalid_q <= 1'b1;
|
669 |
|
|
else if (cfg_bready_i)
|
670 |
|
|
bvalid_q <= 1'b0;
|
671 |
|
|
|
672 |
|
|
assign cfg_bvalid_o = bvalid_q;
|
673 |
|
|
assign cfg_bresp_o = 2'b0;
|
674 |
|
|
|
675 |
|
|
wire usb_rd_data_rd_req_w = read_en_w & (cfg_araddr_i[7:0] == `USB_RD_DATA);
|
676 |
|
|
|
677 |
|
|
wire usb_wr_data_wr_req_w = usb_wr_data_wr_q;
|
678 |
|
|
wire usb_rd_data_wr_req_w = usb_rd_data_wr_q;
|
679 |
|
|
|
680 |
|
|
//-----------------------------------------------------------------
|
681 |
|
|
// Registers / Wires
|
682 |
|
|
//-----------------------------------------------------------------
|
683 |
|
|
// SOF
|
684 |
|
|
reg [10:0] sof_value_q;
|
685 |
|
|
reg [15:0] sof_time_q;
|
686 |
|
|
reg sof_irq_q;
|
687 |
|
|
|
688 |
|
|
reg transfer_req_ack_q;
|
689 |
|
|
|
690 |
|
|
wire [7:0] fifo_tx_data_w;
|
691 |
|
|
wire fifo_tx_pop_w;
|
692 |
|
|
|
693 |
|
|
wire [7:0] fifo_rx_data_w;
|
694 |
|
|
wire fifo_rx_push_w;
|
695 |
|
|
|
696 |
|
|
reg fifo_flush_q;
|
697 |
|
|
|
698 |
|
|
wire [7:0] token_pid_w;
|
699 |
|
|
wire [6:0] token_dev_w;
|
700 |
|
|
wire [3:0] token_ep_w;
|
701 |
|
|
|
702 |
|
|
reg transfer_start_q;
|
703 |
|
|
reg in_transfer_q;
|
704 |
|
|
reg sof_transfer_q;
|
705 |
|
|
reg resp_expected_q;
|
706 |
|
|
wire transfer_ack_w;
|
707 |
|
|
|
708 |
|
|
wire status_crc_err_w;
|
709 |
|
|
wire status_timeout_w;
|
710 |
|
|
wire [7:0] status_response_w;
|
711 |
|
|
wire [15:0] status_rx_count_w;
|
712 |
|
|
wire status_sie_idle_w;
|
713 |
|
|
wire status_tx_done_w;
|
714 |
|
|
wire status_rx_done_w;
|
715 |
|
|
|
716 |
|
|
wire send_sof_w;
|
717 |
|
|
wire sof_gaurd_band_w;
|
718 |
|
|
wire clear_to_send_w;
|
719 |
|
|
|
720 |
|
|
reg usb_err_q;
|
721 |
|
|
|
722 |
|
|
reg intr_done_q;
|
723 |
|
|
reg intr_sof_q;
|
724 |
|
|
reg intr_err_q;
|
725 |
|
|
|
726 |
|
|
//-----------------------------------------------------------------
|
727 |
|
|
// Definitions
|
728 |
|
|
//-----------------------------------------------------------------
|
729 |
|
|
localparam [15:0] SOF_ZERO = 0;
|
730 |
|
|
localparam [15:0] SOF_INC = 1;
|
731 |
|
|
localparam [15:0] SOF_THRESHOLD = 48000-1;
|
732 |
|
|
|
733 |
|
|
localparam [15:0] CLKS_PER_BIT = 4;
|
734 |
|
|
|
735 |
|
|
localparam [15:0] EOF1_THRESHOLD = (50 * CLKS_PER_BIT); // EOF1 + some margin
|
736 |
|
|
localparam [15:0] MAX_XFER_SIZE = 64;
|
737 |
|
|
localparam [15:0] MAX_XFER_PERIOD = ((MAX_XFER_SIZE + 6) * 10 * CLKS_PER_BIT); // Max packet transfer time (+ margin)
|
738 |
|
|
localparam [15:0] SOF_GAURD_LOW = (20 * CLKS_PER_BIT);
|
739 |
|
|
localparam [15:0] SOF_GAURD_HIGH = SOF_THRESHOLD - EOF1_THRESHOLD - MAX_XFER_PERIOD;
|
740 |
|
|
|
741 |
|
|
localparam PID_SOF = 8'hA5;
|
742 |
|
|
|
743 |
|
|
//-----------------------------------------------------------------
|
744 |
|
|
// SIE
|
745 |
|
|
//-----------------------------------------------------------------
|
746 |
|
|
usbh_sie
|
747 |
|
|
u_sie
|
748 |
|
|
(
|
749 |
|
|
// Clock & reset
|
750 |
|
|
.clk_i(clk_i),
|
751 |
|
|
.rst_i(rst_i),
|
752 |
|
|
|
753 |
|
|
// Control
|
754 |
|
|
.start_i(transfer_start_q),
|
755 |
|
|
.in_transfer_i(in_transfer_q),
|
756 |
|
|
.sof_transfer_i(sof_transfer_q),
|
757 |
|
|
.resp_expected_i(resp_expected_q),
|
758 |
|
|
.ack_o(transfer_ack_w),
|
759 |
|
|
|
760 |
|
|
// Token packet
|
761 |
|
|
.token_pid_i(token_pid_w),
|
762 |
|
|
.token_dev_i(token_dev_w),
|
763 |
|
|
.token_ep_i(token_ep_w),
|
764 |
|
|
|
765 |
|
|
// Data packet
|
766 |
|
|
.data_len_i(usb_xfer_data_tx_len_out_w),
|
767 |
|
|
.data_idx_i(usb_xfer_token_pid_datax_out_w),
|
768 |
|
|
|
769 |
|
|
// Tx Data FIFO
|
770 |
|
|
.tx_data_i(fifo_tx_data_w),
|
771 |
|
|
.tx_pop_o(fifo_tx_pop_w),
|
772 |
|
|
|
773 |
|
|
// Rx Data FIFO
|
774 |
|
|
.rx_data_o(fifo_rx_data_w),
|
775 |
|
|
.rx_push_o(fifo_rx_push_w),
|
776 |
|
|
|
777 |
|
|
// Status
|
778 |
|
|
.rx_done_o(status_rx_done_w),
|
779 |
|
|
.tx_done_o(status_tx_done_w),
|
780 |
|
|
.crc_err_o(status_crc_err_w),
|
781 |
|
|
.timeout_o(status_timeout_w),
|
782 |
|
|
.response_o(status_response_w),
|
783 |
|
|
.rx_count_o(status_rx_count_w),
|
784 |
|
|
.idle_o(status_sie_idle_w),
|
785 |
|
|
|
786 |
|
|
// UTMI Interface
|
787 |
|
|
.utmi_data_o(utmi_data_out_o),
|
788 |
|
|
.utmi_txvalid_o(utmi_txvalid_o),
|
789 |
|
|
.utmi_txready_i(utmi_txready_i),
|
790 |
|
|
.utmi_data_i(utmi_data_in_i),
|
791 |
|
|
.utmi_rxvalid_i(utmi_rxvalid_i),
|
792 |
|
|
.utmi_rxactive_i(utmi_rxactive_i)
|
793 |
|
|
);
|
794 |
|
|
|
795 |
|
|
//-----------------------------------------------------------------
|
796 |
|
|
// Peripheral Interface
|
797 |
|
|
//-----------------------------------------------------------------
|
798 |
|
|
assign usb_status_sof_time_in_w = sof_time_q;
|
799 |
|
|
assign usb_status_rx_error_in_w = usb_err_q;
|
800 |
|
|
assign usb_status_linestate_bits_in_w = utmi_linestate_i;
|
801 |
|
|
|
802 |
|
|
assign usb_irq_sts_err_in_w = intr_err_q;
|
803 |
|
|
assign usb_irq_sts_done_in_w = intr_done_q;
|
804 |
|
|
assign usb_irq_sts_sof_in_w = intr_sof_q;
|
805 |
|
|
|
806 |
|
|
assign usb_rx_stat_start_pend_in_w = usb_xfer_token_start_out_w;
|
807 |
|
|
assign usb_rx_stat_crc_err_in_w = status_crc_err_w;
|
808 |
|
|
assign usb_rx_stat_resp_timeout_in_w = status_timeout_w;
|
809 |
|
|
assign usb_rx_stat_idle_in_w = status_sie_idle_w;
|
810 |
|
|
assign usb_rx_stat_resp_bits_in_w = status_response_w;
|
811 |
|
|
assign usb_rx_stat_count_bits_in_w = status_rx_count_w;
|
812 |
|
|
|
813 |
|
|
assign usb_xfer_token_start_ack_in_w = transfer_req_ack_q;
|
814 |
|
|
|
815 |
|
|
assign utmi_op_mode_o = usb_ctrl_phy_opmode_out_w;
|
816 |
|
|
assign utmi_xcvrselect_o = usb_ctrl_phy_xcvrselect_out_w;
|
817 |
|
|
assign utmi_termselect_o = usb_ctrl_phy_termselect_out_w;
|
818 |
|
|
assign utmi_dppulldown_o = usb_ctrl_phy_dppulldown_out_w;
|
819 |
|
|
assign utmi_dmpulldown_o = usb_ctrl_phy_dmpulldown_out_w;
|
820 |
|
|
|
821 |
|
|
//-----------------------------------------------------------------
|
822 |
|
|
// Tx FIFO (Host -> Device)
|
823 |
|
|
//-----------------------------------------------------------------
|
824 |
|
|
usbh_fifo
|
825 |
|
|
u_fifo_tx
|
826 |
|
|
(
|
827 |
|
|
.clk_i(clk_i),
|
828 |
|
|
.rst_i(rst_i),
|
829 |
|
|
|
830 |
|
|
.data_i(usb_wr_data_data_out_w),
|
831 |
|
|
.push_i(usb_wr_data_wr_req_w),
|
832 |
|
|
|
833 |
|
|
.flush_i(usb_ctrl_tx_flush_out_w),
|
834 |
|
|
|
835 |
|
|
.full_o(),
|
836 |
|
|
.empty_o(),
|
837 |
|
|
|
838 |
|
|
.data_o(fifo_tx_data_w),
|
839 |
|
|
.pop_i(fifo_tx_pop_w)
|
840 |
|
|
);
|
841 |
|
|
|
842 |
|
|
//-----------------------------------------------------------------
|
843 |
|
|
// Rx FIFO (Device -> Host)
|
844 |
|
|
//-----------------------------------------------------------------
|
845 |
|
|
usbh_fifo
|
846 |
|
|
u_fifo_rx
|
847 |
|
|
(
|
848 |
|
|
.clk_i(clk_i),
|
849 |
|
|
.rst_i(rst_i),
|
850 |
|
|
|
851 |
|
|
// Receive from UTMI interface
|
852 |
|
|
.data_i(fifo_rx_data_w),
|
853 |
|
|
.push_i(fifo_rx_push_w),
|
854 |
|
|
|
855 |
|
|
.flush_i(fifo_flush_q),
|
856 |
|
|
|
857 |
|
|
.full_o(),
|
858 |
|
|
.empty_o(),
|
859 |
|
|
|
860 |
|
|
.data_o(usb_rd_data_data_in_w),
|
861 |
|
|
.pop_i(usb_rd_data_rd_req_w)
|
862 |
|
|
);
|
863 |
|
|
|
864 |
|
|
//-----------------------------------------------------------------
|
865 |
|
|
// Assignments
|
866 |
|
|
//-----------------------------------------------------------------
|
867 |
|
|
assign send_sof_w = (sof_time_q == SOF_THRESHOLD && usb_ctrl_enable_sof_out_w) & status_sie_idle_w;
|
868 |
|
|
assign sof_gaurd_band_w = (sof_time_q <= SOF_GAURD_LOW || sof_time_q >= SOF_GAURD_HIGH);
|
869 |
|
|
assign clear_to_send_w = (~sof_gaurd_band_w | ~usb_ctrl_enable_sof_out_w) & status_sie_idle_w;
|
870 |
|
|
|
871 |
|
|
assign token_pid_w = sof_transfer_q ? PID_SOF : usb_xfer_token_pid_bits_out_w;
|
872 |
|
|
|
873 |
|
|
assign token_dev_w = sof_transfer_q ?
|
874 |
|
|
{sof_value_q[0], sof_value_q[1], sof_value_q[2],
|
875 |
|
|
sof_value_q[3], sof_value_q[4], sof_value_q[5], sof_value_q[6]} :
|
876 |
|
|
{usb_xfer_token_dev_addr_out_w[0], usb_xfer_token_dev_addr_out_w[1], usb_xfer_token_dev_addr_out_w[2], usb_xfer_token_dev_addr_out_w[3], usb_xfer_token_dev_addr_out_w[4], usb_xfer_token_dev_addr_out_w[5], usb_xfer_token_dev_addr_out_w[6]};
|
877 |
|
|
|
878 |
|
|
assign token_ep_w = sof_transfer_q ?
|
879 |
|
|
{sof_value_q[7], sof_value_q[8], sof_value_q[9], sof_value_q[10]} :
|
880 |
|
|
{usb_xfer_token_ep_addr_out_w[0], usb_xfer_token_ep_addr_out_w[1], usb_xfer_token_ep_addr_out_w[2], usb_xfer_token_ep_addr_out_w[3]};
|
881 |
|
|
|
882 |
|
|
//-----------------------------------------------------------------
|
883 |
|
|
// Control logic
|
884 |
|
|
//-----------------------------------------------------------------
|
885 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
886 |
|
|
if (rst_i)
|
887 |
|
|
begin
|
888 |
|
|
fifo_flush_q <= 1'b0;
|
889 |
|
|
transfer_start_q <= 1'b0;
|
890 |
|
|
sof_transfer_q <= 1'b0;
|
891 |
|
|
transfer_req_ack_q <= 1'b0;
|
892 |
|
|
in_transfer_q <= 1'b0;
|
893 |
|
|
resp_expected_q <= 1'b0;
|
894 |
|
|
end
|
895 |
|
|
else
|
896 |
|
|
begin
|
897 |
|
|
// Transfer in progress?
|
898 |
|
|
if (transfer_start_q)
|
899 |
|
|
begin
|
900 |
|
|
// Transfer accepted
|
901 |
|
|
if (transfer_ack_w)
|
902 |
|
|
transfer_start_q <= 1'b0;
|
903 |
|
|
|
904 |
|
|
fifo_flush_q <= 1'b0;
|
905 |
|
|
transfer_req_ack_q <= 1'b0;
|
906 |
|
|
end
|
907 |
|
|
// Time to send another SOF token?
|
908 |
|
|
else if (send_sof_w)
|
909 |
|
|
begin
|
910 |
|
|
// Start transfer
|
911 |
|
|
in_transfer_q <= 1'b0;
|
912 |
|
|
resp_expected_q <= 1'b0;
|
913 |
|
|
transfer_start_q <= 1'b1;
|
914 |
|
|
sof_transfer_q <= 1'b1;
|
915 |
|
|
end
|
916 |
|
|
// Not in SOF gaurd band region or SOF disabled?
|
917 |
|
|
else if (clear_to_send_w)
|
918 |
|
|
begin
|
919 |
|
|
// Transfer request
|
920 |
|
|
if (usb_xfer_token_start_out_w)
|
921 |
|
|
begin
|
922 |
|
|
// Flush un-used previous Rx data
|
923 |
|
|
fifo_flush_q <= 1'b1;
|
924 |
|
|
|
925 |
|
|
// Start transfer
|
926 |
|
|
in_transfer_q <= usb_xfer_token_in_out_w;
|
927 |
|
|
resp_expected_q <= usb_xfer_token_ack_out_w;
|
928 |
|
|
transfer_start_q <= 1'b1;
|
929 |
|
|
sof_transfer_q <= 1'b0;
|
930 |
|
|
transfer_req_ack_q <= 1'b1;
|
931 |
|
|
end
|
932 |
|
|
end
|
933 |
|
|
end
|
934 |
|
|
|
935 |
|
|
//-----------------------------------------------------------------
|
936 |
|
|
// SOF Frame Number
|
937 |
|
|
//-----------------------------------------------------------------
|
938 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
939 |
|
|
if (rst_i)
|
940 |
|
|
begin
|
941 |
|
|
sof_value_q <= 11'd0;
|
942 |
|
|
sof_time_q <= SOF_ZERO;
|
943 |
|
|
sof_irq_q <= 1'b0;
|
944 |
|
|
end
|
945 |
|
|
// Time to send another SOF token?
|
946 |
|
|
else if (send_sof_w)
|
947 |
|
|
begin
|
948 |
|
|
sof_time_q <= SOF_ZERO;
|
949 |
|
|
sof_value_q <= sof_value_q + 11'd1;
|
950 |
|
|
|
951 |
|
|
// Start of frame interrupt
|
952 |
|
|
sof_irq_q <= 1'b1;
|
953 |
|
|
end
|
954 |
|
|
else
|
955 |
|
|
begin
|
956 |
|
|
// Increment the SOF timer
|
957 |
|
|
if (sof_time_q != SOF_THRESHOLD)
|
958 |
|
|
sof_time_q <= sof_time_q + SOF_INC;
|
959 |
|
|
|
960 |
|
|
sof_irq_q <= 1'b0;
|
961 |
|
|
end
|
962 |
|
|
|
963 |
|
|
//-----------------------------------------------------------------
|
964 |
|
|
// Record Errors
|
965 |
|
|
//-----------------------------------------------------------------
|
966 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
967 |
|
|
if (rst_i)
|
968 |
|
|
usb_err_q <= 1'b0;
|
969 |
|
|
// Clear error
|
970 |
|
|
else if (usb_ctrl_wr_q)
|
971 |
|
|
usb_err_q <= 1'b0;
|
972 |
|
|
// Record bus errors
|
973 |
|
|
else if (utmi_rxerror_i)
|
974 |
|
|
usb_err_q <= 1'b1;
|
975 |
|
|
|
976 |
|
|
//-----------------------------------------------------------------
|
977 |
|
|
// Interrupts
|
978 |
|
|
//-----------------------------------------------------------------
|
979 |
|
|
reg err_cond_q;
|
980 |
|
|
reg intr_q;
|
981 |
|
|
reg device_det_q;
|
982 |
|
|
|
983 |
|
|
always @ (posedge clk_i or posedge rst_i)
|
984 |
|
|
if (rst_i)
|
985 |
|
|
begin
|
986 |
|
|
intr_done_q <= 1'b0;
|
987 |
|
|
intr_sof_q <= 1'b0;
|
988 |
|
|
intr_err_q <= 1'b0;
|
989 |
|
|
err_cond_q <= 1'b0;
|
990 |
|
|
device_det_q <= 1'b0;
|
991 |
|
|
intr_q <= 1'b0;
|
992 |
|
|
end
|
993 |
|
|
else
|
994 |
|
|
begin
|
995 |
|
|
if (status_rx_done_w || status_tx_done_w)
|
996 |
|
|
intr_done_q <= 1'b1;
|
997 |
|
|
else if (usb_irq_ack_done_out_w)
|
998 |
|
|
intr_done_q <= 1'b0;
|
999 |
|
|
|
1000 |
|
|
if (sof_irq_q)
|
1001 |
|
|
intr_sof_q <= 1'b1;
|
1002 |
|
|
else if (usb_irq_ack_sof_out_w)
|
1003 |
|
|
intr_sof_q <= 1'b0;
|
1004 |
|
|
|
1005 |
|
|
if ((status_crc_err_w || status_timeout_w) && (!err_cond_q))
|
1006 |
|
|
intr_err_q <= 1'b1;
|
1007 |
|
|
else if (usb_irq_ack_err_out_w)
|
1008 |
|
|
intr_err_q <= 1'b0;
|
1009 |
|
|
|
1010 |
|
|
// Line state != SE0
|
1011 |
|
|
if (utmi_linestate_i != 2'b0)
|
1012 |
|
|
device_det_q <= 1'b1;
|
1013 |
|
|
else if (usb_irq_ack_device_detect_out_w)
|
1014 |
|
|
device_det_q <= 1'b0;
|
1015 |
|
|
|
1016 |
|
|
err_cond_q <= (status_crc_err_w | status_timeout_w);
|
1017 |
|
|
|
1018 |
|
|
intr_q <= (intr_done_q & usb_irq_mask_done_out_w) |
|
1019 |
|
|
(intr_err_q & usb_irq_mask_err_out_w) |
|
1020 |
|
|
(intr_sof_q & usb_irq_mask_sof_out_w) |
|
1021 |
|
|
(device_det_q & usb_irq_mask_device_detect_out_w);
|
1022 |
|
|
end
|
1023 |
|
|
|
1024 |
|
|
assign intr_o = intr_q;
|
1025 |
|
|
|
1026 |
|
|
|
1027 |
|
|
|
1028 |
|
|
endmodule
|