OpenCores
URL https://opencores.org/ocsvn/usb_nand_reader/usb_nand_reader/trunk

Subversion Repositories usb_nand_reader

[/] [usb_nand_reader/] [trunk/] [mini32/] [CMD_ChipEnable.asm] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 pradd
_cmd_chip_enable:
2
;CMD_ChipEnable.c,5 ::          void cmd_chip_enable(unsigned char* cmd)
3
ADDIU   SP, SP, -8
4
SW      RA, 0(SP)
5
;CMD_ChipEnable.c,7 ::          nand_chip_select((int)cmd[1]);
6
SW      R25, 4(SP)
7
ADDIU   R2, R25, 1
8
LBU     R2, 0(R2)
9
ANDI    R2, R2, 255
10
SEH     R25, R2
11
JAL     _nand_chip_select+0
12
NOP
13
;CMD_ChipEnable.c,8 ::          }
14
L_end_cmd_chip_enable:
15
LW      R25, 4(SP)
16
LW      RA, 0(SP)
17
ADDIU   SP, SP, 8
18
JR      RA
19
NOP
20
; end of _cmd_chip_enable
21
_cmd_chip_disable:
22
;CMD_ChipEnable.c,10 ::                 void cmd_chip_disable()
23
ADDIU   SP, SP, -4
24
SW      RA, 0(SP)
25
;CMD_ChipEnable.c,12 ::                 nand_chip_unselect();
26
JAL     _nand_chip_unselect+0
27
NOP
28
;CMD_ChipEnable.c,13 ::                 }
29
L_end_cmd_chip_disable:
30
LW      RA, 0(SP)
31
ADDIU   SP, SP, 4
32
JR      RA
33
NOP
34
; end of _cmd_chip_disable

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.