URL https://opencores.org/ocsvn/usb_phy/usb_phy/trunk

Subversion Repositories usb_phy

[/] [usb_phy/] [tags/] [start/] [rtl/] [verilog/] [usb_phy.v] - Blame information for rev 12

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  USB 1.1 PHY                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb_phy/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: usb_phy.v,v 1.1.1.1 2002-09-16 14:26:59 rudi Exp $
//
//  $Date: 2002-09-16 14:26:59 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
//
//
 
`include "timescale.v"
 
module usbf_phy(clk, rst, phy_tx_mode, usb_rst,
 
                // Transciever Interface
                txdp, txdn, txoe,
                rxd, rxdp, rxdn,
 
                // UTMI Interface
                DataOut_i, TxValid_i, TxReady_o, RxValid_o,
                RxActive_o, RxError_o, DataIn_o, LineState_o
                );
 
input           clk;
input           rst;
input           phy_tx_mode;
output          usb_rst;
output          txdp, txdn, txoe;
input           rxd, rxdp, rxdn;
input   [7:0]    DataOut_i;
input           TxValid_i;
output          TxReady_o;
output  [7:0]    DataIn_o;
output          RxValid_o;
output          RxActive_o;
output          RxError_o;
output  [1:0]    LineState_o;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
reg     [5:0]    rst_cnt;
reg             usb_rst;
wire            reset;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign reset = rst & ~usb_rst;
 
///////////////////////////////////////////////////////////////////
//
// TX Phy
//
 
usb_tx_phy i_tx_phy(
        .clk(           clk             ),
        .rst(           reset           ),
        .fs_ce(         fs_ce           ),
        .phy_mode(      phy_tx_mode     ),
 
        // Transciever Interface
        .txdp(          txdp            ),
        .txdn(          txdn            ),
        .txoe(          txoe            ),
 
        // UTMI Interface
        .DataOut_i(     DataOut_i       ),
        .TxValid_i(     TxValid_i       ),
        .TxReady_o(     TxReady_o       )
        );
 
///////////////////////////////////////////////////////////////////
//
// RX Phy and DPLL
//
 
usb_rx_phy i_rx_phy(
        .clk(           clk             ),
        .rst(           reset           ),
        .fs_ce(         fs_ce           ),
 
        // Transciever Interface
        .rxd(           rxd             ),
        .rxdp(          rxdp            ),
        .rxdn(          rxdn            ),
 
        // UTMI Interface
        .DataIn_o(      DataIn_o        ),
        .RxValid_o(     RxValid_o       ),
        .RxActive_o(    RxActive_o      ),
        .RxError_o(     RxError_o       ),
        .RxEn_i(        txoe            ),
        .LineState(     LineState_o     )
        );
 
///////////////////////////////////////////////////////////////////
//
// Generate an USB Reset is we see SE0 for at least 2.5uS
//
 
always @(posedge clk)
        if(!rst)                        rst_cnt <= #1 5'h0;
        else
        if(LineState_o != 2'h0)         rst_cnt <= #1 5'h0;
        else
        if(!usb_rst & fs_ce)            rst_cnt <= #1 rst_cnt + 5'h1;
 
always @(posedge clk)
        usb_rst <= #1 (rst_cnt == 5'd31);
 
endmodule
 

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// USB 1.1 PHY ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/usb_phy/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: usb_phy.v,v 1.1.1.1 2002-09-16 14:26:59 rudi Exp $`
42			`//`
43			`// $Date: 2002-09-16 14:26:59 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			`include "timescale.v"
60
61			`module usbf_phy(clk, rst, phy_tx_mode, usb_rst,`
62
63			`// Transciever Interface`
64			`txdp, txdn, txoe,`
65			`rxd, rxdp, rxdn,`
66
67			`// UTMI Interface`
68			`DataOut_i, TxValid_i, TxReady_o, RxValid_o,`
69			`RxActive_o, RxError_o, DataIn_o, LineState_o`
70			`);`
71
72			`input clk;`
73			`input rst;`
74			`input phy_tx_mode;`
75			`output usb_rst;`
76			`output txdp, txdn, txoe;`
77			`input rxd, rxdp, rxdn;`
78			`input [7:0] DataOut_i;`
79			`input TxValid_i;`
80			`output TxReady_o;`
81			`output [7:0] DataIn_o;`
82			`output RxValid_o;`
83			`output RxActive_o;`
84			`output RxError_o;`
85			`output [1:0] LineState_o;`
86
87			`///////////////////////////////////////////////////////////////////`
88			`//`
89			`// Local Wires and Registers`
90			`//`
91
92			`reg [5:0] rst_cnt;`
93			`reg usb_rst;`
94			`wire reset;`
95
96			`///////////////////////////////////////////////////////////////////`
97			`//`
98			`// Misc Logic`
99			`//`
100
101			`assign reset = rst & ~usb_rst;`
102
103			`///////////////////////////////////////////////////////////////////`
104			`//`
105			`// TX Phy`
106			`//`
107
108			`usb_tx_phy i_tx_phy(`
109			`.clk( clk ),`
110			`.rst( reset ),`
111			`.fs_ce( fs_ce ),`
112			`.phy_mode( phy_tx_mode ),`
113
114			`// Transciever Interface`
115			`.txdp( txdp ),`
116			`.txdn( txdn ),`
117			`.txoe( txoe ),`
118
119			`// UTMI Interface`
120			`.DataOut_i( DataOut_i ),`
121			`.TxValid_i( TxValid_i ),`
122			`.TxReady_o( TxReady_o )`
123			`);`
124
125			`///////////////////////////////////////////////////////////////////`
126			`//`
127			`// RX Phy and DPLL`
128			`//`
129
130			`usb_rx_phy i_rx_phy(`
131			`.clk( clk ),`
132			`.rst( reset ),`
133			`.fs_ce( fs_ce ),`
134
135			`// Transciever Interface`
136			`.rxd( rxd ),`
137			`.rxdp( rxdp ),`
138			`.rxdn( rxdn ),`
139
140			`// UTMI Interface`
141			`.DataIn_o( DataIn_o ),`
142			`.RxValid_o( RxValid_o ),`
143			`.RxActive_o( RxActive_o ),`
144			`.RxError_o( RxError_o ),`
145			`.RxEn_i( txoe ),`
146			`.LineState( LineState_o )`
147			`);`
148
149			`///////////////////////////////////////////////////////////////////`
150			`//`
151			`// Generate an USB Reset is we see SE0 for at least 2.5uS`
152			`//`
153
154			`always @(posedge clk)`
155			`if(!rst) rst_cnt <= #1 5'h0;`
156			`else`
157			`if(LineState_o != 2'h0) rst_cnt <= #1 5'h0;`
158			`else`
159			`if(!usb_rst & fs_ce) rst_cnt <= #1 rst_cnt + 5'h1;`
160
161			`always @(posedge clk)`
162			`usb_rst <= #1 (rst_cnt == 5'd31);`
163
164			`endmodule`
165

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[/] [usb_phy/] [tags/] [start/] [rtl/] [verilog/] [usb_phy.v] - Blame information for rev 12