URL https://opencores.org/ocsvn/usb_phy/usb_phy/trunk

Subversion Repositories usb_phy

[/] [usb_phy/] [trunk/] [rtl/] [verilog/] [usb_phy.v] - Blame information for rev 7

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  USB 1.1 PHY                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb_phy/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $
//
//  $Date: 2003-10-19 17:40:13 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/09/16 16:06:37  rudi
//               Changed top level name to be consistent ...
//
//               Revision 1.1.1.1  2002/09/16 14:26:59  rudi
//               Created Directory Structure
//
//
//
//
//
//
//
//
 
`include "timescale.v"
 
module usb_phy(clk, rst, phy_tx_mode, usb_rst,
 
                // Transciever Interface
                txdp, txdn, txoe,
                rxd, rxdp, rxdn,
 
                // UTMI Interface
                DataOut_i, TxValid_i, TxReady_o, RxValid_o,
                RxActive_o, RxError_o, DataIn_o, LineState_o
                );
 
input           clk;
input           rst;
input           phy_tx_mode;
output          usb_rst;
output          txdp, txdn, txoe;
input           rxd, rxdp, rxdn;
input   [7:0]    DataOut_i;
input           TxValid_i;
output          TxReady_o;
output  [7:0]    DataIn_o;
output          RxValid_o;
output          RxActive_o;
output          RxError_o;
output  [1:0]    LineState_o;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
reg     [4:0]    rst_cnt;
reg             usb_rst;
wire            reset;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign reset = rst & ~usb_rst;
 
///////////////////////////////////////////////////////////////////
//
// TX Phy
//
 
usb_tx_phy i_tx_phy(
        .clk(           clk             ),
        .rst(           reset           ),
        .fs_ce(         fs_ce           ),
        .phy_mode(      phy_tx_mode     ),
 
        // Transciever Interface
        .txdp(          txdp            ),
        .txdn(          txdn            ),
        .txoe(          txoe            ),
 
        // UTMI Interface
        .DataOut_i(     DataOut_i       ),
        .TxValid_i(     TxValid_i       ),
        .TxReady_o(     TxReady_o       )
        );
 
///////////////////////////////////////////////////////////////////
//
// RX Phy and DPLL
//
 
usb_rx_phy i_rx_phy(
        .clk(           clk             ),
        .rst(           reset           ),
        .fs_ce(         fs_ce           ),
 
        // Transciever Interface
        .rxd(           rxd             ),
        .rxdp(          rxdp            ),
        .rxdn(          rxdn            ),
 
        // UTMI Interface
        .DataIn_o(      DataIn_o        ),
        .RxValid_o(     RxValid_o       ),
        .RxActive_o(    RxActive_o      ),
        .RxError_o(     RxError_o       ),
        .RxEn_i(        txoe            ),
        .LineState(     LineState_o     )
        );
 
///////////////////////////////////////////////////////////////////
//
// Generate an USB Reset is we see SE0 for at least 2.5uS
//
 
always @(posedge clk)
        if(!rst)                        rst_cnt <= 5'h0;
        else
        if(LineState_o != 2'h0)         rst_cnt <= 5'h0;
        else
        if(!usb_rst && fs_ce)           rst_cnt <= rst_cnt + 5'h1;
 
always @(posedge clk)
        usb_rst <= (rst_cnt == 5'h1f);
 
endmodule
 

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// USB 1.1 PHY ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/usb_phy/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	7	rudi	`// $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $`
42	2	rudi	`//`
43	7	rudi	`// $Date: 2003-10-19 17:40:13 $`
44			`// $Revision: 1.3 $`
45	2	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	7	rudi	`// Revision 1.2 2002/09/16 16:06:37 rudi`
52			`// Changed top level name to be consistent ...`
53			`//`
54	4	rudi	`// Revision 1.1.1.1 2002/09/16 14:26:59 rudi`
55			`// Created Directory Structure`
56	2	rudi	`//`
57			`//`
58			`//`
59			`//`
60			`//`
61			`//`
62			`//`
63	4	rudi	`//`
64	2	rudi
65			`include "timescale.v"
66
67	4	rudi	`module usb_phy(clk, rst, phy_tx_mode, usb_rst,`
68	2	rudi
69			`// Transciever Interface`
70			`txdp, txdn, txoe,`
71			`rxd, rxdp, rxdn,`
72
73			`// UTMI Interface`
74			`DataOut_i, TxValid_i, TxReady_o, RxValid_o,`
75			`RxActive_o, RxError_o, DataIn_o, LineState_o`
76			`);`
77
78			`input clk;`
79			`input rst;`
80			`input phy_tx_mode;`
81			`output usb_rst;`
82			`output txdp, txdn, txoe;`
83			`input rxd, rxdp, rxdn;`
84			`input [7:0] DataOut_i;`
85			`input TxValid_i;`
86			`output TxReady_o;`
87			`output [7:0] DataIn_o;`
88			`output RxValid_o;`
89			`output RxActive_o;`
90			`output RxError_o;`
91			`output [1:0] LineState_o;`
92
93			`///////////////////////////////////////////////////////////////////`
94			`//`
95			`// Local Wires and Registers`
96			`//`
97
98	7	rudi	`reg [4:0] rst_cnt;`
99	2	rudi	`reg usb_rst;`
100			`wire reset;`
101
102			`///////////////////////////////////////////////////////////////////`
103			`//`
104			`// Misc Logic`
105			`//`
106
107			`assign reset = rst & ~usb_rst;`
108
109			`///////////////////////////////////////////////////////////////////`
110			`//`
111			`// TX Phy`
112			`//`
113
114			`usb_tx_phy i_tx_phy(`
115			`.clk( clk ),`
116			`.rst( reset ),`
117			`.fs_ce( fs_ce ),`
118			`.phy_mode( phy_tx_mode ),`
119
120			`// Transciever Interface`
121			`.txdp( txdp ),`
122			`.txdn( txdn ),`
123			`.txoe( txoe ),`
124
125			`// UTMI Interface`
126			`.DataOut_i( DataOut_i ),`
127			`.TxValid_i( TxValid_i ),`
128			`.TxReady_o( TxReady_o )`
129			`);`
130
131			`///////////////////////////////////////////////////////////////////`
132			`//`
133			`// RX Phy and DPLL`
134			`//`
135
136			`usb_rx_phy i_rx_phy(`
137			`.clk( clk ),`
138			`.rst( reset ),`
139			`.fs_ce( fs_ce ),`
140
141			`// Transciever Interface`
142			`.rxd( rxd ),`
143			`.rxdp( rxdp ),`
144			`.rxdn( rxdn ),`
145
146			`// UTMI Interface`
147			`.DataIn_o( DataIn_o ),`
148			`.RxValid_o( RxValid_o ),`
149			`.RxActive_o( RxActive_o ),`
150			`.RxError_o( RxError_o ),`
151			`.RxEn_i( txoe ),`
152			`.LineState( LineState_o )`
153			`);`
154
155			`///////////////////////////////////////////////////////////////////`
156			`//`
157			`// Generate an USB Reset is we see SE0 for at least 2.5uS`
158			`//`
159
160			`always @(posedge clk)`
161	7	rudi	`if(!rst) rst_cnt <= 5'h0;`
162	2	rudi	`else`
163	7	rudi	`if(LineState_o != 2'h0) rst_cnt <= 5'h0;`
164	2	rudi	`else`
165	7	rudi	`if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1;`
166	2	rudi
167			`always @(posedge clk)`
168	7	rudi	`usb_rst <= (rst_cnt == 5'h1f);`
169	2	rudi
170			`endmodule`
171

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[/] [usb_phy/] [trunk/] [rtl/] [verilog/] [usb_phy.v] - Blame information for rev 7