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sfielding |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// fifoRTL.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
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//// No protection against over runs and under runs.
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//// User must check full and empty flags before accessing fifo
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: fifoRTL.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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`timescale 1ns / 1ps
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module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
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//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
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parameter FIFO_WIDTH = 8;
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parameter FIFO_DEPTH = 64;
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parameter ADDR_WIDTH = 6;
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input clk;
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input rst;
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input [FIFO_WIDTH-1:0] dataIn;
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output [FIFO_WIDTH-1:0] dataOut;
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input fifoWEn;
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input fifoREn;
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output fifoFull;
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output fifoEmpty;
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input forceEmpty;
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output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
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wire clk;
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wire rst;
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wire [FIFO_WIDTH-1:0] dataIn;
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reg [FIFO_WIDTH-1:0] dataOut;
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wire fifoWEn;
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wire fifoREn;
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reg fifoFull;
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reg fifoEmpty;
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wire forceEmpty;
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reg [15:0]numElementsInFifo;
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// local registers
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reg [ADDR_WIDTH-1:0]bufferInIndex;
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reg [ADDR_WIDTH-1:0]bufferOutIndex;
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reg [ADDR_WIDTH:0]bufferCnt;
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reg fifoREnDelayed;
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wire [FIFO_WIDTH-1:0] dataFromMem;
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always @(posedge clk)
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begin
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if (rst == 1'b1 || forceEmpty == 1'b1)
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begin
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bufferCnt <= 0;
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fifoFull <= 1'b0;
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fifoEmpty <= 1'b1;
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bufferInIndex <= 0;
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bufferOutIndex <= 0;
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fifoREnDelayed <= 1'b0;
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end
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else
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begin
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if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
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dataOut <= dataFromMem;
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end
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fifoREnDelayed <= fifoREn;
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if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
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bufferCnt <= bufferCnt + 1;
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bufferInIndex <= bufferInIndex + 1;
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end
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else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
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bufferCnt <= bufferCnt - 1;
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bufferOutIndex <= bufferOutIndex + 1;
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end
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else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
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bufferOutIndex <= bufferOutIndex + 1;
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bufferInIndex <= bufferInIndex + 1;
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end
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if (bufferCnt[ADDR_WIDTH] == 1'b1)
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fifoFull <= 1'b1;
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else
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fifoFull <= 1'b0;
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if (|bufferCnt == 1'b0)
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fifoEmpty <= 1'b1;
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else
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fifoEmpty <= 1'b0;
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end
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end
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//pad bufferCnt with leading zeroes
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always @(bufferCnt) begin
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numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
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end
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fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
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.addrIn(bufferInIndex),
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.addrOut(bufferOutIndex),
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.clk(clk),
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.dataIn(dataIn),
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.writeEn(fifoWEn),
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.readEn(fifoREn),
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.dataOut(dataFromMem));
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endmodule
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