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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_01_alpha/] [RTL/] [include/] [usbHostControl_h.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// usbHostControl_h.v                                           ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: usbHostControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
 
//HCRegIndices
`define TX_CONTROL_REG 4'h0
`define TX_TRANS_TYPE_REG 4'h1
`define TX_LINE_CONTROL_REG 4'h2
`define TX_SOF_ENABLE_REG 4'h3
`define TX_ADDR_REG 4'h4
`define TX_ENDP_REG 4'h5
`define FRAME_NUM_MSB_REG 4'h6
`define FRAME_NUM_LSB_REG 4'h7
`define INTERRUPT_STATUS_REG 4'h8
`define INTERRUPT_MASK_REG 4'h9
`define RX_STATUS_REG 4'ha
`define RX_PID_REG 4'hb
`define RX_ADDR_REG 4'hc
`define RX_ENDP_REG 4'hd
`define RX_CONNECT_STATE_REG 4'he
`define HCREG_BUFFER_LEN 4'hf
`define HCREG_MASK 4'hf
 
//TXControlRegIndices
`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2
 
//interruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2
`define SOF_SENT_BIT 3
 
//TXTransactionTypes
`define SETUP_TRANS 0
`define IN_TRANS 1
`define OUTDATA0_TRANS 2
`define OUTDATA1_TRANS 3
 
 //TXLineControlIndices
`define TX_LINE_STATE_LSBIT 0
`define TX_LINE_STATE_MSBIT 1
`define DIRECT_CONTROL_BIT 2
`define FULL_SPEED_LINE_POLARITY_BIT 3
`define FULL_SPEED_LINE_RATE_BIT 4
 
//TXSOFEnableIndices
`define SOF_EN_BIT 0
 
//SOFTimeConstants 
`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval
`define SOF_TX_MARGIN 2
 
//Host RXStatusRegIndices 
`define HC_CRC_ERROR_BIT 0
`define HC_BIT_STUFF_ERROR_BIT 1
`define HC_RX_OVERFLOW_BIT 2
`define HC_RX_TIME_OUT_BIT 3
`define HC_NAK_RXED_BIT 4
`define HC_STALL_RXED_BIT 5
`define HC_ACK_RXED_BIT 6
`define HC_DATA_SEQUENCE_BIT 7
 

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// usbHostControl_h.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Id: usbHostControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49			`//`
50
51
52			`//HCRegIndices`
53			`define TX_CONTROL_REG 4'h0
54			`define TX_TRANS_TYPE_REG 4'h1
55			`define TX_LINE_CONTROL_REG 4'h2
56			`define TX_SOF_ENABLE_REG 4'h3
57			`define TX_ADDR_REG 4'h4
58			`define TX_ENDP_REG 4'h5
59			`define FRAME_NUM_MSB_REG 4'h6
60			`define FRAME_NUM_LSB_REG 4'h7
61			`define INTERRUPT_STATUS_REG 4'h8
62			`define INTERRUPT_MASK_REG 4'h9
63			`define RX_STATUS_REG 4'ha
64			`define RX_PID_REG 4'hb
65			`define RX_ADDR_REG 4'hc
66			`define RX_ENDP_REG 4'hd
67			`define RX_CONNECT_STATE_REG 4'he
68			`define HCREG_BUFFER_LEN 4'hf
69			`define HCREG_MASK 4'hf
70
71			`//TXControlRegIndices`
72			`define TRANS_REQ_BIT 0
73			`define SOF_SYNC_BIT 1
74			`define PREAMBLE_ENABLE_BIT 2
75
76			`//interruptRegIndices`
77			`define TRANS_DONE_BIT 0
78			`define RESUME_INT_BIT 1
79			`define CONNECTION_EVENT_BIT 2
80			`define SOF_SENT_BIT 3
81
82			`//TXTransactionTypes`
83			`define SETUP_TRANS 0
84			`define IN_TRANS 1
85			`define OUTDATA0_TRANS 2
86			`define OUTDATA1_TRANS 3
87
88			`//TXLineControlIndices`
89			`define TX_LINE_STATE_LSBIT 0
90			`define TX_LINE_STATE_MSBIT 1
91			`define DIRECT_CONTROL_BIT 2
92			`define FULL_SPEED_LINE_POLARITY_BIT 3
93			`define FULL_SPEED_LINE_RATE_BIT 4
94
95			`//TXSOFEnableIndices`
96			`define SOF_EN_BIT 0
97
98			`//SOFTimeConstants`
99			`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
100			`define SOF_TX_MARGIN 2
101
102			`//Host RXStatusRegIndices`
103			`define HC_CRC_ERROR_BIT 0
104			`define HC_BIT_STUFF_ERROR_BIT 1
105			`define HC_RX_OVERFLOW_BIT 2
106			`define HC_RX_TIME_OUT_BIT 3
107			`define HC_NAK_RXED_BIT 4
108			`define HC_STALL_RXED_BIT 5
109			`define HC_ACK_RXED_BIT 6
110			`define HC_DATA_SEQUENCE_BIT 7
111

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_01_alpha/] [RTL/] [include/] [usbHostControl_h.v] - Blame information for rev 2