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[/] [usbhostslave/] [tags/] [rel_00_01_alpha/] [RTL/] [serialInterfaceEngine/] [writeUSBWireData.v] - Blame information for rev 43

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// writeUSBWireData.v                                           ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: writeUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
`define BUFFER_FULL  3'b100
 
module writeUSBWireData (
  TxBitsIn,
  TxBitsOut,
        TxDataOutTick,
  TxCtrlIn,
  TxCtrlOut,
  USBWireRdy,
  USBWireWEn,
  disableWireReadOut,
  fullSpeedRate,
  clk,
  rst,
  noActivityTimeOut );
 
input   [1:0] TxBitsIn;
input   TxCtrlIn;
input   USBWireWEn;
input   clk;
input   fullSpeedRate;
input   rst;
output  [1:0] TxBitsOut;
output TxDataOutTick;
output  TxCtrlOut;
output  USBWireRdy;
output  disableWireReadOut;
output noActivityTimeOut;
 
wire    [1:0] TxBitsIn;
reg     [1:0] TxBitsOut;
reg     TxDataOutTick;
wire    TxCtrlIn;
reg     TxCtrlOut;
reg     USBWireRdy;
wire    USBWireWEn;
wire    clk;
wire    fullSpeedRate;
wire    rst;
reg  disableWireReadOut;
reg noActivityTimeOut;
 
// local registers
reg  [2:0]buffer0;
reg  [2:0]buffer1;
reg  [2:0]buffer2;
reg  [2:0]buffer3;
reg  [2:0]bufferCnt;
reg  [1:0]bufferInIndex;
reg  [1:0]bufferOutIndex;
reg decBufferCnt;
reg  [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
reg [15:0] timeOutCnt;
 
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
 
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
 
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
 
// buffer control
always @(posedge clk)
begin
  if (rst == 1'b1)
  begin
    bufferCnt <= 3'b000;
        end
  else
  begin
    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
      bufferCnt <= bufferCnt + 1'b1;
    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
      bufferCnt <= bufferCnt - 1'b1;
  end
end
 
 
//buffer input state machine 
always @(posedge clk) begin
  if (rst == 1'b1) begin
                incBufferCnt <= 1'b0;
                bufferInIndex <= 2'b00;
                buffer0 <= 3'b000;
                buffer1 <= 3'b000;
                buffer2 <= 3'b000;
                buffer3 <= 3'b000;
                USBWireRdy <= 1'b0;
                bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
        end
  else begin
          case (bufferInStMachCurrState)
                `WAIT_BUFFER_NOT_FULL:
                begin
                          if (bufferCnt != `BUFFER_FULL)
                          begin
                                  bufferInStMachCurrState <= `WAIT_WRITE_REQ;
                                  USBWireRdy <= 1'b1;
                          end
                  end
                  `WAIT_WRITE_REQ:
                  begin
                          if (USBWireWEn == 1'b1)
                          begin
                                  incBufferCnt <= 1'b1;
                                  USBWireRdy <= 1'b0;
                                  bufferInIndex <= bufferInIndex + 1'b1;
                                  case (bufferInIndex)
                                          2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
                                          2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
                                          2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
                                          2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
                                  endcase
                                  bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
                          end
                  end
                  `CLR_INC_BUFFER_CNT:
                  begin
                          incBufferCnt <= 1'b0;
                          if (bufferCnt != (`BUFFER_FULL - 1'b1) )
                          begin
                                  bufferInStMachCurrState <= `WAIT_WRITE_REQ;
                                  USBWireRdy <= 1'b1;
                          end
        else begin
                      bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
        end
                  end
          endcase
  end
end
 
//increment counter used to generate USB bit rate
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    i <= 5'b00000;
    fullSpeedTick <= 1'b0;
    lowSpeedTick <= 1'b0;
  end
  else
  begin
    i <= i + 1'b1;
    if (i[1:0] == 2'b00)
      fullSpeedTick <= 1'b1;
    else
      fullSpeedTick <= 1'b0;
    if (i == 5'b00000)
      lowSpeedTick <= 1'b1;
    else
      lowSpeedTick <= 1'b0;
  end
end
 
//buffer output state machine
//After reset, waits for the output buffer to become full.
//Once the buffer is full then it is constantly emptied at either
//the full or low speed rate with no under run protection
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
                bufferOutIndex <= 2'b00;
                decBufferCnt <= 1'b0;
                TxBitsOut <= 2'b00;
                TxCtrlOut <= `TRI_STATE;
    TxDataOutTick <= 1'b0;
                bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
        end
  else
  begin
          case (bufferOutStMachCurrState)
                  `WAIT_BUFFER_FULL:
                  begin
                          if (bufferCnt == `BUFFER_FULL)
                                  bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
                  end
                  `WAIT_LINE_WRITE:
                  begin
                          if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
                          begin
          TxDataOutTick <= !TxDataOutTick;
                                  bufferOutStMachCurrState <= `LINE_WRITE;
                                  decBufferCnt <= 1'b1;
                                  bufferOutIndex <= bufferOutIndex + 1'b1;
                                  case (bufferOutIndex)
                                  2'b00 :
                                  begin
                                          TxBitsOut <= buffer0[2:1];
                                          TxCtrlOut <= buffer0[0];
                                  end
                                  2'b01 :
                                  begin
                                          TxBitsOut <= buffer1[2:1];
                                          TxCtrlOut <= buffer1[0];
                                  end
                                  2'b10 :
                                  begin
                                          TxBitsOut <= buffer2[2:1];
                                          TxCtrlOut <= buffer2[0];
                                  end
                                  2'b11 :
                                  begin
                                          TxBitsOut <= buffer3[2:1];
                                          TxCtrlOut <= buffer3[0];
                                  end
                                  endcase
                          end
                  end
                  `LINE_WRITE:
                  begin
                          decBufferCnt <= 1'b0;
                          bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
                  end
          endcase
  end
end
 
// control 'disableWireReadOut' 
always @(TxCtrlOut)
begin
        if (TxCtrlOut == `DRIVE)
                disableWireReadOut <= 1'b1;
        else
                disableWireReadOut <= 1'b0;
end
 
//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
always @(posedge clk) begin
  if (rst) begin
    timeOutCnt <= 16'h0000;
    noActivityTimeOut <= 1'b0;
  end
  else begin
    if (TxCtrlOut == `DRIVE)
      timeOutCnt <= 16'h0000;
    else
      timeOutCnt <= timeOutCnt + 1'b1;
    //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
    if (timeOutCnt == 16'h200)  //temporary fix
      noActivityTimeOut <= 1'b1;
    else
      noActivityTimeOut <= 1'b0;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_01_alpha/] [RTL/] [serialInterfaceEngine/] [writeUSBWireData.v] - Blame information for rev 43

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// writeUSBWireData.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Id: writeUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49			`//`
50
51			`timescale 1ns / 1ps
52			`include "usbSerialInterfaceEngine_h.v"
53
54			`define BUFFER_FULL 3'b100
55
56			`module writeUSBWireData (`
57			`TxBitsIn,`
58			`TxBitsOut,`
59			`TxDataOutTick,`
60			`TxCtrlIn,`
61			`TxCtrlOut,`
62			`USBWireRdy,`
63			`USBWireWEn,`
64			`disableWireReadOut,`
65			`fullSpeedRate,`
66			`clk,`
67			`rst,`
68			`noActivityTimeOut );`
69
70			`input [1:0] TxBitsIn;`
71			`input TxCtrlIn;`
72			`input USBWireWEn;`
73			`input clk;`
74			`input fullSpeedRate;`
75			`input rst;`
76			`output [1:0] TxBitsOut;`
77			`output TxDataOutTick;`
78			`output TxCtrlOut;`
79			`output USBWireRdy;`
80			`output disableWireReadOut;`
81			`output noActivityTimeOut;`
82
83			`wire [1:0] TxBitsIn;`
84			`reg [1:0] TxBitsOut;`
85			`reg TxDataOutTick;`
86			`wire TxCtrlIn;`
87			`reg TxCtrlOut;`
88			`reg USBWireRdy;`
89			`wire USBWireWEn;`
90			`wire clk;`
91			`wire fullSpeedRate;`
92			`wire rst;`
93			`reg disableWireReadOut;`
94			`reg noActivityTimeOut;`
95
96			`// local registers`
97			`reg [2:0]buffer0;`
98			`reg [2:0]buffer1;`
99			`reg [2:0]buffer2;`
100			`reg [2:0]buffer3;`
101			`reg [2:0]bufferCnt;`
102			`reg [1:0]bufferInIndex;`
103			`reg [1:0]bufferOutIndex;`
104			`reg decBufferCnt;`
105			`reg [4:0]i;`
106			`reg incBufferCnt;`
107			`reg fullSpeedTick;`
108			`reg lowSpeedTick;`
109			`reg [15:0] timeOutCnt;`
110
111			`// buffer in state machine state codes:`
112			`define WAIT_BUFFER_NOT_FULL 2'b00
113			`define WAIT_WRITE_REQ 2'b01
114			`define CLR_INC_BUFFER_CNT 2'b10
115
116			`// buffer output state machine state codes:`
117			`define WAIT_BUFFER_FULL 2'b00
118			`define WAIT_LINE_WRITE 2'b01
119			`define LINE_WRITE 2'b10
120
121			`reg [1:0] bufferInStMachCurrState;`
122			`reg [1:0] bufferOutStMachCurrState;`
123
124			`// buffer control`
125			`always @(posedge clk)`
126			`begin`
127			`if (rst == 1'b1)`
128			`begin`
129			`bufferCnt <= 3'b000;`
130			`end`
131			`else`
132			`begin`
133			`if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)`
134			`bufferCnt <= bufferCnt + 1'b1;`
135			`else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)`
136			`bufferCnt <= bufferCnt - 1'b1;`
137			`end`
138			`end`
139
140
141			`//buffer input state machine`
142			`always @(posedge clk) begin`
143			`if (rst == 1'b1) begin`
144			`incBufferCnt <= 1'b0;`
145			`bufferInIndex <= 2'b00;`
146			`buffer0 <= 3'b000;`
147			`buffer1 <= 3'b000;`
148			`buffer2 <= 3'b000;`
149			`buffer3 <= 3'b000;`
150			`USBWireRdy <= 1'b0;`
151			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
152			`end`
153			`else begin`
154			`case (bufferInStMachCurrState)`
155			`WAIT_BUFFER_NOT_FULL:
156			`begin`
157			if (bufferCnt != `BUFFER_FULL)
158			`begin`
159			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
160			`USBWireRdy <= 1'b1;`
161			`end`
162			`end`
163			`WAIT_WRITE_REQ:
164			`begin`
165			`if (USBWireWEn == 1'b1)`
166			`begin`
167			`incBufferCnt <= 1'b1;`
168			`USBWireRdy <= 1'b0;`
169			`bufferInIndex <= bufferInIndex + 1'b1;`
170			`case (bufferInIndex)`
171			`2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};`
172			`2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};`
173			`2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};`
174			`2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};`
175			`endcase`
176			bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
177			`end`
178			`end`
179			`CLR_INC_BUFFER_CNT:
180			`begin`
181			`incBufferCnt <= 1'b0;`
182			if (bufferCnt != (`BUFFER_FULL - 1'b1) )
183			`begin`
184			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
185			`USBWireRdy <= 1'b1;`
186			`end`
187			`else begin`
188			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
189			`end`
190			`end`
191			`endcase`
192			`end`
193			`end`
194
195			`//increment counter used to generate USB bit rate`
196			`always @(posedge clk) begin`
197			`if (rst == 1'b1)`
198			`begin`
199			`i <= 5'b00000;`
200			`fullSpeedTick <= 1'b0;`
201			`lowSpeedTick <= 1'b0;`
202			`end`
203			`else`
204			`begin`
205			`i <= i + 1'b1;`
206			`if (i[1:0] == 2'b00)`
207			`fullSpeedTick <= 1'b1;`
208			`else`
209			`fullSpeedTick <= 1'b0;`
210			`if (i == 5'b00000)`
211			`lowSpeedTick <= 1'b1;`
212			`else`
213			`lowSpeedTick <= 1'b0;`
214			`end`
215			`end`
216
217			`//buffer output state machine`
218			`//After reset, waits for the output buffer to become full.`
219			`//Once the buffer is full then it is constantly emptied at either`
220			`//the full or low speed rate with no under run protection`
221			`always @(posedge clk) begin`
222			`if (rst == 1'b1)`
223			`begin`
224			`bufferOutIndex <= 2'b00;`
225			`decBufferCnt <= 1'b0;`
226			`TxBitsOut <= 2'b00;`
227			TxCtrlOut <= `TRI_STATE;
228			`TxDataOutTick <= 1'b0;`
229			bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
230			`end`
231			`else`
232			`begin`
233			`case (bufferOutStMachCurrState)`
234			`WAIT_BUFFER_FULL:
235			`begin`
236			if (bufferCnt == `BUFFER_FULL)
237			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
238			`end`
239			`WAIT_LINE_WRITE:
240			`begin`
241			`if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) \|\| (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )`
242			`begin`
243			`TxDataOutTick <= !TxDataOutTick;`
244			bufferOutStMachCurrState <= `LINE_WRITE;
245			`decBufferCnt <= 1'b1;`
246			`bufferOutIndex <= bufferOutIndex + 1'b1;`
247			`case (bufferOutIndex)`
248			`2'b00 :`
249			`begin`
250			`TxBitsOut <= buffer0[2:1];`
251			`TxCtrlOut <= buffer0[0];`
252			`end`
253			`2'b01 :`
254			`begin`
255			`TxBitsOut <= buffer1[2:1];`
256			`TxCtrlOut <= buffer1[0];`
257			`end`
258			`2'b10 :`
259			`begin`
260			`TxBitsOut <= buffer2[2:1];`
261			`TxCtrlOut <= buffer2[0];`
262			`end`
263			`2'b11 :`
264			`begin`
265			`TxBitsOut <= buffer3[2:1];`
266			`TxCtrlOut <= buffer3[0];`
267			`end`
268			`endcase`
269			`end`
270			`end`
271			`LINE_WRITE:
272			`begin`
273			`decBufferCnt <= 1'b0;`
274			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
275			`end`
276			`endcase`
277			`end`
278			`end`
279
280			`// control 'disableWireReadOut'`
281			`always @(TxCtrlOut)`
282			`begin`
283			if (TxCtrlOut == `DRIVE)
284			`disableWireReadOut <= 1'b1;`
285			`else`
286			`disableWireReadOut <= 1'b0;`
287			`end`
288
289			`//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks`
290			`always @(posedge clk) begin`
291			`if (rst) begin`
292			`timeOutCnt <= 16'h0000;`
293			`noActivityTimeOut <= 1'b0;`
294			`end`
295			`else begin`
296			if (TxCtrlOut == `DRIVE)
297			`timeOutCnt <= 16'h0000;`
298			`else`
299			`timeOutCnt <= timeOutCnt + 1'b1;`
300			//if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
301			`if (timeOutCnt == 16'h200) //temporary fix`
302			`noActivityTimeOut <= 1'b1;`
303			`else`
304			`noActivityTimeOut <= 1'b0;`
305			`end`
306			`end`
307
308			`endmodule`