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[/] [usbhostslave/] [tags/] [rel_00_04_alpha/] [RTL/] [include/] [usbHostControl_h.v] - Blame information for rev 43

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//////////////////////////////////////////////////////////////////////
// usbHostControl_h.v                                          
// $Id: usbHostControl_h.v,v 1.3 2004-12-31 14:40:42 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
// Created
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostControl_h_vdefined
`else
`define usbHostControl_h_vdefined
 
//HCRegIndices
`define TX_CONTROL_REG 4'h0
`define TX_TRANS_TYPE_REG 4'h1
`define TX_LINE_CONTROL_REG 4'h2
`define TX_SOF_ENABLE_REG 4'h3
`define TX_ADDR_REG 4'h4
`define TX_ENDP_REG 4'h5
`define FRAME_NUM_MSB_REG 4'h6
`define FRAME_NUM_LSB_REG 4'h7
`define INTERRUPT_STATUS_REG 4'h8
`define INTERRUPT_MASK_REG 4'h9
`define RX_STATUS_REG 4'ha
`define RX_PID_REG 4'hb
`define RX_ADDR_REG 4'hc
`define RX_ENDP_REG 4'hd
`define RX_CONNECT_STATE_REG 4'he
`define HCREG_BUFFER_LEN 4'hf
`define HCREG_MASK 4'hf
 
//TXControlRegIndices
`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2
 
//interruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2
`define SOF_SENT_BIT 3
 
//TXTransactionTypes
`define SETUP_TRANS 0
`define IN_TRANS 1
`define OUTDATA0_TRANS 2
`define OUTDATA1_TRANS 3
 
 //TXLineControlIndices
`define TX_LINE_STATE_LSBIT 0
`define TX_LINE_STATE_MSBIT 1
`define DIRECT_CONTROL_BIT 2
`define FULL_SPEED_LINE_POLARITY_BIT 3
`define FULL_SPEED_LINE_RATE_BIT 4
 
//TXSOFEnableIndices
`define SOF_EN_BIT 0
 
//SOFTimeConstants 
//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval
`define SOF_TX_TIME 16'hbb80     //Correct SOF interval for 48MHz clock
//`define SOF_TX_MARGIN 2 
`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
 
//Host RXStatusRegIndices 
`define HC_CRC_ERROR_BIT 0
`define HC_BIT_STUFF_ERROR_BIT 1
`define HC_RX_OVERFLOW_BIT 2
`define HC_RX_TIME_OUT_BIT 3
`define HC_NAK_RXED_BIT 4
`define HC_STALL_RXED_BIT 5
`define HC_ACK_RXED_BIT 6
`define HC_DATA_SEQUENCE_BIT 7
 
`endif //usbHostControl_h_vdefined 

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2	5	sfielding	`// usbHostControl_h.v`
3	7	sfielding	`// $Id: usbHostControl_h.v,v 1.3 2004-12-31 14:40:42 sfielding Exp $`
4	2	sfielding	`//`
5			`// CVS Revision History`
6			`//`
7			`// $Log: not supported by cvs2svn $`
8	5	sfielding	`// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding`
9			`// Created`
10			`//////////////////////////////////////////////////////////////////////`
11	2	sfielding
12	5	sfielding	`ifdef usbHostControl_h_vdefined
13			`else
14			`define usbHostControl_h_vdefined
15	2	sfielding
16			`//HCRegIndices`
17			`define TX_CONTROL_REG 4'h0
18			`define TX_TRANS_TYPE_REG 4'h1
19			`define TX_LINE_CONTROL_REG 4'h2
20			`define TX_SOF_ENABLE_REG 4'h3
21			`define TX_ADDR_REG 4'h4
22			`define TX_ENDP_REG 4'h5
23			`define FRAME_NUM_MSB_REG 4'h6
24			`define FRAME_NUM_LSB_REG 4'h7
25			`define INTERRUPT_STATUS_REG 4'h8
26			`define INTERRUPT_MASK_REG 4'h9
27			`define RX_STATUS_REG 4'ha
28			`define RX_PID_REG 4'hb
29			`define RX_ADDR_REG 4'hc
30			`define RX_ENDP_REG 4'hd
31			`define RX_CONNECT_STATE_REG 4'he
32			`define HCREG_BUFFER_LEN 4'hf
33			`define HCREG_MASK 4'hf
34
35			`//TXControlRegIndices`
36			`define TRANS_REQ_BIT 0
37			`define SOF_SYNC_BIT 1
38			`define PREAMBLE_ENABLE_BIT 2
39
40			`//interruptRegIndices`
41			`define TRANS_DONE_BIT 0
42			`define RESUME_INT_BIT 1
43			`define CONNECTION_EVENT_BIT 2
44			`define SOF_SENT_BIT 3
45
46			`//TXTransactionTypes`
47			`define SETUP_TRANS 0
48			`define IN_TRANS 1
49			`define OUTDATA0_TRANS 2
50			`define OUTDATA1_TRANS 3
51
52			`//TXLineControlIndices`
53			`define TX_LINE_STATE_LSBIT 0
54			`define TX_LINE_STATE_MSBIT 1
55			`define DIRECT_CONTROL_BIT 2
56			`define FULL_SPEED_LINE_POLARITY_BIT 3
57			`define FULL_SPEED_LINE_RATE_BIT 4
58
59			`//TXSOFEnableIndices`
60			`define SOF_EN_BIT 0
61
62			`//SOFTimeConstants`
63	7	sfielding	//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
64			`define SOF_TX_TIME 16'hbb80 //Correct SOF interval for 48MHz clock
65			//`define SOF_TX_MARGIN 2
66			`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
67	2	sfielding
68			`//Host RXStatusRegIndices`
69			`define HC_CRC_ERROR_BIT 0
70			`define HC_BIT_STUFF_ERROR_BIT 1
71			`define HC_RX_OVERFLOW_BIT 2
72			`define HC_RX_TIME_OUT_BIT 3
73			`define HC_NAK_RXED_BIT 4
74			`define HC_STALL_RXED_BIT 5
75			`define HC_ACK_RXED_BIT 6
76			`define HC_DATA_SEQUENCE_BIT 7
77
78	7	sfielding	`endif //usbHostControl_h_vdefined

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[/] [usbhostslave/] [tags/] [rel_00_04_alpha/] [RTL/] [include/] [usbHostControl_h.v] - Blame information for rev 43