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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_04_alpha/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processTxByte.v
// Generated   : 08/29/04 21:36:09
// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processTxByte.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
input   [1:0] JBit;
input   [1:0] KBit;
input   [7:0] TxByteCtrlIn;
input   [7:0] TxByteIn;
input   USBWireGnt;
input   USBWireRdy;
input   clk;
input   processTxByteWEn;
input   rst;
output  USBWireCtrl;
output  [1:0] USBWireData;
output  USBWireReq;
output  USBWireWEn;
output  processTxByteRdy;
 
wire    [1:0] JBit;
wire    [1:0] KBit;
wire    [7:0] TxByteCtrlIn;
wire    [7:0] TxByteIn;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0] USBWireData, next_USBWireData;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
wire    clk;
reg     processTxByteRdy, next_processTxByteRdy;
wire    processTxByteWEn;
wire    rst;
 
// diagram signals declarations
reg  [1:0]TXLineState, next_TXLineState;
reg  [3:0]TXOneCount, next_TXOneCount;
reg  [7:0]TxByteCtrl, next_TxByteCtrl;
reg  [7:0]TxByte, next_TxByte;
reg  [3:0]i, next_i;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 4'b0000
`define PTBY_WAIT_EN 4'b0001
`define SEND_BYTE_UPDATE_BYTE 4'b0010
`define SEND_BYTE_WAIT_RDY 4'b0011
`define SEND_BYTE_CHK 4'b0100
`define SEND_BYTE_BIT_STUFF 4'b0101
`define SEND_BYTE_WAIT_RDY2 4'b0110
`define SEND_BYTE_CHK_FIN 4'b0111
`define PTBY_WAIT_GNT 4'b1000
`define STOP_SND_SE0_2 4'b1001
`define STOP_SND_SE0_1 4'b1010
`define STOP_CHK 4'b1011
`define STOP_SND_J 4'b1100
`define STOP_SND_IDLE 4'b1101
`define STOP_FIN 4'b1110
 
reg [3:0] CurrState_prcTxB;
reg [3:0] NextState_prcTxB;
 
 
//--------------------------------------------------------------------
// Machine: prcTxB
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (TxByteIn or TxByteCtrlIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
begin : prcTxB_NextState
        NextState_prcTxB <= CurrState_prcTxB;
        // Set default values for outputs and signals
        next_processTxByteRdy <= processTxByteRdy;
        next_USBWireData <= USBWireData;
        next_USBWireCtrl <= USBWireCtrl;
        next_USBWireReq <= USBWireReq;
        next_USBWireWEn <= USBWireWEn;
        next_i <= i;
        next_TxByte <= TxByte;
        next_TxByteCtrl <= TxByteCtrl;
        next_TXLineState <= TXLineState;
        next_TXOneCount <= TXOneCount;
        case (CurrState_prcTxB) // synopsys parallel_case full_case
                `START_PTBY:
                begin
                        next_processTxByteRdy <= 1'b0;
                        next_USBWireData <= 2'b00;
                        next_USBWireCtrl <= `TRI_STATE;
                        next_USBWireReq <= 1'b0;
                        next_USBWireWEn <= 1'b0;
                        next_i <= 4'h0;
                        next_TxByte <= 8'h00;
                        next_TxByteCtrl <= 8'h00;
                        next_TXLineState <= 2'b0;
                        next_TXOneCount <= 4'h0;
                        NextState_prcTxB <= `PTBY_WAIT_EN;
                end
                `PTBY_WAIT_EN:
                begin
                        next_processTxByteRdy <= 1'b1;
                        if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
                        begin
                                NextState_prcTxB <= `PTBY_WAIT_GNT;
                                next_processTxByteRdy <= 1'b0;
                                next_TxByte <= TxByteIn;
                                next_TxByteCtrl <= TxByteCtrlIn;
                                next_TXOneCount <= 1;
                                next_TXLineState <= JBit;
                                next_USBWireReq <= 1'b1;
                        end
                        else if (processTxByteWEn == 1'b1)
                        begin
                                NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
                                next_processTxByteRdy <= 1'b0;
                                next_TxByte <= TxByteIn;
                                next_TxByteCtrl <= TxByteCtrlIn;
                                next_i <= 4'h0;
                        end
                end
                `PTBY_WAIT_GNT:
                        if (USBWireGnt == 1'b1)
                        begin
                                NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
                                next_i <= 4'h0;
                        end
                `SEND_BYTE_UPDATE_BYTE:
                begin
                        next_i <= i + 1'b1;
                        next_TxByte <= {1'b0, TxByte[7:1] };
                        if (TxByte[0] == 1'b1)                      //If this bit is 1, then
                          next_TXOneCount <= TXOneCount + 1'b1;
                            //increment 'TXOneCount'
                        else                                        //else this is a zero bit
                        begin
                          next_TXOneCount <= 4'h1;
                            //reset 'TXOneCount'
                          if (TXLineState == JBit) next_TXLineState <= KBit;
                            //toggle the line state
                          else next_TXLineState <= JBit;
                        end
                        NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
                end
                `SEND_BYTE_WAIT_RDY:
                        if (USBWireRdy == 1'b1)
                        begin
                                NextState_prcTxB <= `SEND_BYTE_CHK;
                                next_USBWireWEn <= 1'b1;
                                next_USBWireData <= TXLineState;
                                next_USBWireCtrl <= `DRIVE;
                        end
                `SEND_BYTE_CHK:
                begin
                        next_USBWireWEn <= 1'b0;
                        if (TXOneCount == 4'h6)
                                NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
                        else if (i != 4'h8)
                                NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
                        else
                                NextState_prcTxB <= `STOP_CHK;
                end
                `SEND_BYTE_BIT_STUFF:
                begin
                        next_TXOneCount <= 4'h1;
                        //reset 'TXOneCount'
                        if (TXLineState == JBit) next_TXLineState <= KBit;
                        //toggle the line state
                        else next_TXLineState <= JBit;
                        NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
                end
                `SEND_BYTE_WAIT_RDY2:
                        if (USBWireRdy == 1'b1)
                        begin
                                NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
                                next_USBWireWEn <= 1'b1;
                                next_USBWireData <= TXLineState;
                                next_USBWireCtrl <= `DRIVE;
                        end
                `SEND_BYTE_CHK_FIN:
                begin
                        next_USBWireWEn <= 1'b0;
                        if (i == 4'h8)
                                NextState_prcTxB <= `STOP_CHK;
                        else
                                NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
                end
                `STOP_SND_SE0_2:
                begin
                        next_USBWireWEn <= 1'b0;
                        if (USBWireRdy == 1'b1)
                        begin
                                NextState_prcTxB <= `STOP_SND_J;
                                next_USBWireWEn <= 1'b1;
                                next_USBWireData <= `SE0;
                                next_USBWireCtrl <= `DRIVE;
                        end
                end
                `STOP_SND_SE0_1:
                        if (USBWireRdy == 1'b1)
                        begin
                                NextState_prcTxB <= `STOP_SND_SE0_2;
                                next_USBWireWEn <= 1'b1;
                                next_USBWireData <= `SE0;
                                next_USBWireCtrl <= `DRIVE;
                        end
                `STOP_CHK:
                        if (TxByteCtrl == `DATA_STOP)
                                NextState_prcTxB <= `STOP_SND_SE0_1;
                        else
                                NextState_prcTxB <= `PTBY_WAIT_EN;
                `STOP_SND_J:
                begin
                        next_USBWireWEn <= 1'b0;
                        if (USBWireRdy == 1'b1)
                        begin
                                NextState_prcTxB <= `STOP_SND_IDLE;
                                next_USBWireWEn <= 1'b1;
                                next_USBWireData <= JBit;
                                next_USBWireCtrl <= `DRIVE;
                        end
                end
                `STOP_SND_IDLE:
                begin
                        next_USBWireWEn <= 1'b0;
                        if (USBWireRdy == 1'b1)
                        begin
                                NextState_prcTxB <= `STOP_FIN;
                                next_USBWireWEn <= 1'b1;
                                next_USBWireData <= JBit;
                                next_USBWireCtrl <= `TRI_STATE;
                        end
                end
                `STOP_FIN:
                begin
                        next_USBWireWEn <= 1'b0;
                        next_USBWireReq <= 1'b0;
                        //release the wire
                        NextState_prcTxB <= `PTBY_WAIT_EN;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prcTxB_CurrentState
        if (rst)
                CurrState_prcTxB <= `START_PTBY;
        else
                CurrState_prcTxB <= NextState_prcTxB;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prcTxB_RegOutput
        if (rst)
        begin
                i <= 4'h0;
                TxByte <= 8'h00;
                TxByteCtrl <= 8'h00;
                TXLineState <= 2'b0;
                TXOneCount <= 4'h0;
                processTxByteRdy <= 1'b0;
                USBWireData <= 2'b00;
                USBWireCtrl <= `TRI_STATE;
                USBWireReq <= 1'b0;
                USBWireWEn <= 1'b0;
        end
        else
        begin
                i <= next_i;
                TxByte <= next_TxByte;
                TxByteCtrl <= next_TxByteCtrl;
                TXLineState <= next_TXLineState;
                TXOneCount <= next_TXOneCount;
                processTxByteRdy <= next_processTxByteRdy;
                USBWireData <= next_USBWireData;
                USBWireCtrl <= next_USBWireCtrl;
                USBWireReq <= next_USBWireReq;
                USBWireWEn <= next_USBWireWEn;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_04_alpha/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processTxByte.v`
11			`// Generated : 08/29/04 21:36:09`
12			`// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processTxByte.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbSerialInterfaceEngine_h.v"
23			`include "usbConstants_h.v"
24
25			`module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);`
26			`input [1:0] JBit;`
27			`input [1:0] KBit;`
28			`input [7:0] TxByteCtrlIn;`
29			`input [7:0] TxByteIn;`
30			`input USBWireGnt;`
31			`input USBWireRdy;`
32			`input clk;`
33			`input processTxByteWEn;`
34			`input rst;`
35			`output USBWireCtrl;`
36			`output [1:0] USBWireData;`
37			`output USBWireReq;`
38			`output USBWireWEn;`
39			`output processTxByteRdy;`
40
41			`wire [1:0] JBit;`
42			`wire [1:0] KBit;`
43			`wire [7:0] TxByteCtrlIn;`
44			`wire [7:0] TxByteIn;`
45			`reg USBWireCtrl, next_USBWireCtrl;`
46			`reg [1:0] USBWireData, next_USBWireData;`
47			`wire USBWireGnt;`
48			`wire USBWireRdy;`
49			`reg USBWireReq, next_USBWireReq;`
50			`reg USBWireWEn, next_USBWireWEn;`
51			`wire clk;`
52			`reg processTxByteRdy, next_processTxByteRdy;`
53			`wire processTxByteWEn;`
54			`wire rst;`
55
56			`// diagram signals declarations`
57			`reg [1:0]TXLineState, next_TXLineState;`
58			`reg [3:0]TXOneCount, next_TXOneCount;`
59			`reg [7:0]TxByteCtrl, next_TxByteCtrl;`
60			`reg [7:0]TxByte, next_TxByte;`
61			`reg [3:0]i, next_i;`
62
63			`// BINARY ENCODED state machine: prcTxB`
64			`// State codes definitions:`
65			`define START_PTBY 4'b0000
66			`define PTBY_WAIT_EN 4'b0001
67			`define SEND_BYTE_UPDATE_BYTE 4'b0010
68			`define SEND_BYTE_WAIT_RDY 4'b0011
69			`define SEND_BYTE_CHK 4'b0100
70			`define SEND_BYTE_BIT_STUFF 4'b0101
71			`define SEND_BYTE_WAIT_RDY2 4'b0110
72			`define SEND_BYTE_CHK_FIN 4'b0111
73			`define PTBY_WAIT_GNT 4'b1000
74			`define STOP_SND_SE0_2 4'b1001
75			`define STOP_SND_SE0_1 4'b1010
76			`define STOP_CHK 4'b1011
77			`define STOP_SND_J 4'b1100
78			`define STOP_SND_IDLE 4'b1101
79			`define STOP_FIN 4'b1110
80
81			`reg [3:0] CurrState_prcTxB;`
82			`reg [3:0] NextState_prcTxB;`
83
84
85			`//--------------------------------------------------------------------`
86			`// Machine: prcTxB`
87			`//--------------------------------------------------------------------`
88			`//----------------------------------`
89			`// NextState logic (combinatorial)`
90			`//----------------------------------`
91			`always @ (TxByteIn or TxByteCtrlIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)`
92			`begin : prcTxB_NextState`
93			`NextState_prcTxB <= CurrState_prcTxB;`
94			`// Set default values for outputs and signals`
95			`next_processTxByteRdy <= processTxByteRdy;`
96			`next_USBWireData <= USBWireData;`
97			`next_USBWireCtrl <= USBWireCtrl;`
98			`next_USBWireReq <= USBWireReq;`
99			`next_USBWireWEn <= USBWireWEn;`
100			`next_i <= i;`
101			`next_TxByte <= TxByte;`
102			`next_TxByteCtrl <= TxByteCtrl;`
103			`next_TXLineState <= TXLineState;`
104			`next_TXOneCount <= TXOneCount;`
105			`case (CurrState_prcTxB) // synopsys parallel_case full_case`
106			`START_PTBY:
107			`begin`
108			`next_processTxByteRdy <= 1'b0;`
109			`next_USBWireData <= 2'b00;`
110			next_USBWireCtrl <= `TRI_STATE;
111			`next_USBWireReq <= 1'b0;`
112			`next_USBWireWEn <= 1'b0;`
113			`next_i <= 4'h0;`
114			`next_TxByte <= 8'h00;`
115			`next_TxByteCtrl <= 8'h00;`
116			`next_TXLineState <= 2'b0;`
117			`next_TXOneCount <= 4'h0;`
118			NextState_prcTxB <= `PTBY_WAIT_EN;
119			`end`
120			`PTBY_WAIT_EN:
121			`begin`
122			`next_processTxByteRdy <= 1'b1;`
123			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
124			`begin`
125			NextState_prcTxB <= `PTBY_WAIT_GNT;
126			`next_processTxByteRdy <= 1'b0;`
127			`next_TxByte <= TxByteIn;`
128			`next_TxByteCtrl <= TxByteCtrlIn;`
129			`next_TXOneCount <= 1;`
130			`next_TXLineState <= JBit;`
131			`next_USBWireReq <= 1'b1;`
132			`end`
133			`else if (processTxByteWEn == 1'b1)`
134			`begin`
135			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
136			`next_processTxByteRdy <= 1'b0;`
137			`next_TxByte <= TxByteIn;`
138			`next_TxByteCtrl <= TxByteCtrlIn;`
139			`next_i <= 4'h0;`
140			`end`
141			`end`
142			`PTBY_WAIT_GNT:
143			`if (USBWireGnt == 1'b1)`
144			`begin`
145			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
146			`next_i <= 4'h0;`
147			`end`
148			`SEND_BYTE_UPDATE_BYTE:
149			`begin`
150			`next_i <= i + 1'b1;`
151			`next_TxByte <= {1'b0, TxByte[7:1] };`
152			`if (TxByte[0] == 1'b1) //If this bit is 1, then`
153			`next_TXOneCount <= TXOneCount + 1'b1;`
154			`//increment 'TXOneCount'`
155			`else //else this is a zero bit`
156			`begin`
157			`next_TXOneCount <= 4'h1;`
158			`//reset 'TXOneCount'`
159			`if (TXLineState == JBit) next_TXLineState <= KBit;`
160			`//toggle the line state`
161			`else next_TXLineState <= JBit;`
162			`end`
163			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
164			`end`
165			`SEND_BYTE_WAIT_RDY:
166			`if (USBWireRdy == 1'b1)`
167			`begin`
168			NextState_prcTxB <= `SEND_BYTE_CHK;
169			`next_USBWireWEn <= 1'b1;`
170			`next_USBWireData <= TXLineState;`
171			next_USBWireCtrl <= `DRIVE;
172			`end`
173			`SEND_BYTE_CHK:
174			`begin`
175			`next_USBWireWEn <= 1'b0;`
176			`if (TXOneCount == 4'h6)`
177			NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
178			`else if (i != 4'h8)`
179			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
180			`else`
181			NextState_prcTxB <= `STOP_CHK;
182			`end`
183			`SEND_BYTE_BIT_STUFF:
184			`begin`
185			`next_TXOneCount <= 4'h1;`
186			`//reset 'TXOneCount'`
187			`if (TXLineState == JBit) next_TXLineState <= KBit;`
188			`//toggle the line state`
189			`else next_TXLineState <= JBit;`
190			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
191			`end`
192			`SEND_BYTE_WAIT_RDY2:
193			`if (USBWireRdy == 1'b1)`
194			`begin`
195			NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
196			`next_USBWireWEn <= 1'b1;`
197			`next_USBWireData <= TXLineState;`
198			next_USBWireCtrl <= `DRIVE;
199			`end`
200			`SEND_BYTE_CHK_FIN:
201			`begin`
202			`next_USBWireWEn <= 1'b0;`
203			`if (i == 4'h8)`
204			NextState_prcTxB <= `STOP_CHK;
205			`else`
206			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
207			`end`
208			`STOP_SND_SE0_2:
209			`begin`
210			`next_USBWireWEn <= 1'b0;`
211			`if (USBWireRdy == 1'b1)`
212			`begin`
213			NextState_prcTxB <= `STOP_SND_J;
214			`next_USBWireWEn <= 1'b1;`
215			next_USBWireData <= `SE0;
216			next_USBWireCtrl <= `DRIVE;
217			`end`
218			`end`
219			`STOP_SND_SE0_1:
220			`if (USBWireRdy == 1'b1)`
221			`begin`
222			NextState_prcTxB <= `STOP_SND_SE0_2;
223			`next_USBWireWEn <= 1'b1;`
224			next_USBWireData <= `SE0;
225			next_USBWireCtrl <= `DRIVE;
226			`end`
227			`STOP_CHK:
228			if (TxByteCtrl == `DATA_STOP)
229			NextState_prcTxB <= `STOP_SND_SE0_1;
230			`else`
231			NextState_prcTxB <= `PTBY_WAIT_EN;
232			`STOP_SND_J:
233			`begin`
234			`next_USBWireWEn <= 1'b0;`
235			`if (USBWireRdy == 1'b1)`
236			`begin`
237			NextState_prcTxB <= `STOP_SND_IDLE;
238			`next_USBWireWEn <= 1'b1;`
239			`next_USBWireData <= JBit;`
240			next_USBWireCtrl <= `DRIVE;
241			`end`
242			`end`
243			`STOP_SND_IDLE:
244			`begin`
245			`next_USBWireWEn <= 1'b0;`
246			`if (USBWireRdy == 1'b1)`
247			`begin`
248			NextState_prcTxB <= `STOP_FIN;
249			`next_USBWireWEn <= 1'b1;`
250			`next_USBWireData <= JBit;`
251			next_USBWireCtrl <= `TRI_STATE;
252			`end`
253			`end`
254			`STOP_FIN:
255			`begin`
256			`next_USBWireWEn <= 1'b0;`
257			`next_USBWireReq <= 1'b0;`
258			`//release the wire`
259			NextState_prcTxB <= `PTBY_WAIT_EN;
260			`end`
261			`endcase`
262			`end`
263
264			`//----------------------------------`
265			`// Current State Logic (sequential)`
266			`//----------------------------------`
267			`always @ (posedge clk)`
268			`begin : prcTxB_CurrentState`
269			`if (rst)`
270			CurrState_prcTxB <= `START_PTBY;
271			`else`
272			`CurrState_prcTxB <= NextState_prcTxB;`
273			`end`
274
275			`//----------------------------------`
276			`// Registered outputs logic`
277			`//----------------------------------`
278			`always @ (posedge clk)`
279			`begin : prcTxB_RegOutput`
280			`if (rst)`
281			`begin`
282			`i <= 4'h0;`
283			`TxByte <= 8'h00;`
284			`TxByteCtrl <= 8'h00;`
285			`TXLineState <= 2'b0;`
286			`TXOneCount <= 4'h0;`
287			`processTxByteRdy <= 1'b0;`
288			`USBWireData <= 2'b00;`
289			USBWireCtrl <= `TRI_STATE;
290			`USBWireReq <= 1'b0;`
291			`USBWireWEn <= 1'b0;`
292			`end`
293			`else`
294			`begin`
295			`i <= next_i;`
296			`TxByte <= next_TxByte;`
297			`TxByteCtrl <= next_TxByteCtrl;`
298			`TXLineState <= next_TXLineState;`
299			`TXOneCount <= next_TXOneCount;`
300			`processTxByteRdy <= next_processTxByteRdy;`
301			`USBWireData <= next_USBWireData;`
302			`USBWireCtrl <= next_USBWireCtrl;`
303			`USBWireReq <= next_USBWireReq;`
304			`USBWireWEn <= next_USBWireWEn;`
305			`end`
306			`end`
307
308			`endmodule`