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[/] [usbhostslave/] [tags/] [rel_00_04_alpha/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 40

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: slavecontroller.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbSlaveControl_h.v"
`include "usbConstants_h.v"
 
 
module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
input   bitStuffError;
input   clk;
input   CRCError;
input   getPacketRdy;
input   rst;
input   [7:0]RxByte;
input   RxDataWEn;
input   RxOverflow;
input   [7:0]RxStatus;
input   RxTimeOut;
input   SCGlobalEn;
input   sendPacketRdy;
input   [3:0]USBEndPControlReg;
input   [6:0]USBTgtAddress;
output  clrEPRdy;
output  endPMuxErrorsWEn;
output  [10:0]frameNum;
output  getPacketREn;
output  NAKSent;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  SOFRxed;
output  stallSent;
output  transDone;
output  [3:0]USBEndP;
output  [1:0]USBEndPNakTransTypeReg;
output  [1:0]USBEndPTransTypeReg;
 
wire    bitStuffError;
wire    clk;
reg     clrEPRdy, next_clrEPRdy;
wire    CRCError;
reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
reg     [10:0]frameNum, next_frameNum;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
reg     NAKSent, next_NAKSent;
wire    rst;
wire    [7:0]RxByte;
wire    RxDataWEn;
wire    RxOverflow;
wire    [7:0]RxStatus;
wire    RxTimeOut;
wire    SCGlobalEn;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     SOFRxed, next_SOFRxed;
reg     stallSent, next_stallSent;
reg     transDone, next_transDone;
reg     [3:0]USBEndP, next_USBEndP;
wire    [3:0]USBEndPControlReg;
reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
wire    [6:0]USBTgtAddress;
 
// diagram signals declarations
reg  [7:0]addrEndPTemp, next_addrEndPTemp;
reg  [7:0]endpCRCTemp, next_endpCRCTemp;
reg  [7:0]PIDByte, next_PIDByte;
reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
reg  [6:0]USBAddress, next_USBAddress;
 
// BINARY ENCODED state machine: slvCntrl
// State codes definitions:
`define WAIT_RX1 5'b00000
`define FIN_SC 5'b00001
`define GET_TOKEN_WAIT_CRC 5'b00010
`define GET_TOKEN_WAIT_ADDR 5'b00011
`define GET_TOKEN_WAIT_STOP 5'b00100
`define CHK_PID 5'b00101
`define GET_TOKEN_CHK_SOF 5'b00110
`define PID_ERROR 5'b00111
`define CHK_RDY 5'b01000
`define IN_NAK_STALL 5'b01001
`define IN_CHK_RDY 5'b01010
`define IN_DATA 5'b01011
`define IN_GET_RESP 5'b01100
`define SETUP_OUT_CHK 5'b01101
`define SETUP_OUT_SEND 5'b01110
`define SETUP_OUT_GET_PKT 5'b01111
`define START_S1 5'b10000
`define GET_TOKEN_DELAY 5'b10001
`define GET_TOKEN_CHK_ADDR 5'b10010
 
reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
 
 
// Machine: slvCntrl
 
// NextState logic (combinatorial)
always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
begin
  NextState_slvCntrl <= CurrState_slvCntrl;
  // Set default values for outputs and signals
  next_stallSent <= stallSent;
  next_NAKSent <= NAKSent;
  next_SOFRxed <= SOFRxed;
  next_PIDByte <= PIDByte;
  next_transDone <= transDone;
  next_clrEPRdy <= clrEPRdy;
  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
  next_endpCRCTemp <= endpCRCTemp;
  next_addrEndPTemp <= addrEndPTemp;
  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
  next_frameNum <= frameNum;
  next_USBAddress <= USBAddress;
  next_USBEndP <= USBEndP;
  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_getPacketREn <= getPacketREn;
  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
    `WAIT_RX1:
    begin
      next_stallSent <= 1'b0;
      next_NAKSent <= 1'b0;
      next_SOFRxed <= 1'b0;
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_START &&
        RxByte[1:0] == `TOKEN)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
        next_PIDByte <= RxByte;
      end
    end
    `FIN_SC:
    begin
      next_transDone <= 1'b0;
      next_clrEPRdy <= 1'b0;
      next_endPMuxErrorsWEn <= 1'b0;
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_PID:
    begin
      if (PIDByte[3:0] == `SETUP)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `OUT)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `IN)
      begin
        NextState_slvCntrl <= `IN_CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else
      begin
        NextState_slvCntrl <= `PID_ERROR;
      end
    end
    `PID_ERROR:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_RDY:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_transDone <= 1'b1;
        next_clrEPRdy <= 1'b1;
        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else if (NAKSent == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `FIN_SC;
      end
    end
    `SETUP_OUT_CHK:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `SETUP_OUT_SEND:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `SETUP_OUT_GET_PKT:
    begin
      next_getPacketREn <= 1'b0;
      if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
        bitStuffError == 1'b0 &&
        RxOverflow == 1'b0 &&
        RxTimeOut == 1'b0))
      begin
        NextState_slvCntrl <= `SETUP_OUT_CHK;
      end
      else if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_NAK_STALL:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_CHK_RDY:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else
      begin
        NextState_slvCntrl <= `IN_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `IN_DATA:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `IN_GET_RESP;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_GET_RESP:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `START_S1:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `GET_TOKEN_WAIT_CRC:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
        next_endpCRCTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_ADDR:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
        next_addrEndPTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_STOP:
    begin
      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
      end
      else if (RxDataWEn == 1'b1)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_CHK_SOF:
    begin
      if (PIDByte[3:0] == `SOF)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
        next_SOFRxed <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `GET_TOKEN_DELAY;
        next_USBAddress <= addrEndPTemp[6:0];
        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
      end
    end
    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndPControlReg to update
    begin
      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
    end
    `GET_TOKEN_CHK_ADDR:
    begin
      if (USBEndP < `NUM_OF_ENDPOINTS  &&
        USBAddress == USBTgtAddress &&
        SCGlobalEn == 1'b1 &&
        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_PID;
      end
      else
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvCntrl <= `START_S1;
  else
    CurrState_slvCntrl <= NextState_slvCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    stallSent <= 1'b0;
    NAKSent <= 1'b0;
    SOFRxed <= 1'b0;
    transDone <= 1'b0;
    clrEPRdy <= 1'b0;
    endPMuxErrorsWEn <= 1'b0;
    frameNum <= 11'b00000000000;
    USBEndP <= 4'h0;
    USBEndPTransTypeReg <= 2'b00;
    USBEndPNakTransTypeReg <= 2'b00;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
    getPacketREn <= 1'b0;
    PIDByte <= 8'h00;
    endpCRCTemp <= 8'h00;
    addrEndPTemp <= 8'h00;
    tempUSBEndPTransTypeReg <= 2'b00;
    USBAddress <= 7'b0000000;
  end
  else
  begin
    stallSent <= next_stallSent;
    NAKSent <= next_NAKSent;
    SOFRxed <= next_SOFRxed;
    transDone <= next_transDone;
    clrEPRdy <= next_clrEPRdy;
    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
    frameNum <= next_frameNum;
    USBEndP <= next_USBEndP;
    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
    getPacketREn <= next_getPacketREn;
    PIDByte <= next_PIDByte;
    endpCRCTemp <= next_endpCRCTemp;
    addrEndPTemp <= next_addrEndPTemp;
    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
    USBAddress <= next_USBAddress;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_04_alpha/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 40

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	7	sfielding	`// $Id: slavecontroller.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $`
46	5	sfielding	`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbSerialInterfaceEngine_h.v"
53			`include "usbSlaveControl_h.v"
54			`include "usbConstants_h.v"
55
56
57			`module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);`
58			`input bitStuffError;`
59			`input clk;`
60			`input CRCError;`
61			`input getPacketRdy;`
62			`input rst;`
63			`input [7:0]RxByte;`
64			`input RxDataWEn;`
65			`input RxOverflow;`
66			`input [7:0]RxStatus;`
67			`input RxTimeOut;`
68			`input SCGlobalEn;`
69			`input sendPacketRdy;`
70			`input [3:0]USBEndPControlReg;`
71			`input [6:0]USBTgtAddress;`
72			`output clrEPRdy;`
73			`output endPMuxErrorsWEn;`
74			`output [10:0]frameNum;`
75			`output getPacketREn;`
76			`output NAKSent;`
77			`output [3:0]sendPacketPID;`
78			`output sendPacketWEn;`
79			`output SOFRxed;`
80			`output stallSent;`
81			`output transDone;`
82			`output [3:0]USBEndP;`
83			`output [1:0]USBEndPNakTransTypeReg;`
84			`output [1:0]USBEndPTransTypeReg;`
85
86			`wire bitStuffError;`
87			`wire clk;`
88			`reg clrEPRdy, next_clrEPRdy;`
89			`wire CRCError;`
90			`reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;`
91			`reg [10:0]frameNum, next_frameNum;`
92			`wire getPacketRdy;`
93			`reg getPacketREn, next_getPacketREn;`
94			`reg NAKSent, next_NAKSent;`
95			`wire rst;`
96			`wire [7:0]RxByte;`
97			`wire RxDataWEn;`
98			`wire RxOverflow;`
99			`wire [7:0]RxStatus;`
100			`wire RxTimeOut;`
101			`wire SCGlobalEn;`
102			`reg [3:0]sendPacketPID, next_sendPacketPID;`
103			`wire sendPacketRdy;`
104			`reg sendPacketWEn, next_sendPacketWEn;`
105			`reg SOFRxed, next_SOFRxed;`
106			`reg stallSent, next_stallSent;`
107			`reg transDone, next_transDone;`
108			`reg [3:0]USBEndP, next_USBEndP;`
109			`wire [3:0]USBEndPControlReg;`
110			`reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;`
111			`reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;`
112			`wire [6:0]USBTgtAddress;`
113
114			`// diagram signals declarations`
115			`reg [7:0]addrEndPTemp, next_addrEndPTemp;`
116			`reg [7:0]endpCRCTemp, next_endpCRCTemp;`
117			`reg [7:0]PIDByte, next_PIDByte;`
118			`reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;`
119			`reg [6:0]USBAddress, next_USBAddress;`
120
121			`// BINARY ENCODED state machine: slvCntrl`
122			`// State codes definitions:`
123			`define WAIT_RX1 5'b00000
124			`define FIN_SC 5'b00001
125			`define GET_TOKEN_WAIT_CRC 5'b00010
126			`define GET_TOKEN_WAIT_ADDR 5'b00011
127			`define GET_TOKEN_WAIT_STOP 5'b00100
128			`define CHK_PID 5'b00101
129			`define GET_TOKEN_CHK_SOF 5'b00110
130			`define PID_ERROR 5'b00111
131			`define CHK_RDY 5'b01000
132			`define IN_NAK_STALL 5'b01001
133			`define IN_CHK_RDY 5'b01010
134			`define IN_DATA 5'b01011
135			`define IN_GET_RESP 5'b01100
136			`define SETUP_OUT_CHK 5'b01101
137			`define SETUP_OUT_SEND 5'b01110
138			`define SETUP_OUT_GET_PKT 5'b01111
139			`define START_S1 5'b10000
140			`define GET_TOKEN_DELAY 5'b10001
141			`define GET_TOKEN_CHK_ADDR 5'b10010
142
143			`reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;`
144
145
146			`// Machine: slvCntrl`
147
148			`// NextState logic (combinatorial)`
149			`always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)`
150			`begin`
151			`NextState_slvCntrl <= CurrState_slvCntrl;`
152			`// Set default values for outputs and signals`
153			`next_stallSent <= stallSent;`
154			`next_NAKSent <= NAKSent;`
155			`next_SOFRxed <= SOFRxed;`
156			`next_PIDByte <= PIDByte;`
157			`next_transDone <= transDone;`
158			`next_clrEPRdy <= clrEPRdy;`
159			`next_endPMuxErrorsWEn <= endPMuxErrorsWEn;`
160			`next_endpCRCTemp <= endpCRCTemp;`
161			`next_addrEndPTemp <= addrEndPTemp;`
162			`next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
163			`next_frameNum <= frameNum;`
164			`next_USBAddress <= USBAddress;`
165			`next_USBEndP <= USBEndP;`
166			`next_USBEndPTransTypeReg <= USBEndPTransTypeReg;`
167			`next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;`
168			`next_sendPacketWEn <= sendPacketWEn;`
169			`next_sendPacketPID <= sendPacketPID;`
170			`next_getPacketREn <= getPacketREn;`
171			`case (CurrState_slvCntrl) // synopsys parallel_case full_case`
172			`WAIT_RX1:
173			`begin`
174			`next_stallSent <= 1'b0;`
175			`next_NAKSent <= 1'b0;`
176			`next_SOFRxed <= 1'b0;`
177			`if (RxDataWEn == 1'b1 &&`
178			RxStatus == `RX_PACKET_START &&
179			RxByte[1:0] == `TOKEN)
180			`begin`
181			NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
182			`next_PIDByte <= RxByte;`
183			`end`
184			`end`
185			`FIN_SC:
186			`begin`
187			`next_transDone <= 1'b0;`
188			`next_clrEPRdy <= 1'b0;`
189			`next_endPMuxErrorsWEn <= 1'b0;`
190			NextState_slvCntrl <= `WAIT_RX1;
191			`end`
192			`CHK_PID:
193			`begin`
194			if (PIDByte[3:0] == `SETUP)
195			`begin`
196			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
197			next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
198			`next_getPacketREn <= 1'b1;`
199			`end`
200			else if (PIDByte[3:0] == `OUT)
201			`begin`
202			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
203			next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
204			`next_getPacketREn <= 1'b1;`
205			`end`
206			else if (PIDByte[3:0] == `IN)
207			`begin`
208			NextState_slvCntrl <= `IN_CHK_RDY;
209			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
210			`end`
211			`else`
212			`begin`
213			NextState_slvCntrl <= `PID_ERROR;
214			`end`
215			`end`
216			`PID_ERROR:
217			`begin`
218			NextState_slvCntrl <= `WAIT_RX1;
219			`end`
220			`CHK_RDY:
221			`begin`
222			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
223			`begin`
224			NextState_slvCntrl <= `FIN_SC;
225			`next_transDone <= 1'b1;`
226			`next_clrEPRdy <= 1'b1;`
227			`next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
228			`next_endPMuxErrorsWEn <= 1'b1;`
229			`end`
230			`else if (NAKSent == 1'b1)`
231			`begin`
232			NextState_slvCntrl <= `FIN_SC;
233			`next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;`
234			`next_endPMuxErrorsWEn <= 1'b1;`
235			`end`
236			`else`
237			`begin`
238			NextState_slvCntrl <= `FIN_SC;
239			`end`
240			`end`
241			`SETUP_OUT_CHK:
242			`begin`
243			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
244			`begin`
245			NextState_slvCntrl <= `SETUP_OUT_SEND;
246			`next_sendPacketWEn <= 1'b1;`
247			next_sendPacketPID <= `NAK;
248			`next_NAKSent <= 1'b1;`
249			`end`
250			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
251			`begin`
252			NextState_slvCntrl <= `SETUP_OUT_SEND;
253			`next_sendPacketWEn <= 1'b1;`
254			next_sendPacketPID <= `STALL;
255			`next_stallSent <= 1'b1;`
256			`end`
257			`else`
258			`begin`
259			NextState_slvCntrl <= `SETUP_OUT_SEND;
260			`next_sendPacketWEn <= 1'b1;`
261			next_sendPacketPID <= `ACK;
262			`end`
263			`end`
264			`SETUP_OUT_SEND:
265			`begin`
266			`next_sendPacketWEn <= 1'b0;`
267			`if (sendPacketRdy == 1'b1)`
268			`begin`
269			NextState_slvCntrl <= `CHK_RDY;
270			`end`
271			`end`
272			`SETUP_OUT_GET_PKT:
273			`begin`
274			`next_getPacketREn <= 1'b0;`
275			`if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&`
276			`bitStuffError == 1'b0 &&`
277			`RxOverflow == 1'b0 &&`
278			`RxTimeOut == 1'b0))`
279			`begin`
280			NextState_slvCntrl <= `SETUP_OUT_CHK;
281			`end`
282			`else if (getPacketRdy == 1'b1)`
283			`begin`
284			NextState_slvCntrl <= `CHK_RDY;
285			`end`
286			`end`
287			`IN_NAK_STALL:
288			`begin`
289			`next_sendPacketWEn <= 1'b0;`
290			`if (sendPacketRdy == 1'b1)`
291			`begin`
292			NextState_slvCntrl <= `CHK_RDY;
293			`end`
294			`end`
295			`IN_CHK_RDY:
296			`begin`
297			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
298			`begin`
299			NextState_slvCntrl <= `IN_NAK_STALL;
300			`next_sendPacketWEn <= 1'b1;`
301			next_sendPacketPID <= `NAK;
302			`next_NAKSent <= 1'b1;`
303			`end`
304			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
305			`begin`
306			NextState_slvCntrl <= `IN_NAK_STALL;
307			`next_sendPacketWEn <= 1'b1;`
308			next_sendPacketPID <= `STALL;
309			`next_stallSent <= 1'b1;`
310			`end`
311			else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
312			`begin`
313			NextState_slvCntrl <= `IN_DATA;
314			`next_sendPacketWEn <= 1'b1;`
315			next_sendPacketPID <= `DATA0;
316			`end`
317			`else`
318			`begin`
319			NextState_slvCntrl <= `IN_DATA;
320			`next_sendPacketWEn <= 1'b1;`
321			next_sendPacketPID <= `DATA1;
322			`end`
323			`end`
324			`IN_DATA:
325			`begin`
326			`next_sendPacketWEn <= 1'b0;`
327			`if (sendPacketRdy == 1'b1)`
328			`begin`
329			NextState_slvCntrl <= `IN_GET_RESP;
330			`next_getPacketREn <= 1'b1;`
331			`end`
332			`end`
333			`IN_GET_RESP:
334			`begin`
335			`next_getPacketREn <= 1'b0;`
336			`if (getPacketRdy == 1'b1)`
337			`begin`
338			NextState_slvCntrl <= `CHK_RDY;
339			`end`
340			`end`
341			`START_S1:
342			`begin`
343			NextState_slvCntrl <= `WAIT_RX1;
344			`end`
345			`GET_TOKEN_WAIT_CRC:
346			`begin`
347			`if (RxDataWEn == 1'b1 &&`
348			RxStatus == `RX_PACKET_STREAM)
349			`begin`
350			NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
351			`next_endpCRCTemp <= RxByte;`
352			`end`
353			`else if (RxDataWEn == 1'b1 &&`
354			RxStatus != `RX_PACKET_STREAM)
355			`begin`
356			NextState_slvCntrl <= `WAIT_RX1;
357			`end`
358			`end`
359			`GET_TOKEN_WAIT_ADDR:
360			`begin`
361			`if (RxDataWEn == 1'b1 &&`
362			RxStatus == `RX_PACKET_STREAM)
363			`begin`
364			NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
365			`next_addrEndPTemp <= RxByte;`
366			`end`
367			`else if (RxDataWEn == 1'b1 &&`
368			RxStatus != `RX_PACKET_STREAM)
369			`begin`
370			NextState_slvCntrl <= `WAIT_RX1;
371			`end`
372			`end`
373			`GET_TOKEN_WAIT_STOP:
374			`begin`
375			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
376			RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
377			RxByte [`RX_OVERFLOW_BIT] == 1'b0))
378			`begin`
379			NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
380			`end`
381			`else if (RxDataWEn == 1'b1)`
382			`begin`
383			NextState_slvCntrl <= `WAIT_RX1;
384			`end`
385			`end`
386			`GET_TOKEN_CHK_SOF:
387			`begin`
388			if (PIDByte[3:0] == `SOF)
389			`begin`
390			NextState_slvCntrl <= `WAIT_RX1;
391			`next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};`
392			`next_SOFRxed <= 1'b1;`
393			`end`
394			`else`
395			`begin`
396			NextState_slvCntrl <= `GET_TOKEN_DELAY;
397			`next_USBAddress <= addrEndPTemp[6:0];`
398			`next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};`
399			`end`
400			`end`
401			`GET_TOKEN_DELAY: // Insert delay to allow USBEndPControlReg to update
402			`begin`
403			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
404			`end`
405			`GET_TOKEN_CHK_ADDR:
406			`begin`
407			if (USBEndP < `NUM_OF_ENDPOINTS &&
408			`USBAddress == USBTgtAddress &&`
409			`SCGlobalEn == 1'b1 &&`
410			USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
411			`begin`
412			NextState_slvCntrl <= `CHK_PID;
413			`end`
414			`else`
415			`begin`
416			NextState_slvCntrl <= `WAIT_RX1;
417			`end`
418			`end`
419			`endcase`
420			`end`
421
422			`// Current State Logic (sequential)`
423			`always @ (posedge clk)`
424			`begin`
425			`if (rst)`
426			CurrState_slvCntrl <= `START_S1;
427			`else`
428			`CurrState_slvCntrl <= NextState_slvCntrl;`
429			`end`
430
431			`// Registered outputs logic`
432			`always @ (posedge clk)`
433			`begin`
434			`if (rst)`
435			`begin`
436			`stallSent <= 1'b0;`
437			`NAKSent <= 1'b0;`
438			`SOFRxed <= 1'b0;`
439			`transDone <= 1'b0;`
440			`clrEPRdy <= 1'b0;`
441			`endPMuxErrorsWEn <= 1'b0;`
442			`frameNum <= 11'b00000000000;`
443			`USBEndP <= 4'h0;`
444			`USBEndPTransTypeReg <= 2'b00;`
445			`USBEndPNakTransTypeReg <= 2'b00;`
446			`sendPacketWEn <= 1'b0;`
447			`sendPacketPID <= 4'b0;`
448			`getPacketREn <= 1'b0;`
449			`PIDByte <= 8'h00;`
450			`endpCRCTemp <= 8'h00;`
451			`addrEndPTemp <= 8'h00;`
452			`tempUSBEndPTransTypeReg <= 2'b00;`
453			`USBAddress <= 7'b0000000;`
454			`end`
455			`else`
456			`begin`
457			`stallSent <= next_stallSent;`
458			`NAKSent <= next_NAKSent;`
459			`SOFRxed <= next_SOFRxed;`
460			`transDone <= next_transDone;`
461			`clrEPRdy <= next_clrEPRdy;`
462			`endPMuxErrorsWEn <= next_endPMuxErrorsWEn;`
463			`frameNum <= next_frameNum;`
464			`USBEndP <= next_USBEndP;`
465			`USBEndPTransTypeReg <= next_USBEndPTransTypeReg;`
466			`USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;`
467			`sendPacketWEn <= next_sendPacketWEn;`
468			`sendPacketPID <= next_sendPacketPID;`
469			`getPacketREn <= next_getPacketREn;`
470			`PIDByte <= next_PIDByte;`
471			`endpCRCTemp <= next_endpCRCTemp;`
472			`addrEndPTemp <= next_addrEndPTemp;`
473			`tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;`
474			`USBAddress <= next_USBAddress;`
475			`end`
476			`end`
477
478	2	sfielding	`endmodule`