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[/] [usbhostslave/] [tags/] [rel_00_06_alpha/] [RTL/] [hostController/] [directcontrol.v] - Blame information for rev 13

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// directControl
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
input   clk;
input   directControlEn;
input   [1:0]directControlLineState;
input   HCTxPortGnt;
input   HCTxPortRdy;
input   rst;
output  [7:0]HCTxPortCntl;
output  [7:0]HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
 
wire    clk;
wire    directControlEn;
wire    [1:0]directControlLineState;
reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0]HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    rst;
 
// BINARY ENCODED state machine: drctCntl
// State codes definitions:
`define START_DC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
 
reg [2:0]CurrState_drctCntl, NextState_drctCntl;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: drctCntl
 
// NextState logic (combinatorial)
always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
begin
  NextState_drctCntl <= CurrState_drctCntl;
  // Set default values for outputs and signals
  next_HCTxPortCntl <= HCTxPortCntl;
  next_HCTxPortData <= HCTxPortData;
  next_HCTxPortWEn <= HCTxPortWEn;
  next_HCTxPortReq <= HCTxPortReq;
  case (CurrState_drctCntl)  // synopsys parallel_case full_case
    `START_DC:
    begin
      NextState_drctCntl <= `CHK_DRCT_CNTL;
    end
    `CHK_DRCT_CNTL:
    begin
      if (directControlEn == 1'b1)
      begin
        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
        next_HCTxPortReq <= 1'b1;
      end
      else
      begin
        NextState_drctCntl <= `IDLE_WAIT_GNT;
        next_HCTxPortReq <= 1'b1;
      end
    end
    `DRCT_CNTL_WAIT_GNT:
    begin
      if (HCTxPortGnt == 1'b1)
      begin
        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
      end
    end
    `DRCT_CNTL_CHK_LOOP:
    begin
      next_HCTxPortWEn <= 1'b0;
      if (directControlEn == 1'b0)
      begin
        NextState_drctCntl <= `CHK_DRCT_CNTL;
        next_HCTxPortReq <= 1'b0;
      end
      else
      begin
        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
      end
    end
    `DRCT_CNTL_WAIT_RDY:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {6'b000000, directControlLineState};
        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
      end
    end
    `IDLE_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      next_HCTxPortReq <= 1'b0;
      NextState_drctCntl <= `CHK_DRCT_CNTL;
    end
    `IDLE_WAIT_GNT:
    begin
      if (HCTxPortGnt == 1'b1)
      begin
        NextState_drctCntl <= `IDLE_WAIT_RDY;
      end
    end
    `IDLE_WAIT_RDY:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_drctCntl <= `IDLE_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_IDLE;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_drctCntl <= `START_DC;
  else
    CurrState_drctCntl <= NextState_drctCntl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    HCTxPortCntl <= 8'h00;
    HCTxPortData <= 8'h00;
    HCTxPortWEn <= 1'b0;
    HCTxPortReq <= 1'b0;
  end
  else
  begin
    HCTxPortCntl <= next_HCTxPortCntl;
    HCTxPortData <= next_HCTxPortData;
    HCTxPortWEn <= next_HCTxPortWEn;
    HCTxPortReq <= next_HCTxPortReq;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_06_alpha/] [RTL/] [hostController/] [directcontrol.v] - Blame information for rev 13

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// directControl`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47
48			`module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);`
49			`input clk;`
50			`input directControlEn;`
51			`input [1:0]directControlLineState;`
52			`input HCTxPortGnt;`
53			`input HCTxPortRdy;`
54			`input rst;`
55			`output [7:0]HCTxPortCntl;`
56			`output [7:0]HCTxPortData;`
57			`output HCTxPortReq;`
58			`output HCTxPortWEn;`
59
60			`wire clk;`
61			`wire directControlEn;`
62			`wire [1:0]directControlLineState;`
63			`reg [7:0]HCTxPortCntl, next_HCTxPortCntl;`
64			`reg [7:0]HCTxPortData, next_HCTxPortData;`
65			`wire HCTxPortGnt;`
66			`wire HCTxPortRdy;`
67			`reg HCTxPortReq, next_HCTxPortReq;`
68			`reg HCTxPortWEn, next_HCTxPortWEn;`
69			`wire rst;`
70
71			`// BINARY ENCODED state machine: drctCntl`
72			`// State codes definitions:`
73			`define START_DC 3'b000
74			`define CHK_DRCT_CNTL 3'b001
75			`define DRCT_CNTL_WAIT_GNT 3'b010
76			`define DRCT_CNTL_CHK_LOOP 3'b011
77			`define DRCT_CNTL_WAIT_RDY 3'b100
78			`define IDLE_FIN 3'b101
79			`define IDLE_WAIT_GNT 3'b110
80			`define IDLE_WAIT_RDY 3'b111
81
82			`reg [2:0]CurrState_drctCntl, NextState_drctCntl;`
83
84			`// Diagram actions (continuous assignments allowed only: assign ...)`
85			`// diagram ACTION`
86
87
88			`// Machine: drctCntl`
89
90			`// NextState logic (combinatorial)`
91			`always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)`
92			`begin`
93			`NextState_drctCntl <= CurrState_drctCntl;`
94			`// Set default values for outputs and signals`
95			`next_HCTxPortCntl <= HCTxPortCntl;`
96			`next_HCTxPortData <= HCTxPortData;`
97			`next_HCTxPortWEn <= HCTxPortWEn;`
98			`next_HCTxPortReq <= HCTxPortReq;`
99			`case (CurrState_drctCntl) // synopsys parallel_case full_case`
100			`START_DC:
101			`begin`
102			NextState_drctCntl <= `CHK_DRCT_CNTL;
103			`end`
104			`CHK_DRCT_CNTL:
105			`begin`
106			`if (directControlEn == 1'b1)`
107			`begin`
108			NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
109			`next_HCTxPortReq <= 1'b1;`
110			`end`
111			`else`
112			`begin`
113			NextState_drctCntl <= `IDLE_WAIT_GNT;
114			`next_HCTxPortReq <= 1'b1;`
115			`end`
116			`end`
117			`DRCT_CNTL_WAIT_GNT:
118			`begin`
119			`if (HCTxPortGnt == 1'b1)`
120			`begin`
121			NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
122			`end`
123			`end`
124			`DRCT_CNTL_CHK_LOOP:
125			`begin`
126			`next_HCTxPortWEn <= 1'b0;`
127			`if (directControlEn == 1'b0)`
128			`begin`
129			NextState_drctCntl <= `CHK_DRCT_CNTL;
130			`next_HCTxPortReq <= 1'b0;`
131			`end`
132			`else`
133			`begin`
134			NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
135			`end`
136			`end`
137			`DRCT_CNTL_WAIT_RDY:
138			`begin`
139			`if (HCTxPortRdy == 1'b1)`
140			`begin`
141			NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
142			`next_HCTxPortWEn <= 1'b1;`
143			`next_HCTxPortData <= {6'b000000, directControlLineState};`
144			next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
145			`end`
146			`end`
147			`IDLE_FIN:
148			`begin`
149			`next_HCTxPortWEn <= 1'b0;`
150			`next_HCTxPortReq <= 1'b0;`
151			NextState_drctCntl <= `CHK_DRCT_CNTL;
152			`end`
153			`IDLE_WAIT_GNT:
154			`begin`
155			`if (HCTxPortGnt == 1'b1)`
156			`begin`
157			NextState_drctCntl <= `IDLE_WAIT_RDY;
158			`end`
159			`end`
160			`IDLE_WAIT_RDY:
161			`begin`
162			`if (HCTxPortRdy == 1'b1)`
163			`begin`
164			NextState_drctCntl <= `IDLE_FIN;
165			`next_HCTxPortWEn <= 1'b1;`
166			`next_HCTxPortData <= 8'h00;`
167			next_HCTxPortCntl <= `TX_IDLE;
168			`end`
169			`end`
170			`endcase`
171			`end`
172
173			`// Current State Logic (sequential)`
174			`always @ (posedge clk)`
175			`begin`
176			`if (rst)`
177			CurrState_drctCntl <= `START_DC;
178			`else`
179			`CurrState_drctCntl <= NextState_drctCntl;`
180			`end`
181
182			`// Registered outputs logic`
183			`always @ (posedge clk)`
184			`begin`
185			`if (rst)`
186			`begin`
187			`HCTxPortCntl <= 8'h00;`
188			`HCTxPortData <= 8'h00;`
189			`HCTxPortWEn <= 1'b0;`
190			`HCTxPortReq <= 1'b0;`
191			`end`
192			`else`
193			`begin`
194			`HCTxPortCntl <= next_HCTxPortCntl;`
195			`HCTxPortData <= next_HCTxPortData;`
196			`HCTxPortWEn <= next_HCTxPortWEn;`
197			`HCTxPortReq <= next_HCTxPortReq;`
198			`end`
199			`end`
200
201	2	sfielding	`endmodule`