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[/] [usbhostslave/] [tags/] [rel_00_06_alpha/] [RTL/] [serialInterfaceEngine/] [processRxByte.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxByte.v
// Generated   : 09/13/04 06:05:00
// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxByte.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
input   [15:0] CRC16Result;
input   CRC16UpdateRdy;
input   [4:0] CRC5Result;
input   CRC5UpdateRdy;
input   [7:0] RxByteIn;
input   [7:0] RxCtrlIn;
input   clk;
input   processRxDataInWEn;
input   rst;
output  CRC16En;
output  CRC5En;
output  CRC5_8Bit;
output  [7:0] CRCData;
output  [7:0] RxCtrlOut;
output  RxDataOutWEn;
output  [7:0] RxDataOut;
output  processRxByteRdy;
output  rstCRC;
 
reg     CRC16En, next_CRC16En;
wire    [15:0] CRC16Result;
wire    CRC16UpdateRdy;
reg     CRC5En, next_CRC5En;
wire    [4:0] CRC5Result;
wire    CRC5UpdateRdy;
reg     CRC5_8Bit, next_CRC5_8Bit;
reg     [7:0] CRCData, next_CRCData;
wire    [7:0] RxByteIn;
wire    [7:0] RxCtrlIn;
reg     [7:0] RxCtrlOut, next_RxCtrlOut;
reg     RxDataOutWEn, next_RxDataOutWEn;
reg     [7:0] RxDataOut, next_RxDataOut;
wire    clk;
reg     processRxByteRdy, next_processRxByteRdy;
wire    processRxDataInWEn;
wire    rst;
reg     rstCRC, next_rstCRC;
 
// diagram signals declarations
reg ACKRxed, next_ACKRxed;
reg CRCError, next_CRCError;
reg NAKRxed, next_NAKRxed;
reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
reg  [7:0]RxByte, next_RxByte;
reg  [7:0]RxCtrl, next_RxCtrl;
reg RxOverflow, next_RxOverflow;
reg  [7:0]RxStatus;
reg RxTimeOut, next_RxTimeOut;
reg Signal1, next_Signal1;
reg bitStuffError, next_bitStuffError;
reg dataSequence, next_dataSequence;
reg stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: prRxByte
// State codes definitions:
`define CHK_ST 4'b0000
`define START_PRBY 4'b0001
`define WAIT_BYTE 4'b0010
`define IDLE_CHK_START 4'b0011
`define CHK_SYNC_DO 4'b0100
`define CHK_PID_DO_CHK 4'b0101
`define CHK_PID_FIRST_BYTE_PROC 4'b0110
`define HSHAKE_FIN 4'b0111
`define HSHAKE_CHK 4'b1000
`define TOKEN_CHK_STRM 4'b1001
`define TOKEN_FIN 4'b1010
`define DATA_FIN 4'b1011
`define DATA_CHK_STRM 4'b1100
`define TOKEN_WAIT_CRC 4'b1101
`define DATA_WAIT_CRC 4'b1110
 
reg [3:0] CurrState_prRxByte;
reg [3:0] NextState_prRxByte;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(next_CRCError or next_bitStuffError or
  next_RxOverflow or next_NAKRxed or
  next_stallRxed or next_ACKRxed or
  next_dataSequence)
begin
    RxStatus <=
    {1'b0, next_dataSequence,
    next_ACKRxed,
    next_stallRxed, next_NAKRxed,
    next_RxOverflow,
    next_bitStuffError, next_CRCError };
end
 
 
//--------------------------------------------------------------------
// Machine: prRxByte
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
begin : prRxByte_NextState
        NextState_prRxByte <= CurrState_prRxByte;
        // Set default values for outputs and signals
        next_RxByte <= RxByte;
        next_RxCtrl <= RxCtrl;
        next_RXByteStMachCurrState <= RXByteStMachCurrState;
        next_CRCError <= CRCError;
        next_bitStuffError <= bitStuffError;
        next_RxOverflow <= RxOverflow;
        next_RxTimeOut <= RxTimeOut;
        next_NAKRxed <= NAKRxed;
        next_stallRxed <= stallRxed;
        next_ACKRxed <= ACKRxed;
        next_dataSequence <= dataSequence;
        next_RxDataOut <= RxDataOut;
        next_RxCtrlOut <= RxCtrlOut;
        next_RxDataOutWEn <= RxDataOutWEn;
        next_rstCRC <= rstCRC;
        next_CRCData <= CRCData;
        next_CRC5En <= CRC5En;
        next_CRC5_8Bit <= CRC5_8Bit;
        next_CRC16En <= CRC16En;
        next_RXDataByteCnt <= RXDataByteCnt;
        next_processRxByteRdy <= processRxByteRdy;
        case (CurrState_prRxByte) // synopsys parallel_case full_case
                `CHK_ST:
                        if (RXByteStMachCurrState == `HS_BYTE_ST)
                                NextState_prRxByte <= `HSHAKE_CHK;
                        else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
                                NextState_prRxByte <= `TOKEN_WAIT_CRC;
                        else if (RXByteStMachCurrState == `DATA_BYTE_ST)
                                NextState_prRxByte <= `DATA_WAIT_CRC;
                        else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
                                NextState_prRxByte <= `IDLE_CHK_START;
                        else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
                                NextState_prRxByte <= `CHK_SYNC_DO;
                        else if (RXByteStMachCurrState == `CHECK_PID_ST)
                                NextState_prRxByte <= `CHK_PID_DO_CHK;
                `START_PRBY:
                begin
                        next_RxByte <= 8'h00;
                        next_RxCtrl <= 8'h00;
                        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                        next_CRCError <= 1'b0;
                        next_bitStuffError <= 1'b0;
                        next_RxOverflow <= 1'b0;
                        next_RxTimeOut <= 1'b0;
                        next_NAKRxed <= 1'b0;
                        next_stallRxed <= 1'b0;
                        next_ACKRxed <= 1'b0;
                        next_dataSequence <= 1'b0;
                        next_RxDataOut <= 8'h00;
                        next_RxCtrlOut <= 8'h00;
                        next_RxDataOutWEn <= 1'b0;
                        next_rstCRC <= 1'b0;
                        next_CRCData <= 8'h00;
                        next_CRC5En <= 1'b0;
                        next_CRC5_8Bit <= 1'b0;
                        next_CRC16En <= 1'b0;
                        next_RXDataByteCnt <= 10'h00;
                        next_processRxByteRdy <= 1'b1;
                        NextState_prRxByte <= `WAIT_BYTE;
                end
                `WAIT_BYTE:
                        if (processRxDataInWEn == 1'b1)
                        begin
                                NextState_prRxByte <= `CHK_ST;
                                next_RxByte <= RxByteIn;
                                next_RxCtrl <= RxCtrlIn;
                                next_processRxByteRdy <= 1'b0;
                        end
                `HSHAKE_FIN:
                begin
                        next_RxDataOutWEn <= 1'b0;
                        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                        NextState_prRxByte <= `WAIT_BYTE;
                        next_processRxByteRdy <= 1'b1;
                end
                `HSHAKE_CHK:
                begin
                        NextState_prRxByte <= `HSHAKE_FIN;
                        if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
                          next_RxOverflow <= 1'b1;
                        next_RxDataOut <= RxStatus;
                        next_RxCtrlOut <= `RX_PACKET_STOP;
                        next_RxDataOutWEn <= 1'b1;
                end
                `CHK_PID_DO_CHK:
                        if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
                        begin
                                NextState_prRxByte <= `WAIT_BYTE;
                                next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                                next_processRxByteRdy <= 1'b1;
                        end
                        else
                        begin
                                NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
                                next_CRCError <= 1'b0;
                                next_bitStuffError <= 1'b0;
                                next_RxOverflow <= 1'b0;
                                next_NAKRxed <= 1'b0;
                                next_stallRxed <= 1'b0;
                                next_ACKRxed <= 1'b0;
                                next_dataSequence <= 1'b0;
                                next_RxTimeOut <= 1'b0;
                                next_RXDataByteCnt <= 0;
                                next_RxDataOut <= RxByte;
                                next_RxCtrlOut <= `RX_PACKET_START;
                                next_RxDataOutWEn <= 1'b1;
                                next_rstCRC <= 1'b1;
                        end
                `CHK_PID_FIRST_BYTE_PROC:
                begin
                        next_rstCRC <= 1'b0;
                        next_RxDataOutWEn <= 1'b0;
                        case (RxByte[1:0] )
                            `SPECIAL:                              //Special PID.
                            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                            `TOKEN:                                //Token PID
                            begin
                            next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
                            next_RXDataByteCnt <= 0;
                            end
                            `HANDSHAKE:                            //Handshake PID
                            begin
                                case (RxByte[3:2] )
                                    2'b00:
                                next_ACKRxed <= 1'b1;
                                    2'b10:
                                next_NAKRxed <= 1'b1;
                                    2'b11:
                                next_stallRxed <= 1'b1;
                                    default:
                                    begin
                                        $display ("Invalid Handshake PID detected in ProcessRXByte\n");
                                    end
                                endcase
                            next_RXByteStMachCurrState <= `HS_BYTE_ST;
                            end
                            `DATA:                                  //Data PID
                            begin
                                case (RxByte[3:2] )
                                    2'b00:
                                next_dataSequence <= 1'b0;
                                    2'b10:
                                next_dataSequence <= 1'b1;
                                    default:
                                        $display ("Invalid DATA PID detected in ProcessRXByte\n");
                                endcase
                            next_RXByteStMachCurrState <= `DATA_BYTE_ST;
                            next_RXDataByteCnt <= 0;
                            end
                        endcase
                        NextState_prRxByte <= `WAIT_BYTE;
                        next_processRxByteRdy <= 1'b1;
                end
                `DATA_FIN:
                begin
                        next_CRC16En <= 1'b0;
                        next_RxDataOutWEn <= 1'b0;
                        NextState_prRxByte <= `WAIT_BYTE;
                        next_processRxByteRdy <= 1'b1;
                end
                `DATA_CHK_STRM:
                begin
                        next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
                        case (RxCtrl)
                            `DATA_STOP:
                            begin
                                if (CRC16Result != 16'hb001)
                              next_CRCError <= 1'b1;
                            next_RxDataOut <= RxStatus;
                            next_RxCtrlOut <= `RX_PACKET_STOP;
                            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                            end
                            `DATA_BIT_STUFF_ERROR:
                            begin
                            next_bitStuffError <= 1'b1;
                            next_RxDataOut <= RxStatus;
                            next_RxCtrlOut <= `RX_PACKET_STOP;
                            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                            end
                            `DATA_STREAM:
                            begin
                            next_RxDataOut <= RxByte;
                            next_RxCtrlOut <= `RX_PACKET_STREAM;
                            next_CRCData <= RxByte;
                            next_CRC16En <= 1'b1;
                            end
                        endcase
                        next_RxDataOutWEn <= 1'b1;
                        NextState_prRxByte <= `DATA_FIN;
                end
                `DATA_WAIT_CRC:
                        if (CRC16UpdateRdy == 1'b1)
                                NextState_prRxByte <= `DATA_CHK_STRM;
                `TOKEN_CHK_STRM:
                begin
                        next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
                        case (RxCtrl)
                            `DATA_STOP:
                            begin
                                if (CRC5Result != 5'h6)
                              next_CRCError <= 1'b1;
                            next_RxDataOut <= RxStatus;
                            next_RxCtrlOut <= `RX_PACKET_STOP;
                            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                            end
                            `DATA_BIT_STUFF_ERROR:
                            begin
                            next_bitStuffError <= 1'b1;
                            next_RxDataOut <= RxStatus;
                            next_RxCtrlOut <= `RX_PACKET_STOP;
                            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                            end
                            `DATA_STREAM:
                            begin
                                if (RXDataByteCnt > 10'h2)
                                begin
                              next_RxOverflow <= 1'b1;
                              next_RxDataOut <= RxStatus;
                              next_RxCtrlOut <= `RX_PACKET_STOP;
                              next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
                                end
                                else
                                begin
                              next_RxDataOut <= RxByte;
                              next_RxCtrlOut <= `RX_PACKET_STREAM;
                              next_CRCData <= RxByte;
                              next_CRC5_8Bit <= 1'b1;
                              next_CRC5En <= 1'b1;
                                end
                            end
                        endcase
                        next_RxDataOutWEn <= 1'b1;
                        NextState_prRxByte <= `TOKEN_FIN;
                end
                `TOKEN_FIN:
                begin
                        next_CRC5En <= 1'b0;
                        next_RxDataOutWEn <= 1'b0;
                        NextState_prRxByte <= `WAIT_BYTE;
                        next_processRxByteRdy <= 1'b1;
                end
                `TOKEN_WAIT_CRC:
                        if (CRC5UpdateRdy == 1'b1)
                                NextState_prRxByte <= `TOKEN_CHK_STRM;
                `CHK_SYNC_DO:
                begin
                        if (RxByte == `SYNC_BYTE)
                          next_RXByteStMachCurrState = `CHECK_PID_ST;
                        else
                          next_RXByteStMachCurrState = `IDLE_BYTE_ST;
                        NextState_prRxByte <= `WAIT_BYTE;
                        next_processRxByteRdy <= 1'b1;
                end
                `IDLE_CHK_START:
                begin
                        if (RxCtrl == `DATA_START)
                          next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
                        NextState_prRxByte <= `WAIT_BYTE;
                        next_processRxByteRdy <= 1'b1;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxByte_CurrentState
        if (rst)
                CurrState_prRxByte <= `START_PRBY;
        else
                CurrState_prRxByte <= NextState_prRxByte;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxByte_RegOutput
        if (rst)
        begin
                RxByte <= 8'h00;
                RxCtrl <= 8'h00;
                RXByteStMachCurrState <= `IDLE_BYTE_ST;
                CRCError <= 1'b0;
                bitStuffError <= 1'b0;
                RxOverflow <= 1'b0;
                RxTimeOut <= 1'b0;
                NAKRxed <= 1'b0;
                stallRxed <= 1'b0;
                ACKRxed <= 1'b0;
                dataSequence <= 1'b0;
                RXDataByteCnt <= 10'h00;
                RxDataOut <= 8'h00;
                RxCtrlOut <= 8'h00;
                RxDataOutWEn <= 1'b0;
                rstCRC <= 1'b0;
                CRCData <= 8'h00;
                CRC5En <= 1'b0;
                CRC5_8Bit <= 1'b0;
                CRC16En <= 1'b0;
                processRxByteRdy <= 1'b1;
        end
        else
        begin
                RxByte <= next_RxByte;
                RxCtrl <= next_RxCtrl;
                RXByteStMachCurrState <= next_RXByteStMachCurrState;
                CRCError <= next_CRCError;
                bitStuffError <= next_bitStuffError;
                RxOverflow <= next_RxOverflow;
                RxTimeOut <= next_RxTimeOut;
                NAKRxed <= next_NAKRxed;
                stallRxed <= next_stallRxed;
                ACKRxed <= next_ACKRxed;
                dataSequence <= next_dataSequence;
                RXDataByteCnt <= next_RXDataByteCnt;
                RxDataOut <= next_RxDataOut;
                RxCtrlOut <= next_RxCtrlOut;
                RxDataOutWEn <= next_RxDataOutWEn;
                rstCRC <= next_rstCRC;
                CRCData <= next_CRCData;
                CRC5En <= next_CRC5En;
                CRC5_8Bit <= next_CRC5_8Bit;
                CRC16En <= next_CRC16En;
                processRxByteRdy <= next_processRxByteRdy;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_06_alpha/] [RTL/] [serialInterfaceEngine/] [processRxByte.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxByte.v`
11			`// Generated : 09/13/04 06:05:00`
12			`// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxByte.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbSerialInterfaceEngine_h.v"
23			`include "usbConstants_h.v"
24
25			`module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);`
26			`input [15:0] CRC16Result;`
27			`input CRC16UpdateRdy;`
28			`input [4:0] CRC5Result;`
29			`input CRC5UpdateRdy;`
30			`input [7:0] RxByteIn;`
31			`input [7:0] RxCtrlIn;`
32			`input clk;`
33			`input processRxDataInWEn;`
34			`input rst;`
35			`output CRC16En;`
36			`output CRC5En;`
37			`output CRC5_8Bit;`
38			`output [7:0] CRCData;`
39			`output [7:0] RxCtrlOut;`
40			`output RxDataOutWEn;`
41			`output [7:0] RxDataOut;`
42			`output processRxByteRdy;`
43			`output rstCRC;`
44
45			`reg CRC16En, next_CRC16En;`
46			`wire [15:0] CRC16Result;`
47			`wire CRC16UpdateRdy;`
48			`reg CRC5En, next_CRC5En;`
49			`wire [4:0] CRC5Result;`
50			`wire CRC5UpdateRdy;`
51			`reg CRC5_8Bit, next_CRC5_8Bit;`
52			`reg [7:0] CRCData, next_CRCData;`
53			`wire [7:0] RxByteIn;`
54			`wire [7:0] RxCtrlIn;`
55			`reg [7:0] RxCtrlOut, next_RxCtrlOut;`
56			`reg RxDataOutWEn, next_RxDataOutWEn;`
57			`reg [7:0] RxDataOut, next_RxDataOut;`
58			`wire clk;`
59			`reg processRxByteRdy, next_processRxByteRdy;`
60			`wire processRxDataInWEn;`
61			`wire rst;`
62			`reg rstCRC, next_rstCRC;`
63
64			`// diagram signals declarations`
65			`reg ACKRxed, next_ACKRxed;`
66			`reg CRCError, next_CRCError;`
67			`reg NAKRxed, next_NAKRxed;`
68			`reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;`
69			`reg [9:0]RXDataByteCnt, next_RXDataByteCnt;`
70			`reg [7:0]RxByte, next_RxByte;`
71			`reg [7:0]RxCtrl, next_RxCtrl;`
72			`reg RxOverflow, next_RxOverflow;`
73			`reg [7:0]RxStatus;`
74			`reg RxTimeOut, next_RxTimeOut;`
75			`reg Signal1, next_Signal1;`
76			`reg bitStuffError, next_bitStuffError;`
77			`reg dataSequence, next_dataSequence;`
78			`reg stallRxed, next_stallRxed;`
79
80			`// BINARY ENCODED state machine: prRxByte`
81			`// State codes definitions:`
82			`define CHK_ST 4'b0000
83			`define START_PRBY 4'b0001
84			`define WAIT_BYTE 4'b0010
85			`define IDLE_CHK_START 4'b0011
86			`define CHK_SYNC_DO 4'b0100
87			`define CHK_PID_DO_CHK 4'b0101
88			`define CHK_PID_FIRST_BYTE_PROC 4'b0110
89			`define HSHAKE_FIN 4'b0111
90			`define HSHAKE_CHK 4'b1000
91			`define TOKEN_CHK_STRM 4'b1001
92			`define TOKEN_FIN 4'b1010
93			`define DATA_FIN 4'b1011
94			`define DATA_CHK_STRM 4'b1100
95			`define TOKEN_WAIT_CRC 4'b1101
96			`define DATA_WAIT_CRC 4'b1110
97
98			`reg [3:0] CurrState_prRxByte;`
99			`reg [3:0] NextState_prRxByte;`
100
101			`// Diagram actions (continuous assignments allowed only: assign ...)`
102			`always @`
103			`(next_CRCError or next_bitStuffError or`
104			`next_RxOverflow or next_NAKRxed or`
105			`next_stallRxed or next_ACKRxed or`
106			`next_dataSequence)`
107			`begin`
108			`RxStatus <=`
109			`{1'b0, next_dataSequence,`
110			`next_ACKRxed,`
111			`next_stallRxed, next_NAKRxed,`
112			`next_RxOverflow,`
113			`next_bitStuffError, next_CRCError };`
114			`end`
115
116
117			`//--------------------------------------------------------------------`
118			`// Machine: prRxByte`
119			`//--------------------------------------------------------------------`
120			`//----------------------------------`
121			`// NextState logic (combinatorial)`
122			`//----------------------------------`
123			`always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)`
124			`begin : prRxByte_NextState`
125			`NextState_prRxByte <= CurrState_prRxByte;`
126			`// Set default values for outputs and signals`
127			`next_RxByte <= RxByte;`
128			`next_RxCtrl <= RxCtrl;`
129			`next_RXByteStMachCurrState <= RXByteStMachCurrState;`
130			`next_CRCError <= CRCError;`
131			`next_bitStuffError <= bitStuffError;`
132			`next_RxOverflow <= RxOverflow;`
133			`next_RxTimeOut <= RxTimeOut;`
134			`next_NAKRxed <= NAKRxed;`
135			`next_stallRxed <= stallRxed;`
136			`next_ACKRxed <= ACKRxed;`
137			`next_dataSequence <= dataSequence;`
138			`next_RxDataOut <= RxDataOut;`
139			`next_RxCtrlOut <= RxCtrlOut;`
140			`next_RxDataOutWEn <= RxDataOutWEn;`
141			`next_rstCRC <= rstCRC;`
142			`next_CRCData <= CRCData;`
143			`next_CRC5En <= CRC5En;`
144			`next_CRC5_8Bit <= CRC5_8Bit;`
145			`next_CRC16En <= CRC16En;`
146			`next_RXDataByteCnt <= RXDataByteCnt;`
147			`next_processRxByteRdy <= processRxByteRdy;`
148			`case (CurrState_prRxByte) // synopsys parallel_case full_case`
149			`CHK_ST:
150			if (RXByteStMachCurrState == `HS_BYTE_ST)
151			NextState_prRxByte <= `HSHAKE_CHK;
152			else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
153			NextState_prRxByte <= `TOKEN_WAIT_CRC;
154			else if (RXByteStMachCurrState == `DATA_BYTE_ST)
155			NextState_prRxByte <= `DATA_WAIT_CRC;
156			else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
157			NextState_prRxByte <= `IDLE_CHK_START;
158			else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
159			NextState_prRxByte <= `CHK_SYNC_DO;
160			else if (RXByteStMachCurrState == `CHECK_PID_ST)
161			NextState_prRxByte <= `CHK_PID_DO_CHK;
162			`START_PRBY:
163			`begin`
164			`next_RxByte <= 8'h00;`
165			`next_RxCtrl <= 8'h00;`
166			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
167			`next_CRCError <= 1'b0;`
168			`next_bitStuffError <= 1'b0;`
169			`next_RxOverflow <= 1'b0;`
170			`next_RxTimeOut <= 1'b0;`
171			`next_NAKRxed <= 1'b0;`
172			`next_stallRxed <= 1'b0;`
173			`next_ACKRxed <= 1'b0;`
174			`next_dataSequence <= 1'b0;`
175			`next_RxDataOut <= 8'h00;`
176			`next_RxCtrlOut <= 8'h00;`
177			`next_RxDataOutWEn <= 1'b0;`
178			`next_rstCRC <= 1'b0;`
179			`next_CRCData <= 8'h00;`
180			`next_CRC5En <= 1'b0;`
181			`next_CRC5_8Bit <= 1'b0;`
182			`next_CRC16En <= 1'b0;`
183			`next_RXDataByteCnt <= 10'h00;`
184			`next_processRxByteRdy <= 1'b1;`
185			NextState_prRxByte <= `WAIT_BYTE;
186			`end`
187			`WAIT_BYTE:
188			`if (processRxDataInWEn == 1'b1)`
189			`begin`
190			NextState_prRxByte <= `CHK_ST;
191			`next_RxByte <= RxByteIn;`
192			`next_RxCtrl <= RxCtrlIn;`
193			`next_processRxByteRdy <= 1'b0;`
194			`end`
195			`HSHAKE_FIN:
196			`begin`
197			`next_RxDataOutWEn <= 1'b0;`
198			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
199			NextState_prRxByte <= `WAIT_BYTE;
200			`next_processRxByteRdy <= 1'b1;`
201			`end`
202			`HSHAKE_CHK:
203			`begin`
204			NextState_prRxByte <= `HSHAKE_FIN;
205			if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
206			`next_RxOverflow <= 1'b1;`
207			`next_RxDataOut <= RxStatus;`
208			next_RxCtrlOut <= `RX_PACKET_STOP;
209			`next_RxDataOutWEn <= 1'b1;`
210			`end`
211			`CHK_PID_DO_CHK:
212			`if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)`
213			`begin`
214			NextState_prRxByte <= `WAIT_BYTE;
215			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
216			`next_processRxByteRdy <= 1'b1;`
217			`end`
218			`else`
219			`begin`
220			NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
221			`next_CRCError <= 1'b0;`
222			`next_bitStuffError <= 1'b0;`
223			`next_RxOverflow <= 1'b0;`
224			`next_NAKRxed <= 1'b0;`
225			`next_stallRxed <= 1'b0;`
226			`next_ACKRxed <= 1'b0;`
227			`next_dataSequence <= 1'b0;`
228			`next_RxTimeOut <= 1'b0;`
229			`next_RXDataByteCnt <= 0;`
230			`next_RxDataOut <= RxByte;`
231			next_RxCtrlOut <= `RX_PACKET_START;
232			`next_RxDataOutWEn <= 1'b1;`
233			`next_rstCRC <= 1'b1;`
234			`end`
235			`CHK_PID_FIRST_BYTE_PROC:
236			`begin`
237			`next_rstCRC <= 1'b0;`
238			`next_RxDataOutWEn <= 1'b0;`
239			`case (RxByte[1:0] )`
240			`SPECIAL: //Special PID.
241			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
242			`TOKEN: //Token PID
243			`begin`
244			next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
245			`next_RXDataByteCnt <= 0;`
246			`end`
247			`HANDSHAKE: //Handshake PID
248			`begin`
249			`case (RxByte[3:2] )`
250			`2'b00:`
251			`next_ACKRxed <= 1'b1;`
252			`2'b10:`
253			`next_NAKRxed <= 1'b1;`
254			`2'b11:`
255			`next_stallRxed <= 1'b1;`
256			`default:`
257			`begin`
258			`$display ("Invalid Handshake PID detected in ProcessRXByte\n");`
259			`end`
260			`endcase`
261			next_RXByteStMachCurrState <= `HS_BYTE_ST;
262			`end`
263			`DATA: //Data PID
264			`begin`
265			`case (RxByte[3:2] )`
266			`2'b00:`
267			`next_dataSequence <= 1'b0;`
268			`2'b10:`
269			`next_dataSequence <= 1'b1;`
270			`default:`
271			`$display ("Invalid DATA PID detected in ProcessRXByte\n");`
272			`endcase`
273			next_RXByteStMachCurrState <= `DATA_BYTE_ST;
274			`next_RXDataByteCnt <= 0;`
275			`end`
276			`endcase`
277			NextState_prRxByte <= `WAIT_BYTE;
278			`next_processRxByteRdy <= 1'b1;`
279			`end`
280			`DATA_FIN:
281			`begin`
282			`next_CRC16En <= 1'b0;`
283			`next_RxDataOutWEn <= 1'b0;`
284			NextState_prRxByte <= `WAIT_BYTE;
285			`next_processRxByteRdy <= 1'b1;`
286			`end`
287			`DATA_CHK_STRM:
288			`begin`
289			`next_RXDataByteCnt <= RXDataByteCnt + 1'b1;`
290			`case (RxCtrl)`
291			`DATA_STOP:
292			`begin`
293			`if (CRC16Result != 16'hb001)`
294			`next_CRCError <= 1'b1;`
295			`next_RxDataOut <= RxStatus;`
296			next_RxCtrlOut <= `RX_PACKET_STOP;
297			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
298			`end`
299			`DATA_BIT_STUFF_ERROR:
300			`begin`
301			`next_bitStuffError <= 1'b1;`
302			`next_RxDataOut <= RxStatus;`
303			next_RxCtrlOut <= `RX_PACKET_STOP;
304			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
305			`end`
306			`DATA_STREAM:
307			`begin`
308			`next_RxDataOut <= RxByte;`
309			next_RxCtrlOut <= `RX_PACKET_STREAM;
310			`next_CRCData <= RxByte;`
311			`next_CRC16En <= 1'b1;`
312			`end`
313			`endcase`
314			`next_RxDataOutWEn <= 1'b1;`
315			NextState_prRxByte <= `DATA_FIN;
316			`end`
317			`DATA_WAIT_CRC:
318			`if (CRC16UpdateRdy == 1'b1)`
319			NextState_prRxByte <= `DATA_CHK_STRM;
320			`TOKEN_CHK_STRM:
321			`begin`
322			`next_RXDataByteCnt <= RXDataByteCnt + 1'b1;`
323			`case (RxCtrl)`
324			`DATA_STOP:
325			`begin`
326			`if (CRC5Result != 5'h6)`
327			`next_CRCError <= 1'b1;`
328			`next_RxDataOut <= RxStatus;`
329			next_RxCtrlOut <= `RX_PACKET_STOP;
330			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
331			`end`
332			`DATA_BIT_STUFF_ERROR:
333			`begin`
334			`next_bitStuffError <= 1'b1;`
335			`next_RxDataOut <= RxStatus;`
336			next_RxCtrlOut <= `RX_PACKET_STOP;
337			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
338			`end`
339			`DATA_STREAM:
340			`begin`
341			`if (RXDataByteCnt > 10'h2)`
342			`begin`
343			`next_RxOverflow <= 1'b1;`
344			`next_RxDataOut <= RxStatus;`
345			next_RxCtrlOut <= `RX_PACKET_STOP;
346			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
347			`end`
348			`else`
349			`begin`
350			`next_RxDataOut <= RxByte;`
351			next_RxCtrlOut <= `RX_PACKET_STREAM;
352			`next_CRCData <= RxByte;`
353			`next_CRC5_8Bit <= 1'b1;`
354			`next_CRC5En <= 1'b1;`
355			`end`
356			`end`
357			`endcase`
358			`next_RxDataOutWEn <= 1'b1;`
359			NextState_prRxByte <= `TOKEN_FIN;
360			`end`
361			`TOKEN_FIN:
362			`begin`
363			`next_CRC5En <= 1'b0;`
364			`next_RxDataOutWEn <= 1'b0;`
365			NextState_prRxByte <= `WAIT_BYTE;
366			`next_processRxByteRdy <= 1'b1;`
367			`end`
368			`TOKEN_WAIT_CRC:
369			`if (CRC5UpdateRdy == 1'b1)`
370			NextState_prRxByte <= `TOKEN_CHK_STRM;
371			`CHK_SYNC_DO:
372			`begin`
373			if (RxByte == `SYNC_BYTE)
374			next_RXByteStMachCurrState = `CHECK_PID_ST;
375			`else`
376			next_RXByteStMachCurrState = `IDLE_BYTE_ST;
377			NextState_prRxByte <= `WAIT_BYTE;
378			`next_processRxByteRdy <= 1'b1;`
379			`end`
380			`IDLE_CHK_START:
381			`begin`
382			if (RxCtrl == `DATA_START)
383			next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
384			NextState_prRxByte <= `WAIT_BYTE;
385			`next_processRxByteRdy <= 1'b1;`
386			`end`
387			`endcase`
388			`end`
389
390			`//----------------------------------`
391			`// Current State Logic (sequential)`
392			`//----------------------------------`
393			`always @ (posedge clk)`
394			`begin : prRxByte_CurrentState`
395			`if (rst)`
396			CurrState_prRxByte <= `START_PRBY;
397			`else`
398			`CurrState_prRxByte <= NextState_prRxByte;`
399			`end`
400
401			`//----------------------------------`
402			`// Registered outputs logic`
403			`//----------------------------------`
404			`always @ (posedge clk)`
405			`begin : prRxByte_RegOutput`
406			`if (rst)`
407			`begin`
408			`RxByte <= 8'h00;`
409			`RxCtrl <= 8'h00;`
410			RXByteStMachCurrState <= `IDLE_BYTE_ST;
411			`CRCError <= 1'b0;`
412			`bitStuffError <= 1'b0;`
413			`RxOverflow <= 1'b0;`
414			`RxTimeOut <= 1'b0;`
415			`NAKRxed <= 1'b0;`
416			`stallRxed <= 1'b0;`
417			`ACKRxed <= 1'b0;`
418			`dataSequence <= 1'b0;`
419			`RXDataByteCnt <= 10'h00;`
420			`RxDataOut <= 8'h00;`
421			`RxCtrlOut <= 8'h00;`
422			`RxDataOutWEn <= 1'b0;`
423			`rstCRC <= 1'b0;`
424			`CRCData <= 8'h00;`
425			`CRC5En <= 1'b0;`
426			`CRC5_8Bit <= 1'b0;`
427			`CRC16En <= 1'b0;`
428			`processRxByteRdy <= 1'b1;`
429			`end`
430			`else`
431			`begin`
432			`RxByte <= next_RxByte;`
433			`RxCtrl <= next_RxCtrl;`
434			`RXByteStMachCurrState <= next_RXByteStMachCurrState;`
435			`CRCError <= next_CRCError;`
436			`bitStuffError <= next_bitStuffError;`
437			`RxOverflow <= next_RxOverflow;`
438			`RxTimeOut <= next_RxTimeOut;`
439			`NAKRxed <= next_NAKRxed;`
440			`stallRxed <= next_stallRxed;`
441			`ACKRxed <= next_ACKRxed;`
442			`dataSequence <= next_dataSequence;`
443			`RXDataByteCnt <= next_RXDataByteCnt;`
444			`RxDataOut <= next_RxDataOut;`
445			`RxCtrlOut <= next_RxCtrlOut;`
446			`RxDataOutWEn <= next_RxDataOutWEn;`
447			`rstCRC <= next_rstCRC;`
448			`CRCData <= next_CRCData;`
449			`CRC5En <= next_CRC5En;`
450			`CRC5_8Bit <= next_CRC5_8Bit;`
451			`CRC16En <= next_CRC16En;`
452			`processRxByteRdy <= next_processRxByteRdy;`
453			`end`
454			`end`
455
456			`endmodule`