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[/] [usbhostslave/] [tags/] [rel_00_06_alpha/] [RTL/] [serialInterfaceEngine/] [readUSBWireData.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// readUSBWireData.v                                            ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: readUSBWireData.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/10/11 04:01:01  sfielding
// Created
//
//
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
input   [1:0] RxBitsIn;
output  RxDataInTick;
input   SIERxRdyIn;
input   clk;
input   fullSpeedRate;
input   rst;
input   disableWireRead;
output  [1:0] RxBitsOut;
output  SIERxWEn;
 
wire   [1:0] RxBitsIn;
reg    RxDataInTick;
wire   SIERxRdyIn;
wire   clk;
wire   fullSpeedRate;
wire   rst;
reg    [1:0] RxBitsOut;
reg    SIERxWEn;
 
// local registers
reg  [1:0]buffer0;
reg  [1:0]buffer1;
reg  [1:0]buffer2;
reg  [1:0]buffer3;
reg  [2:0]bufferCnt;
reg  [1:0]bufferInIndex;
reg  [1:0]bufferOutIndex;
reg decBufferCnt;
reg  [4:0]i;
reg incBufferCnt;
reg  [1:0]oldRxBitsIn;
reg [1:0] RxBitsInReg;
 
// buffer output state machine state codes:
`define WAIT_BUFFER_NOT_EMPTY 2'b00
`define WAIT_SIE_RX_READY 2'b01
`define SIE_RX_WRITE 2'b10
 
reg [1:0] bufferOutStMachCurrState;
 
 
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    bufferCnt <= 3'b000;
  end
  else begin
    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
      bufferCnt <= bufferCnt + 1'b1;
    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
      bufferCnt <= bufferCnt - 1'b1;
  end
end
 
 
 
//Perform line rate clock recovery
//Recover the wire data, and store data to buffer
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    i <= 5'b00000;
    incBufferCnt <= 1'b0;
    bufferInIndex <= 2'b00;
    buffer0 <= 2'b00;
    buffer1 <= 2'b00;
    buffer2 <= 2'b00;
    buffer3 <= 2'b00;
    RxDataInTick <= 1'b0;
  end
  else begin
    RxBitsInReg <= RxBitsIn;      //sync to local clock to avoid metastability issues
    incBufferCnt <= 1'b0;         //default value
    oldRxBitsIn <= RxBitsInReg;
    if (oldRxBitsIn != RxBitsInReg)  //if edge detected then
      i <= 5'b00000;              //reset the counter
    else
      i <= i + 1'b1;
    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
    begin
      RxDataInTick <= !RxDataInTick;
      if (disableWireRead != 1'b1)  //do not read wire data when transmitter is active
      begin
        incBufferCnt <= 1'b1;
        bufferInIndex <= bufferInIndex + 1'b1;
        case (bufferInIndex)
          2'b00 : buffer0 <= RxBitsInReg;
          2'b01 : buffer1 <= RxBitsInReg;
          2'b10 : buffer2 <= RxBitsInReg;
          2'b11 : buffer3 <= RxBitsInReg;
        endcase
      end
    end
  end
end
 
 
 
//read from buffer, and output to SIEReceiver
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    decBufferCnt <= 1'b0;
    bufferOutIndex <= 2'b00;
    RxBitsOut <= 2'b00;
    SIERxWEn <= 1'b0;
    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
  end
  else begin
    case (bufferOutStMachCurrState)
      `WAIT_BUFFER_NOT_EMPTY:
      begin
        if (bufferCnt != 3'b000)
          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
      end
      `WAIT_SIE_RX_READY:
      begin
        if (SIERxRdyIn == 1'b1)
        begin
          SIERxWEn <= 1'b1;
          bufferOutStMachCurrState <= `SIE_RX_WRITE;
          decBufferCnt <= 1'b1;
          bufferOutIndex <= bufferOutIndex + 1'b1;
          case (bufferOutIndex)
            2'b00 :  RxBitsOut <= buffer0;
            2'b01 : RxBitsOut <= buffer1;
            2'b10 : RxBitsOut <= buffer2;
            2'b11 : RxBitsOut <= buffer3;
          endcase
        end
      end
      `SIE_RX_WRITE:
      begin
        SIERxWEn <= 1'b0;
        decBufferCnt <= 1'b0;
        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
      end
    endcase
  end
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// readUSBWireData.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44	5	sfielding	`// $Id: readUSBWireData.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $`
45	2	sfielding	`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	5	sfielding	`// Revision 1.1.1.1 2004/10/11 04:01:01 sfielding`
50			`// Created`
51	2	sfielding	`//`
52	5	sfielding	`//`
53	2	sfielding
54			`timescale 1ns / 1ps
55			`include "usbSerialInterfaceEngine_h.v"
56
57			`module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);`
58			`input [1:0] RxBitsIn;`
59			`output RxDataInTick;`
60			`input SIERxRdyIn;`
61			`input clk;`
62			`input fullSpeedRate;`
63			`input rst;`
64			`input disableWireRead;`
65			`output [1:0] RxBitsOut;`
66			`output SIERxWEn;`
67
68			`wire [1:0] RxBitsIn;`
69			`reg RxDataInTick;`
70			`wire SIERxRdyIn;`
71			`wire clk;`
72			`wire fullSpeedRate;`
73			`wire rst;`
74			`reg [1:0] RxBitsOut;`
75			`reg SIERxWEn;`
76
77			`// local registers`
78			`reg [1:0]buffer0;`
79			`reg [1:0]buffer1;`
80			`reg [1:0]buffer2;`
81			`reg [1:0]buffer3;`
82			`reg [2:0]bufferCnt;`
83			`reg [1:0]bufferInIndex;`
84			`reg [1:0]bufferOutIndex;`
85			`reg decBufferCnt;`
86			`reg [4:0]i;`
87			`reg incBufferCnt;`
88			`reg [1:0]oldRxBitsIn;`
89	5	sfielding	`reg [1:0] RxBitsInReg;`
90	2	sfielding
91			`// buffer output state machine state codes:`
92			`define WAIT_BUFFER_NOT_EMPTY 2'b00
93			`define WAIT_SIE_RX_READY 2'b01
94			`define SIE_RX_WRITE 2'b10
95
96			`reg [1:0] bufferOutStMachCurrState;`
97
98
99			`always @(posedge clk) begin`
100			`if (rst == 1'b1)`
101			`begin`
102			`bufferCnt <= 3'b000;`
103	5	sfielding	`end`
104	2	sfielding	`else begin`
105			`if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)`
106			`bufferCnt <= bufferCnt + 1'b1;`
107			`else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)`
108			`bufferCnt <= bufferCnt - 1'b1;`
109			`end`
110			`end`
111
112
113
114			`//Perform line rate clock recovery`
115			`//Recover the wire data, and store data to buffer`
116			`always @(posedge clk) begin`
117			`if (rst == 1'b1)`
118			`begin`
119			`i <= 5'b00000;`
120	5	sfielding	`incBufferCnt <= 1'b0;`
121			`bufferInIndex <= 2'b00;`
122			`buffer0 <= 2'b00;`
123			`buffer1 <= 2'b00;`
124			`buffer2 <= 2'b00;`
125			`buffer3 <= 2'b00;`
126	2	sfielding	`RxDataInTick <= 1'b0;`
127	5	sfielding	`end`
128	2	sfielding	`else begin`
129	5	sfielding	`RxBitsInReg <= RxBitsIn; //sync to local clock to avoid metastability issues`
130			`incBufferCnt <= 1'b0; //default value`
131			`oldRxBitsIn <= RxBitsInReg;`
132			`if (oldRxBitsIn != RxBitsInReg) //if edge detected then`
133			`i <= 5'b00000; //reset the counter`
134			`else`
135			`i <= i + 1'b1;`
136			`if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) \|\| (fullSpeedRate == 1'b0 && i == 5'b10000) )`
137			`begin`
138	2	sfielding	`RxDataInTick <= !RxDataInTick;`
139			`if (disableWireRead != 1'b1) //do not read wire data when transmitter is active`
140			`begin`
141			`incBufferCnt <= 1'b1;`
142	5	sfielding	`bufferInIndex <= bufferInIndex + 1'b1;`
143			`case (bufferInIndex)`
144			`2'b00 : buffer0 <= RxBitsInReg;`
145			`2'b01 : buffer1 <= RxBitsInReg;`
146			`2'b10 : buffer2 <= RxBitsInReg;`
147			`2'b11 : buffer3 <= RxBitsInReg;`
148			`endcase`
149	2	sfielding	`end`
150	5	sfielding	`end`
151	2	sfielding	`end`
152			`end`
153
154	5	sfielding
155	2	sfielding
156			`//read from buffer, and output to SIEReceiver`
157			`always @(posedge clk) begin`
158			`if (rst == 1'b1)`
159			`begin`
160	5	sfielding	`decBufferCnt <= 1'b0;`
161			`bufferOutIndex <= 2'b00;`
162			`RxBitsOut <= 2'b00;`
163			`SIERxWEn <= 1'b0;`
164			bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
165			`end`
166	2	sfielding	`else begin`
167	5	sfielding	`case (bufferOutStMachCurrState)`
168			`WAIT_BUFFER_NOT_EMPTY:
169			`begin`
170			`if (bufferCnt != 3'b000)`
171			bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
172			`end`
173			`WAIT_SIE_RX_READY:
174			`begin`
175			`if (SIERxRdyIn == 1'b1)`
176			`begin`
177			`SIERxWEn <= 1'b1;`
178			bufferOutStMachCurrState <= `SIE_RX_WRITE;
179			`decBufferCnt <= 1'b1;`
180			`bufferOutIndex <= bufferOutIndex + 1'b1;`
181			`case (bufferOutIndex)`
182			`2'b00 : RxBitsOut <= buffer0;`
183			`2'b01 : RxBitsOut <= buffer1;`
184			`2'b10 : RxBitsOut <= buffer2;`
185			`2'b11 : RxBitsOut <= buffer3;`
186			`endcase`
187			`end`
188			`end`
189			`SIE_RX_WRITE:
190			`begin`
191			`SIERxWEn <= 1'b0;`
192			`decBufferCnt <= 1'b0;`
193			bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
194			`end`
195			`endcase`
196	2	sfielding	`end`
197			`end`
198
199	5	sfielding
200	2	sfielding
201
202
203			`endmodule`

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[/] [usbhostslave/] [tags/] [rel_00_06_alpha/] [RTL/] [serialInterfaceEngine/] [readUSBWireData.v] - Blame information for rev 5