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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_07_alpha/] [RTL/] [hostController/] [sendpacketarbiter.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketarbiter.v
// Generated   : 09/10/04 20:20:24
// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacketarbiter.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbConstants_h.v"
 
module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);
input   HCTxReq;
input   [3:0] HC_PID;
input   HC_SP_WEn;
input   SOFTxReq;
input   SOF_SP_WEn;
input   clk;
input   rst;
output  HCTxGnt;
output  SOFTxGnt;
output  [3:0] sendPacketPID;
output  sendPacketWEnable;
 
reg     HCTxGnt, next_HCTxGnt;
wire    HCTxReq;
wire    [3:0] HC_PID;
wire    HC_SP_WEn;
reg     SOFTxGnt, next_SOFTxGnt;
wire    SOFTxReq;
wire    SOF_SP_WEn;
wire    clk;
wire    rst;
reg     [3:0] sendPacketPID, next_sendPacketPID;
reg     sendPacketWEnable, next_sendPacketWEnable;
 
// diagram signals declarations
reg muxSOFNotHC, next_muxSOFNotHC;
 
// BINARY ENCODED state machine: sendPktArb
// State codes definitions:
`define HC_ACT 2'b00
`define SOF_ACT 2'b01
`define SARB_WAIT_REQ 2'b10
`define START_SARB 2'b11
 
reg [1:0] CurrState_sendPktArb;
reg [1:0] NextState_sendPktArb;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// hostController/SOFTransmit mux
always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
begin
    if (muxSOFNotHC  == 1'b1)
    begin
        sendPacketWEnable <= SOF_SP_WEn;
        sendPacketPID <= `SOF;
    end
    else
    begin
        sendPacketWEnable <= HC_SP_WEn;
        sendPacketPID <= HC_PID;
    end
end
 
 
//--------------------------------------------------------------------
// Machine: sendPktArb
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
begin : sendPktArb_NextState
        NextState_sendPktArb <= CurrState_sendPktArb;
        // Set default values for outputs and signals
        next_HCTxGnt <= HCTxGnt;
        next_SOFTxGnt <= SOFTxGnt;
        next_muxSOFNotHC <= muxSOFNotHC;
        case (CurrState_sendPktArb) // synopsys parallel_case full_case
                `HC_ACT:
                        if (HCTxReq == 1'b0)
                        begin
                                NextState_sendPktArb <= `SARB_WAIT_REQ;
                                next_HCTxGnt <= 1'b0;
                        end
                `SOF_ACT:
                        if (SOFTxReq == 1'b0)
                        begin
                                NextState_sendPktArb <= `SARB_WAIT_REQ;
                                next_SOFTxGnt <= 1'b0;
                        end
                `SARB_WAIT_REQ:
                        if (SOFTxReq == 1'b1)
                        begin
                                NextState_sendPktArb <= `SOF_ACT;
                                next_SOFTxGnt <= 1'b1;
                                next_muxSOFNotHC <= 1'b1;
                        end
                        else if (HCTxReq == 1'b1)
                        begin
                                NextState_sendPktArb <= `HC_ACT;
                                next_HCTxGnt <= 1'b1;
                                next_muxSOFNotHC <= 1'b0;
                        end
                `START_SARB:
                        NextState_sendPktArb <= `SARB_WAIT_REQ;
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sendPktArb_CurrentState
        if (rst)
                CurrState_sendPktArb <= `START_SARB;
        else
                CurrState_sendPktArb <= NextState_sendPktArb;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sendPktArb_RegOutput
        if (rst)
        begin
                muxSOFNotHC <= 1'b0;
                SOFTxGnt <= 1'b0;
                HCTxGnt <= 1'b0;
        end
        else
        begin
                muxSOFNotHC <= next_muxSOFNotHC;
                SOFTxGnt <= next_SOFTxGnt;
                HCTxGnt <= next_HCTxGnt;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author :`
6			`// Company :`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketarbiter.v`
11			`// Generated : 09/10/04 20:20:24`
12			`// From : c:\projects\USBHostSlave\RTL\hostController\sendpacketarbiter.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbConstants_h.v"
23
24			`module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);`
25			`input HCTxReq;`
26			`input [3:0] HC_PID;`
27			`input HC_SP_WEn;`
28			`input SOFTxReq;`
29			`input SOF_SP_WEn;`
30			`input clk;`
31			`input rst;`
32			`output HCTxGnt;`
33			`output SOFTxGnt;`
34			`output [3:0] sendPacketPID;`
35			`output sendPacketWEnable;`
36
37			`reg HCTxGnt, next_HCTxGnt;`
38			`wire HCTxReq;`
39			`wire [3:0] HC_PID;`
40			`wire HC_SP_WEn;`
41			`reg SOFTxGnt, next_SOFTxGnt;`
42			`wire SOFTxReq;`
43			`wire SOF_SP_WEn;`
44			`wire clk;`
45			`wire rst;`
46			`reg [3:0] sendPacketPID, next_sendPacketPID;`
47			`reg sendPacketWEnable, next_sendPacketWEnable;`
48
49			`// diagram signals declarations`
50			`reg muxSOFNotHC, next_muxSOFNotHC;`
51
52			`// BINARY ENCODED state machine: sendPktArb`
53			`// State codes definitions:`
54			`define HC_ACT 2'b00
55			`define SOF_ACT 2'b01
56			`define SARB_WAIT_REQ 2'b10
57			`define START_SARB 2'b11
58
59			`reg [1:0] CurrState_sendPktArb;`
60			`reg [1:0] NextState_sendPktArb;`
61
62			`// Diagram actions (continuous assignments allowed only: assign ...)`
63			`// hostController/SOFTransmit mux`
64			`always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)`
65			`begin`
66			`if (muxSOFNotHC == 1'b1)`
67			`begin`
68			`sendPacketWEnable <= SOF_SP_WEn;`
69			sendPacketPID <= `SOF;
70			`end`
71			`else`
72			`begin`
73			`sendPacketWEnable <= HC_SP_WEn;`
74			`sendPacketPID <= HC_PID;`
75			`end`
76			`end`
77
78
79			`//--------------------------------------------------------------------`
80			`// Machine: sendPktArb`
81			`//--------------------------------------------------------------------`
82			`//----------------------------------`
83			`// NextState logic (combinatorial)`
84			`//----------------------------------`
85			`always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)`
86			`begin : sendPktArb_NextState`
87			`NextState_sendPktArb <= CurrState_sendPktArb;`
88			`// Set default values for outputs and signals`
89			`next_HCTxGnt <= HCTxGnt;`
90			`next_SOFTxGnt <= SOFTxGnt;`
91			`next_muxSOFNotHC <= muxSOFNotHC;`
92			`case (CurrState_sendPktArb) // synopsys parallel_case full_case`
93			`HC_ACT:
94			`if (HCTxReq == 1'b0)`
95			`begin`
96			NextState_sendPktArb <= `SARB_WAIT_REQ;
97			`next_HCTxGnt <= 1'b0;`
98			`end`
99			`SOF_ACT:
100			`if (SOFTxReq == 1'b0)`
101			`begin`
102			NextState_sendPktArb <= `SARB_WAIT_REQ;
103			`next_SOFTxGnt <= 1'b0;`
104			`end`
105			`SARB_WAIT_REQ:
106			`if (SOFTxReq == 1'b1)`
107			`begin`
108			NextState_sendPktArb <= `SOF_ACT;
109			`next_SOFTxGnt <= 1'b1;`
110			`next_muxSOFNotHC <= 1'b1;`
111			`end`
112			`else if (HCTxReq == 1'b1)`
113			`begin`
114			NextState_sendPktArb <= `HC_ACT;
115			`next_HCTxGnt <= 1'b1;`
116			`next_muxSOFNotHC <= 1'b0;`
117			`end`
118			`START_SARB:
119			NextState_sendPktArb <= `SARB_WAIT_REQ;
120			`endcase`
121			`end`
122
123			`//----------------------------------`
124			`// Current State Logic (sequential)`
125			`//----------------------------------`
126			`always @ (posedge clk)`
127			`begin : sendPktArb_CurrentState`
128			`if (rst)`
129			CurrState_sendPktArb <= `START_SARB;
130			`else`
131			`CurrState_sendPktArb <= NextState_sendPktArb;`
132			`end`
133
134			`//----------------------------------`
135			`// Registered outputs logic`
136			`//----------------------------------`
137			`always @ (posedge clk)`
138			`begin : sendPktArb_RegOutput`
139			`if (rst)`
140			`begin`
141			`muxSOFNotHC <= 1'b0;`
142			`SOFTxGnt <= 1'b0;`
143			`HCTxGnt <= 1'b0;`
144			`end`
145			`else`
146			`begin`
147			`muxSOFNotHC <= next_muxSOFNotHC;`
148			`SOFTxGnt <= next_SOFTxGnt;`
149			`HCTxGnt <= next_HCTxGnt;`
150			`end`
151			`end`
152
153			`endmodule`

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_00_07_alpha/] [RTL/] [hostController/] [sendpacketarbiter.v] - Blame information for rev 2