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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [hostController/] [sofcontroller.v] - Blame information for rev 40

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// sofcontroller
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
input   clk;
input   HCTxPortGnt;
input   HCTxPortRdy;
input   rst;
input   SOFEnable;
input   SOFTimerClr;
output  [7:0]HCTxPortCntl;
output  [7:0]HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
output  [15:0]SOFTimer;
 
wire    clk;
reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0]HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    rst;
wire    SOFEnable;
reg     [15:0]SOFTimer, next_SOFTimer;
wire    SOFTimerClr;
 
// BINARY ENCODED state machine: sofCntl
// State codes definitions:
`define START_SC 3'b000
`define WAIT_SOF_EN 3'b001
`define WAIT_SEND_RESUME 3'b010
`define INC_TIMER 3'b011
`define SC_WAIT_GNT 3'b100
`define CLR_WEN 3'b101
 
reg [2:0]CurrState_sofCntl, NextState_sofCntl;
 
 
// Machine: sofCntl
 
// NextState logic (combinatorial)
always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
begin
  NextState_sofCntl <= CurrState_sofCntl;
  // Set default values for outputs and signals
  next_SOFTimer <= SOFTimer;
  next_HCTxPortCntl <= HCTxPortCntl;
  next_HCTxPortData <= HCTxPortData;
  next_HCTxPortWEn <= HCTxPortWEn;
  next_HCTxPortReq <= HCTxPortReq;
  case (CurrState_sofCntl)  // synopsys parallel_case full_case
    `START_SC:
    begin
      NextState_sofCntl <= `WAIT_SOF_EN;
    end
    `WAIT_SOF_EN:
    begin
      if (SOFEnable == 1'b1)
      begin
        NextState_sofCntl <= `SC_WAIT_GNT;
        next_HCTxPortReq <= 1'b1;
      end
    end
    `WAIT_SEND_RESUME:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sofCntl <= `CLR_WEN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_RESUME_START;
      end
    end
    `INC_TIMER:
    begin
      next_HCTxPortReq <= 1'b0;
      if (SOFTimerClr == 1'b1)
      next_SOFTimer <= 16'h0000;
      else
      next_SOFTimer <= SOFTimer + 1'b1;
      if (SOFEnable == 1'b0)
      begin
        NextState_sofCntl <= `WAIT_SOF_EN;
        next_SOFTimer <= 16'h0000;
      end
    end
    `SC_WAIT_GNT:
    begin
      if (HCTxPortGnt == 1'b1)
      begin
        NextState_sofCntl <= `WAIT_SEND_RESUME;
      end
    end
    `CLR_WEN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sofCntl <= `INC_TIMER;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_sofCntl <= `START_SC;
  else
    CurrState_sofCntl <= NextState_sofCntl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    SOFTimer <= 16'h0000;
    HCTxPortCntl <= 8'h00;
    HCTxPortData <= 8'h00;
    HCTxPortWEn <= 1'b0;
    HCTxPortReq <= 1'b0;
  end
  else
  begin
    SOFTimer <= next_SOFTimer;
    HCTxPortCntl <= next_HCTxPortCntl;
    HCTxPortData <= next_HCTxPortData;
    HCTxPortWEn <= next_HCTxPortWEn;
    HCTxPortReq <= next_HCTxPortReq;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// sofcontroller`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47
48			`module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);`
49			`input clk;`
50			`input HCTxPortGnt;`
51			`input HCTxPortRdy;`
52			`input rst;`
53			`input SOFEnable;`
54			`input SOFTimerClr;`
55			`output [7:0]HCTxPortCntl;`
56			`output [7:0]HCTxPortData;`
57			`output HCTxPortReq;`
58			`output HCTxPortWEn;`
59			`output [15:0]SOFTimer;`
60
61			`wire clk;`
62			`reg [7:0]HCTxPortCntl, next_HCTxPortCntl;`
63			`reg [7:0]HCTxPortData, next_HCTxPortData;`
64			`wire HCTxPortGnt;`
65			`wire HCTxPortRdy;`
66			`reg HCTxPortReq, next_HCTxPortReq;`
67			`reg HCTxPortWEn, next_HCTxPortWEn;`
68			`wire rst;`
69			`wire SOFEnable;`
70			`reg [15:0]SOFTimer, next_SOFTimer;`
71			`wire SOFTimerClr;`
72
73			`// BINARY ENCODED state machine: sofCntl`
74			`// State codes definitions:`
75			`define START_SC 3'b000
76			`define WAIT_SOF_EN 3'b001
77			`define WAIT_SEND_RESUME 3'b010
78			`define INC_TIMER 3'b011
79			`define SC_WAIT_GNT 3'b100
80			`define CLR_WEN 3'b101
81
82			`reg [2:0]CurrState_sofCntl, NextState_sofCntl;`
83
84
85			`// Machine: sofCntl`
86
87			`// NextState logic (combinatorial)`
88			`always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)`
89			`begin`
90			`NextState_sofCntl <= CurrState_sofCntl;`
91			`// Set default values for outputs and signals`
92			`next_SOFTimer <= SOFTimer;`
93			`next_HCTxPortCntl <= HCTxPortCntl;`
94			`next_HCTxPortData <= HCTxPortData;`
95			`next_HCTxPortWEn <= HCTxPortWEn;`
96			`next_HCTxPortReq <= HCTxPortReq;`
97			`case (CurrState_sofCntl) // synopsys parallel_case full_case`
98			`START_SC:
99			`begin`
100			NextState_sofCntl <= `WAIT_SOF_EN;
101			`end`
102			`WAIT_SOF_EN:
103			`begin`
104			`if (SOFEnable == 1'b1)`
105			`begin`
106			NextState_sofCntl <= `SC_WAIT_GNT;
107			`next_HCTxPortReq <= 1'b1;`
108			`end`
109			`end`
110			`WAIT_SEND_RESUME:
111			`begin`
112			`if (HCTxPortRdy == 1'b1)`
113			`begin`
114			NextState_sofCntl <= `CLR_WEN;
115			`next_HCTxPortWEn <= 1'b1;`
116			`next_HCTxPortData <= 8'h00;`
117			next_HCTxPortCntl <= `TX_RESUME_START;
118			`end`
119			`end`
120			`INC_TIMER:
121			`begin`
122			`next_HCTxPortReq <= 1'b0;`
123			`if (SOFTimerClr == 1'b1)`
124			`next_SOFTimer <= 16'h0000;`
125			`else`
126			`next_SOFTimer <= SOFTimer + 1'b1;`
127			`if (SOFEnable == 1'b0)`
128			`begin`
129			NextState_sofCntl <= `WAIT_SOF_EN;
130			`next_SOFTimer <= 16'h0000;`
131			`end`
132			`end`
133			`SC_WAIT_GNT:
134			`begin`
135			`if (HCTxPortGnt == 1'b1)`
136			`begin`
137			NextState_sofCntl <= `WAIT_SEND_RESUME;
138			`end`
139			`end`
140			`CLR_WEN:
141			`begin`
142			`next_HCTxPortWEn <= 1'b0;`
143			NextState_sofCntl <= `INC_TIMER;
144			`end`
145			`endcase`
146			`end`
147
148			`// Current State Logic (sequential)`
149			`always @ (posedge clk)`
150			`begin`
151			`if (rst)`
152			CurrState_sofCntl <= `START_SC;
153			`else`
154			`CurrState_sofCntl <= NextState_sofCntl;`
155			`end`
156
157			`// Registered outputs logic`
158			`always @ (posedge clk)`
159			`begin`
160			`if (rst)`
161			`begin`
162			`SOFTimer <= 16'h0000;`
163			`HCTxPortCntl <= 8'h00;`
164			`HCTxPortData <= 8'h00;`
165			`HCTxPortWEn <= 1'b0;`
166			`HCTxPortReq <= 1'b0;`
167			`end`
168			`else`
169			`begin`
170			`SOFTimer <= next_SOFTimer;`
171			`HCTxPortCntl <= next_HCTxPortCntl;`
172			`HCTxPortData <= next_HCTxPortData;`
173			`HCTxPortWEn <= next_HCTxPortWEn;`
174			`HCTxPortReq <= next_HCTxPortReq;`
175			`end`
176			`end`
177
178	2	sfielding	`endmodule`

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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [hostController/] [sofcontroller.v] - Blame information for rev 40