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//////////////////////////////////////////////////////////////////////
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//// ////
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//// usbHostControl_h.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: usbHostControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//HCRegIndices
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`define TX_CONTROL_REG 4'h0
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`define TX_TRANS_TYPE_REG 4'h1
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`define TX_LINE_CONTROL_REG 4'h2
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`define TX_SOF_ENABLE_REG 4'h3
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`define TX_ADDR_REG 4'h4
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`define TX_ENDP_REG 4'h5
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`define FRAME_NUM_MSB_REG 4'h6
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`define FRAME_NUM_LSB_REG 4'h7
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`define INTERRUPT_STATUS_REG 4'h8
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`define INTERRUPT_MASK_REG 4'h9
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`define RX_STATUS_REG 4'ha
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`define RX_PID_REG 4'hb
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`define RX_ADDR_REG 4'hc
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`define RX_ENDP_REG 4'hd
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`define RX_CONNECT_STATE_REG 4'he
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`define HCREG_BUFFER_LEN 4'hf
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`define HCREG_MASK 4'hf
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//TXControlRegIndices
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`define TRANS_REQ_BIT 0
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`define SOF_SYNC_BIT 1
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`define PREAMBLE_ENABLE_BIT 2
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//interruptRegIndices
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`define TRANS_DONE_BIT 0
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`define RESUME_INT_BIT 1
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`define CONNECTION_EVENT_BIT 2
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`define SOF_SENT_BIT 3
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//TXTransactionTypes
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`define SETUP_TRANS 0
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`define IN_TRANS 1
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`define OUTDATA0_TRANS 2
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`define OUTDATA1_TRANS 3
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//TXLineControlIndices
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`define TX_LINE_STATE_LSBIT 0
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`define TX_LINE_STATE_MSBIT 1
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`define DIRECT_CONTROL_BIT 2
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`define FULL_SPEED_LINE_POLARITY_BIT 3
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`define FULL_SPEED_LINE_RATE_BIT 4
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//TXSOFEnableIndices
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`define SOF_EN_BIT 0
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//SOFTimeConstants
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`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
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`define SOF_TX_MARGIN 2
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//Host RXStatusRegIndices
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`define HC_CRC_ERROR_BIT 0
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`define HC_BIT_STUFF_ERROR_BIT 1
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`define HC_RX_OVERFLOW_BIT 2
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`define HC_RX_TIME_OUT_BIT 3
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`define HC_NAK_RXED_BIT 4
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`define HC_STALL_RXED_BIT 5
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`define HC_ACK_RXED_BIT 6
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`define HC_DATA_SEQUENCE_BIT 7
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