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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Blame information for rev 40

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processrxbit
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
input   clk;
input   [1:0]JBit;
input   [1:0]KBit;
input   processRxBitsWEn;
input   processRxByteRdy;
input   rst;
input   [1:0]RxBitsIn;
input   RxWireActive;
output  processRxBitRdy;
output  processRxByteWEn;
output  resumeDetected;
output  [7:0]RxCtrlOut;
output  [7:0]RxDataOut;
 
wire    clk;
wire    [1:0]JBit;
wire    [1:0]KBit;
reg     processRxBitRdy, next_processRxBitRdy;
wire    processRxBitsWEn;
wire    processRxByteRdy;
reg     processRxByteWEn, next_processRxByteWEn;
reg     resumeDetected, next_resumeDetected;
wire    rst;
wire    [1:0]RxBitsIn;
reg     [7:0]RxCtrlOut, next_RxCtrlOut;
reg     [7:0]RxDataOut, next_RxDataOut;
wire    RxWireActive;
 
// diagram signals declarations
reg bitStuffError, next_bitStuffError;
reg  [1:0]oldRXBits, next_oldRXBits;
reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
reg  [3:0]RXBitCount, next_RXBitCount;
reg  [1:0]RxBits, next_RxBits;
reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg  [7:0]RXByte, next_RXByte;
reg  [3:0]RXSameBitCount, next_RXSameBitCount;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
 
reg [3:0]CurrState_prRxBit, NextState_prRxBit;
 
 
// Machine: prRxBit
 
// NextState logic (combinatorial)
always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
begin
  NextState_prRxBit <= CurrState_prRxBit;
  // Set default values for outputs and signals
  next_processRxByteWEn <= processRxByteWEn;
  next_RxCtrlOut <= RxCtrlOut;
  next_RxDataOut <= RxDataOut;
  next_resumeDetected <= resumeDetected;
  next_RXBitStMachCurrState <= RXBitStMachCurrState;
  next_RxBits <= RxBits;
  next_RXSameBitCount <= RXSameBitCount;
  next_RXBitCount <= RXBitCount;
  next_oldRXBits <= oldRXBits;
  next_RXByte <= RXByte;
  next_bitStuffError <= bitStuffError;
  next_resumeWaitCnt <= resumeWaitCnt;
  next_processRxBitRdy <= processRxBitRdy;
  case (CurrState_prRxBit)  // synopsys parallel_case full_case
    `START:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RxCtrlOut <= 8'h00;
      next_RxDataOut <= 8'h00;
      next_resumeDetected <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      next_RxBits <= 2'b00;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h0;
      next_oldRXBits <= 2'b00;
      next_RXByte <= 8'h00;
      next_bitStuffError <= 1'b0;
      next_resumeWaitCnt <= 5'h0;
      next_processRxBitRdy <= 1'b1;
      NextState_prRxBit <= `WAIT_BITS;
    end
    `WAIT_BITS:
    begin
      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
      begin
        NextState_prRxBit <= `DATA_RX_CHK_SE0;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
      begin
        NextState_prRxBit <= `RES_RX_CHK;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
      begin
        NextState_prRxBit <= `RES_END_CHK1;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
      begin
        NextState_prRxBit <= `IDLE_CHK_KBIT;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
    end
    `IDLE_FIRST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h1;
      next_oldRXBits <= RxBits;
      //zero is always the first RZ data bit of a new packet
      next_RXByte <= 8'h00;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `IDLE_CHK_KBIT:
    begin
      if ((RxBits == KBit) && (RxWireActive == 1'b1))
      begin
        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
      end
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    end
    `IDLE_WAIT_PRB_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `IDLE_FIRST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_START;
        //start of packet
        next_processRxByteWEn <= 1'b1;
      end
    end
    `DATA_RX_LAST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_CHK_SE0:
    begin
      next_bitStuffError <= 1'b0;
      if (RxBits == `SE0)
      begin
        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
      end
      else
      begin
        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
        begin
        next_RXSameBitCount <= RXSameBitCount + 1'b1;
        //inc 'RXSameBitCount'
        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
        next_bitStuffError <= 1'b1;
        //flag 'bitStuffError'
        else                                          //else no bit stuffing error
        begin
        next_RXBitCount <= RXBitCount + 1'b1;
        if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
        next_processRxBitRdy <= 1'b1;
        //early indication of ready
        end
        next_RXByte <= { 1'b1, RXByte[7:1]};
        //RZ bit <= 1 (ie no change in 'RxBits')
        end
        end
        else                                            //else current 'RxBits' are different from old 'RxBits'
        begin
        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
        begin
        next_RXBitCount <= RXBitCount + 1'b1;
        if (RXBitCount != 4'h7) begin
        next_processRxBitRdy <= 1'b1;
        //early indication of ready
        end
        next_RXByte <= {1'b0, RXByte[7:1]};
        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
        end
        next_RXSameBitCount <= 4'h0;
        //reset 'RXSameBitCount'
        end
        next_oldRXBits <= RxBits;
      end
    end
    `DATA_RX_WAIT_PRB_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_LAST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_STOP;
        //end of packet
        next_processRxByteWEn <= 1'b1;
      end
    end
    `DATA_RX_DATA_DESTUFF:
    begin
      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
      begin
        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
      end
      else if (bitStuffError == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
      end
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    end
    `DATA_RX_BYTE_SEND2:
    begin
      next_processRxByteWEn <= 1'b0;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_BYTE_WAIT_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
        next_RXBitCount <= 4'h0;
        next_RxDataOut <= RXByte;
        next_RxCtrlOut <= `DATA_STREAM;
        next_processRxByteWEn <= 1'b1;
      end
    end
    `DATA_RX_ERROR_CHK_RES:
    begin
      next_processRxByteWEn <= 1'b0;
      if (RxBits == JBit)                           //if current bit is a JBit, then
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      //next state is idle
      else                                          //else
      begin
      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
      //check for resume
      next_resumeWaitCnt <= 5'h0;
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_ERROR_WAIT_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
        next_processRxByteWEn <= 1'b1;
      end
    end
    `RES_RX_CHK:
    begin
      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      else
      begin
      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
      //if we've waited long enough, then
      if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
      begin
      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
      next_resumeDetected <= 1'b1;
      //report resume detected
      end
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `RES_END_CHK1:
    begin
      if (RxBits != KBit)  //line must leave KBit state for the end of resume
      begin
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      next_resumeDetected <= 1'b0;
      //clear resume detected flag
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_prRxBit <= `START;
  else
    CurrState_prRxBit <= NextState_prRxBit;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    processRxByteWEn <= 1'b0;
    RxCtrlOut <= 8'h00;
    RxDataOut <= 8'h00;
    resumeDetected <= 1'b0;
    processRxBitRdy <= 1'b1;
    RXBitStMachCurrState <= `IDLE_BIT_ST;
    RxBits <= 2'b00;
    RXSameBitCount <= 4'h0;
    RXBitCount <= 4'h0;
    oldRXBits <= 2'b00;
    RXByte <= 8'h00;
    bitStuffError <= 1'b0;
    resumeWaitCnt <= 5'h0;
  end
  else
  begin
    processRxByteWEn <= next_processRxByteWEn;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOut <= next_RxDataOut;
    resumeDetected <= next_resumeDetected;
    processRxBitRdy <= next_processRxBitRdy;
    RXBitStMachCurrState <= next_RXBitStMachCurrState;
    RxBits <= next_RxBits;
    RXSameBitCount <= next_RXSameBitCount;
    RXBitCount <= next_RXBitCount;
    oldRXBits <= next_oldRXBits;
    RXByte <= next_RXByte;
    bitStuffError <= next_bitStuffError;
    resumeWaitCnt <= next_resumeWaitCnt;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// processrxbit`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47
48
49	14	sfielding	`module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);`
50	5	sfielding	`input clk;`
51			`input [1:0]JBit;`
52			`input [1:0]KBit;`
53			`input processRxBitsWEn;`
54			`input processRxByteRdy;`
55			`input rst;`
56			`input [1:0]RxBitsIn;`
57	14	sfielding	`input RxWireActive;`
58	5	sfielding	`output processRxBitRdy;`
59			`output processRxByteWEn;`
60			`output resumeDetected;`
61			`output [7:0]RxCtrlOut;`
62			`output [7:0]RxDataOut;`
63
64			`wire clk;`
65			`wire [1:0]JBit;`
66			`wire [1:0]KBit;`
67			`reg processRxBitRdy, next_processRxBitRdy;`
68			`wire processRxBitsWEn;`
69			`wire processRxByteRdy;`
70			`reg processRxByteWEn, next_processRxByteWEn;`
71			`reg resumeDetected, next_resumeDetected;`
72			`wire rst;`
73			`wire [1:0]RxBitsIn;`
74			`reg [7:0]RxCtrlOut, next_RxCtrlOut;`
75			`reg [7:0]RxDataOut, next_RxDataOut;`
76	14	sfielding	`wire RxWireActive;`
77	5	sfielding
78			`// diagram signals declarations`
79			`reg bitStuffError, next_bitStuffError;`
80			`reg [1:0]oldRXBits, next_oldRXBits;`
81	14	sfielding	`reg [4:0]resumeWaitCnt, next_resumeWaitCnt;`
82	5	sfielding	`reg [3:0]RXBitCount, next_RXBitCount;`
83			`reg [1:0]RxBits, next_RxBits;`
84			`reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;`
85			`reg [7:0]RXByte, next_RXByte;`
86			`reg [3:0]RXSameBitCount, next_RXSameBitCount;`
87
88			`// BINARY ENCODED state machine: prRxBit`
89			`// State codes definitions:`
90			`define START 4'b0000
91			`define IDLE_FIRST_BIT 4'b0001
92			`define WAIT_BITS 4'b0010
93			`define IDLE_CHK_KBIT 4'b0011
94			`define DATA_RX_LAST_BIT 4'b0100
95			`define DATA_RX_CHK_SE0 4'b0101
96			`define DATA_RX_DATA_DESTUFF 4'b0110
97			`define DATA_RX_BYTE_SEND2 4'b0111
98			`define DATA_RX_BYTE_WAIT_RDY 4'b1000
99			`define RES_RX_CHK 4'b1001
100			`define DATA_RX_ERROR_CHK_RES 4'b1010
101			`define RES_END_CHK1 4'b1011
102			`define IDLE_WAIT_PRB_RDY 4'b1100
103			`define DATA_RX_WAIT_PRB_RDY 4'b1101
104			`define DATA_RX_ERROR_WAIT_RDY 4'b1110
105
106			`reg [3:0]CurrState_prRxBit, NextState_prRxBit;`
107
108
109			`// Machine: prRxBit`
110
111			`// NextState logic (combinatorial)`
112	14	sfielding	`always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)`
113	5	sfielding	`begin`
114			`NextState_prRxBit <= CurrState_prRxBit;`
115			`// Set default values for outputs and signals`
116			`next_processRxByteWEn <= processRxByteWEn;`
117			`next_RxCtrlOut <= RxCtrlOut;`
118			`next_RxDataOut <= RxDataOut;`
119			`next_resumeDetected <= resumeDetected;`
120			`next_RXBitStMachCurrState <= RXBitStMachCurrState;`
121			`next_RxBits <= RxBits;`
122			`next_RXSameBitCount <= RXSameBitCount;`
123			`next_RXBitCount <= RXBitCount;`
124			`next_oldRXBits <= oldRXBits;`
125			`next_RXByte <= RXByte;`
126			`next_bitStuffError <= bitStuffError;`
127			`next_resumeWaitCnt <= resumeWaitCnt;`
128			`next_processRxBitRdy <= processRxBitRdy;`
129			`case (CurrState_prRxBit) // synopsys parallel_case full_case`
130			`START:
131			`begin`
132			`next_processRxByteWEn <= 1'b0;`
133			`next_RxCtrlOut <= 8'h00;`
134			`next_RxDataOut <= 8'h00;`
135			`next_resumeDetected <= 1'b0;`
136			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
137			`next_RxBits <= 2'b00;`
138			`next_RXSameBitCount <= 4'h0;`
139			`next_RXBitCount <= 4'h0;`
140			`next_oldRXBits <= 2'b00;`
141			`next_RXByte <= 8'h00;`
142			`next_bitStuffError <= 1'b0;`
143	14	sfielding	`next_resumeWaitCnt <= 5'h0;`
144	5	sfielding	`next_processRxBitRdy <= 1'b1;`
145			NextState_prRxBit <= `WAIT_BITS;
146			`end`
147			`WAIT_BITS:
148			`begin`
149	12	sfielding	if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
150	5	sfielding	`begin`
151	12	sfielding	NextState_prRxBit <= `DATA_RX_CHK_SE0;
152	5	sfielding	`next_RxBits <= RxBitsIn;`
153			`next_processRxBitRdy <= 1'b0;`
154			`end`
155	12	sfielding	else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
156	5	sfielding	`begin`
157	12	sfielding	NextState_prRxBit <= `RES_RX_CHK;
158	5	sfielding	`next_RxBits <= RxBitsIn;`
159			`next_processRxBitRdy <= 1'b0;`
160			`end`
161	12	sfielding	else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
162	5	sfielding	`begin`
163	12	sfielding	NextState_prRxBit <= `RES_END_CHK1;
164	5	sfielding	`next_RxBits <= RxBitsIn;`
165			`next_processRxBitRdy <= 1'b0;`
166			`end`
167	12	sfielding	else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
168	5	sfielding	`begin`
169	12	sfielding	NextState_prRxBit <= `IDLE_CHK_KBIT;
170	5	sfielding	`next_RxBits <= RxBitsIn;`
171			`next_processRxBitRdy <= 1'b0;`
172			`end`
173			`end`
174			`IDLE_FIRST_BIT:
175			`begin`
176			`next_processRxByteWEn <= 1'b0;`
177			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
178	12	sfielding	`next_RXSameBitCount <= 4'h0;`
179	5	sfielding	`next_RXBitCount <= 4'h1;`
180			`next_oldRXBits <= RxBits;`
181			`//zero is always the first RZ data bit of a new packet`
182			`next_RXByte <= 8'h00;`
183			NextState_prRxBit <= `WAIT_BITS;
184			`next_processRxBitRdy <= 1'b1;`
185			`end`
186			`IDLE_CHK_KBIT:
187			`begin`
188	14	sfielding	`if ((RxBits == KBit) && (RxWireActive == 1'b1))`
189	5	sfielding	`begin`
190			NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
191			`end`
192			`else`
193			`begin`
194			NextState_prRxBit <= `WAIT_BITS;
195			`next_processRxBitRdy <= 1'b1;`
196			`end`
197			`end`
198			`IDLE_WAIT_PRB_RDY:
199			`begin`
200			`if (processRxByteRdy == 1'b1)`
201			`begin`
202			NextState_prRxBit <= `IDLE_FIRST_BIT;
203			`next_RxDataOut <= 8'h00;`
204			`//redundant data`
205			next_RxCtrlOut <= `DATA_START;
206			`//start of packet`
207			`next_processRxByteWEn <= 1'b1;`
208			`end`
209			`end`
210			`DATA_RX_LAST_BIT:
211			`begin`
212			`next_processRxByteWEn <= 1'b0;`
213			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
214			NextState_prRxBit <= `WAIT_BITS;
215			`next_processRxBitRdy <= 1'b1;`
216			`end`
217			`DATA_RX_CHK_SE0:
218			`begin`
219			`next_bitStuffError <= 1'b0;`
220			if (RxBits == `SE0)
221			`begin`
222			NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
223			`end`
224			`else`
225			`begin`
226			NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
227			`if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then`
228			`begin`
229			`next_RXSameBitCount <= RXSameBitCount + 1'b1;`
230			`//inc 'RXSameBitCount'`
231	12	sfielding	if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
232	5	sfielding	`next_bitStuffError <= 1'b1;`
233			`//flag 'bitStuffError'`
234			`else //else no bit stuffing error`
235			`begin`
236			`next_RXBitCount <= RXBitCount + 1'b1;`
237	12	sfielding	if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
238	5	sfielding	`next_processRxBitRdy <= 1'b1;`
239			`//early indication of ready`
240			`end`
241			`next_RXByte <= { 1'b1, RXByte[7:1]};`
242			`//RZ bit <= 1 (ie no change in 'RxBits')`
243			`end`
244			`end`
245			`else //else current 'RxBits' are different from old 'RxBits'`
246			`begin`
247			if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
248			`begin`
249			`next_RXBitCount <= RXBitCount + 1'b1;`
250			`if (RXBitCount != 4'h7) begin`
251			`next_processRxBitRdy <= 1'b1;`
252			`//early indication of ready`
253			`end`
254			`next_RXByte <= {1'b0, RXByte[7:1]};`
255			`//RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')`
256			`end`
257	12	sfielding	`next_RXSameBitCount <= 4'h0;`
258	5	sfielding	`//reset 'RXSameBitCount'`
259			`end`
260			`next_oldRXBits <= RxBits;`
261			`end`
262			`end`
263			`DATA_RX_WAIT_PRB_RDY:
264			`begin`
265			`if (processRxByteRdy == 1'b1)`
266			`begin`
267			NextState_prRxBit <= `DATA_RX_LAST_BIT;
268			`next_RxDataOut <= 8'h00;`
269			`//redundant data`
270			next_RxCtrlOut <= `DATA_STOP;
271			`//end of packet`
272			`next_processRxByteWEn <= 1'b1;`
273			`end`
274			`end`
275			`DATA_RX_DATA_DESTUFF:
276			`begin`
277			`if (RXBitCount == 4'h8 & bitStuffError == 1'b0)`
278			`begin`
279			NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
280			`end`
281			`else if (bitStuffError == 1'b1)`
282			`begin`
283			NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
284			`end`
285			`else`
286			`begin`
287			NextState_prRxBit <= `WAIT_BITS;
288			`next_processRxBitRdy <= 1'b1;`
289			`end`
290			`end`
291			`DATA_RX_BYTE_SEND2:
292			`begin`
293			`next_processRxByteWEn <= 1'b0;`
294			NextState_prRxBit <= `WAIT_BITS;
295			`next_processRxBitRdy <= 1'b1;`
296			`end`
297			`DATA_RX_BYTE_WAIT_RDY:
298			`begin`
299			`if (processRxByteRdy == 1'b1)`
300			`begin`
301			NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
302			`next_RXBitCount <= 4'h0;`
303			`next_RxDataOut <= RXByte;`
304			next_RxCtrlOut <= `DATA_STREAM;
305			`next_processRxByteWEn <= 1'b1;`
306			`end`
307			`end`
308			`DATA_RX_ERROR_CHK_RES:
309			`begin`
310			`next_processRxByteWEn <= 1'b0;`
311			`if (RxBits == JBit) //if current bit is a JBit, then`
312			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
313			`//next state is idle`
314			`else //else`
315			`begin`
316			next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
317			`//check for resume`
318	14	sfielding	`next_resumeWaitCnt <= 5'h0;`
319	5	sfielding	`end`
320			NextState_prRxBit <= `WAIT_BITS;
321			`next_processRxBitRdy <= 1'b1;`
322			`end`
323			`DATA_RX_ERROR_WAIT_RDY:
324			`begin`
325			`if (processRxByteRdy == 1'b1)`
326			`begin`
327			NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
328			`next_RxDataOut <= 8'h00;`
329			`//redundant data`
330			next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
331			`next_processRxByteWEn <= 1'b1;`
332			`end`
333			`end`
334			`RES_RX_CHK:
335			`begin`
336			`if (RxBits != KBit) //can only be a resume if line remains in Kbit state`
337			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
338			`else`
339			`begin`
340			`next_resumeWaitCnt <= resumeWaitCnt + 1'b1;`
341			`//if we've waited long enough, then`
342	14	sfielding	if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
343	5	sfielding	`begin`
344			next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
345			`next_resumeDetected <= 1'b1;`
346			`//report resume detected`
347			`end`
348			`end`
349			NextState_prRxBit <= `WAIT_BITS;
350			`next_processRxBitRdy <= 1'b1;`
351			`end`
352			`RES_END_CHK1:
353			`begin`
354			`if (RxBits != KBit) //line must leave KBit state for the end of resume`
355			`begin`
356			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
357			`next_resumeDetected <= 1'b0;`
358			`//clear resume detected flag`
359			`end`
360			NextState_prRxBit <= `WAIT_BITS;
361			`next_processRxBitRdy <= 1'b1;`
362			`end`
363			`endcase`
364			`end`
365
366			`// Current State Logic (sequential)`
367			`always @ (posedge clk)`
368			`begin`
369			`if (rst)`
370			CurrState_prRxBit <= `START;
371			`else`
372			`CurrState_prRxBit <= NextState_prRxBit;`
373			`end`
374
375			`// Registered outputs logic`
376			`always @ (posedge clk)`
377			`begin`
378			`if (rst)`
379			`begin`
380			`processRxByteWEn <= 1'b0;`
381			`RxCtrlOut <= 8'h00;`
382			`RxDataOut <= 8'h00;`
383			`resumeDetected <= 1'b0;`
384			`processRxBitRdy <= 1'b1;`
385			RXBitStMachCurrState <= `IDLE_BIT_ST;
386			`RxBits <= 2'b00;`
387			`RXSameBitCount <= 4'h0;`
388			`RXBitCount <= 4'h0;`
389			`oldRXBits <= 2'b00;`
390			`RXByte <= 8'h00;`
391			`bitStuffError <= 1'b0;`
392	14	sfielding	`resumeWaitCnt <= 5'h0;`
393	5	sfielding	`end`
394			`else`
395			`begin`
396			`processRxByteWEn <= next_processRxByteWEn;`
397			`RxCtrlOut <= next_RxCtrlOut;`
398			`RxDataOut <= next_RxDataOut;`
399			`resumeDetected <= next_resumeDetected;`
400			`processRxBitRdy <= next_processRxBitRdy;`
401			`RXBitStMachCurrState <= next_RXBitStMachCurrState;`
402			`RxBits <= next_RxBits;`
403			`RXSameBitCount <= next_RXSameBitCount;`
404			`RXBitCount <= next_RXBitCount;`
405			`oldRXBits <= next_oldRXBits;`
406			`RXByte <= next_RXByte;`
407			`bitStuffError <= next_bitStuffError;`
408			`resumeWaitCnt <= next_resumeWaitCnt;`
409			`end`
410			`end`
411
412	2	sfielding	`endmodule`

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