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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [processRxByte.v] - Blame information for rev 21

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processRxByte
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
input   clk;
input   [15:0]CRC16Result;
input   CRC16UpdateRdy;
input   [4:0]CRC5Result;
input   CRC5UpdateRdy;
input   processRxDataInWEn;
input   rst;
input   [7:0]RxByteIn;
input   [7:0]RxCtrlIn;
output  CRC16En;
output  CRC5_8Bit;
output  CRC5En;
output  [7:0]CRCData;
output  processRxByteRdy;
output  rstCRC;
output  [7:0]RxCtrlOut;
output  [7:0]RxDataOut;
output  RxDataOutWEn;
 
wire    clk;
reg     CRC16En, next_CRC16En;
wire    [15:0]CRC16Result;
wire    CRC16UpdateRdy;
reg     CRC5_8Bit, next_CRC5_8Bit;
reg     CRC5En, next_CRC5En;
wire    [4:0]CRC5Result;
wire    CRC5UpdateRdy;
reg     [7:0]CRCData, next_CRCData;
reg     processRxByteRdy, next_processRxByteRdy;
wire    processRxDataInWEn;
wire    rst;
reg     rstCRC, next_rstCRC;
wire    [7:0]RxByteIn;
wire    [7:0]RxCtrlIn;
reg     [7:0]RxCtrlOut, next_RxCtrlOut;
reg     [7:0]RxDataOut, next_RxDataOut;
reg     RxDataOutWEn, next_RxDataOutWEn;
 
// diagram signals declarations
reg ACKRxed, next_ACKRxed;
reg bitStuffError, next_bitStuffError;
reg CRCError, next_CRCError;
reg dataSequence, next_dataSequence;
reg NAKRxed, next_NAKRxed;
reg  [7:0]RxByte, next_RxByte;
reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
reg  [7:0]RxCtrl, next_RxCtrl;
reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
reg RxOverflow, next_RxOverflow;
reg  [7:0]RxStatus;
reg RxTimeOut, next_RxTimeOut;
reg Signal1, next_Signal1;
reg stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: prRxByte
// State codes definitions:
`define CHK_ST 4'b0000
`define START_PRBY 4'b0001
`define WAIT_BYTE 4'b0010
`define IDLE_CHK_START 4'b0011
`define CHK_SYNC_DO 4'b0100
`define CHK_PID_DO_CHK 4'b0101
`define CHK_PID_FIRST_BYTE_PROC 4'b0110
`define HSHAKE_FIN 4'b0111
`define HSHAKE_CHK 4'b1000
`define TOKEN_CHK_STRM 4'b1001
`define TOKEN_FIN 4'b1010
`define DATA_FIN 4'b1011
`define DATA_CHK_STRM 4'b1100
`define TOKEN_WAIT_CRC 4'b1101
`define DATA_WAIT_CRC 4'b1110
 
reg [3:0]CurrState_prRxByte, NextState_prRxByte;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(next_CRCError or next_bitStuffError or
next_RxOverflow or next_NAKRxed or
next_stallRxed or next_ACKRxed or
next_dataSequence)
begin
RxStatus <=
{1'b0, next_dataSequence,
next_ACKRxed,
next_stallRxed, next_NAKRxed,
next_RxOverflow,
next_bitStuffError, next_CRCError };
end
 
 
// Machine: prRxByte
 
// NextState logic (combinatorial)
always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
begin
  NextState_prRxByte <= CurrState_prRxByte;
  // Set default values for outputs and signals
  next_RxByte <= RxByte;
  next_RxCtrl <= RxCtrl;
  next_RXByteStMachCurrState <= RXByteStMachCurrState;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_RxOverflow <= RxOverflow;
  next_RxTimeOut <= RxTimeOut;
  next_NAKRxed <= NAKRxed;
  next_stallRxed <= stallRxed;
  next_ACKRxed <= ACKRxed;
  next_dataSequence <= dataSequence;
  next_RxDataOut <= RxDataOut;
  next_RxCtrlOut <= RxCtrlOut;
  next_RxDataOutWEn <= RxDataOutWEn;
  next_rstCRC <= rstCRC;
  next_CRCData <= CRCData;
  next_CRC5En <= CRC5En;
  next_CRC5_8Bit <= CRC5_8Bit;
  next_CRC16En <= CRC16En;
  next_RXDataByteCnt <= RXDataByteCnt;
  next_processRxByteRdy <= processRxByteRdy;
  case (CurrState_prRxByte)  // synopsys parallel_case full_case
    `CHK_ST:
    begin
      if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
      begin
        NextState_prRxByte <= `TOKEN_WAIT_CRC;
      end
      else if (RXByteStMachCurrState == `HS_BYTE_ST)
      begin
        NextState_prRxByte <= `HSHAKE_CHK;
      end
      else if (RXByteStMachCurrState == `CHECK_PID_ST)
      begin
        NextState_prRxByte <= `CHK_PID_DO_CHK;
      end
      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
      begin
        NextState_prRxByte <= `CHK_SYNC_DO;
      end
      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
      begin
        NextState_prRxByte <= `IDLE_CHK_START;
      end
      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
      begin
        NextState_prRxByte <= `DATA_WAIT_CRC;
      end
    end
    `START_PRBY:
    begin
      next_RxByte <= 8'h00;
      next_RxCtrl <= 8'h00;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RxOverflow <= 1'b0;
      next_RxTimeOut <= 1'b0;
      next_NAKRxed <= 1'b0;
      next_stallRxed <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      next_RxDataOut <= 8'h00;
      next_RxCtrlOut <= 8'h00;
      next_RxDataOutWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      next_CRCData <= 8'h00;
      next_CRC5En <= 1'b0;
      next_CRC5_8Bit <= 1'b0;
      next_CRC16En <= 1'b0;
      next_RXDataByteCnt <= 10'h00;
      next_processRxByteRdy <= 1'b1;
      NextState_prRxByte <= `WAIT_BYTE;
    end
    `WAIT_BYTE:
    begin
      if (processRxDataInWEn == 1'b1)
      begin
        NextState_prRxByte <= `CHK_ST;
        next_RxByte <= RxByteIn;
        next_RxCtrl <= RxCtrlIn;
        next_processRxByteRdy <= 1'b0;
      end
    end
    `HSHAKE_FIN:
    begin
      next_RxDataOutWEn <= 1'b0;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `HSHAKE_CHK:
    begin
      NextState_prRxByte <= `HSHAKE_FIN;
      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
      next_RxOverflow <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RxDataOutWEn <= 1'b1;
    end
    `CHK_PID_DO_CHK:
    begin
      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
      begin
        NextState_prRxByte <= `WAIT_BYTE;
        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
        next_processRxByteRdy <= 1'b1;
      end
      else
      begin
        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
        next_CRCError <= 1'b0;
        next_bitStuffError <= 1'b0;
        next_RxOverflow <= 1'b0;
        next_NAKRxed <= 1'b0;
        next_stallRxed <= 1'b0;
        next_ACKRxed <= 1'b0;
        next_dataSequence <= 1'b0;
        next_RxTimeOut <= 1'b0;
        next_RXDataByteCnt <= 0;
        next_RxDataOut <= RxByte;
        next_RxCtrlOut <= `RX_PACKET_START;
        next_RxDataOutWEn <= 1'b1;
        next_rstCRC <= 1'b1;
      end
    end
    `CHK_PID_FIRST_BYTE_PROC:
    begin
      next_rstCRC <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      case (RxByte[1:0] )
      `SPECIAL:                              //Special PID.
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      `TOKEN:                                //Token PID
      begin
      next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
      next_RXDataByteCnt <= 0;
      end
      `HANDSHAKE:                            //Handshake PID
      begin
      case (RxByte[3:2] )
      2'b00:
      next_ACKRxed <= 1'b1;
      2'b10:
      next_NAKRxed <= 1'b1;
      2'b11:
      next_stallRxed <= 1'b1;
      default:
      begin
      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
      end
      endcase
      next_RXByteStMachCurrState <= `HS_BYTE_ST;
      end
      `DATA:                                  //Data PID
      begin
      case (RxByte[3:2] )
      2'b00:
      next_dataSequence <= 1'b0;
      2'b10:
      next_dataSequence <= 1'b1;
      default:
      $display ("Invalid DATA PID detected in ProcessRXByte\n");
      endcase
      next_RXByteStMachCurrState <= `DATA_BYTE_ST;
      next_RXDataByteCnt <= 0;
      end
      endcase
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `DATA_FIN:
    begin
      next_CRC16En <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `DATA_CHK_STRM:
    begin
      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
      case (RxCtrl)
      `DATA_STOP:
      begin
      if (CRC16Result != 16'hb001)
      next_CRCError <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      end
      `DATA_BIT_STUFF_ERROR:
      begin
      next_bitStuffError <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      end
      `DATA_STREAM:
      begin
      next_RxDataOut <= RxByte;
      next_RxCtrlOut <= `RX_PACKET_STREAM;
      next_CRCData <= RxByte;
      next_CRC16En <= 1'b1;
      end
      endcase
      next_RxDataOutWEn <= 1'b1;
      NextState_prRxByte <= `DATA_FIN;
    end
    `DATA_WAIT_CRC:
    begin
      if (CRC16UpdateRdy == 1'b1)
      begin
        NextState_prRxByte <= `DATA_CHK_STRM;
      end
    end
    `TOKEN_CHK_STRM:
    begin
      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
      case (RxCtrl)
      `DATA_STOP:
      begin
      if (CRC5Result != 5'h6)
      next_CRCError <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      end
      `DATA_BIT_STUFF_ERROR:
      begin
      next_bitStuffError <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      end
      `DATA_STREAM:
      begin
      if (RXDataByteCnt > 10'h2)
      begin
      next_RxOverflow <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      end
      else
      begin
      next_RxDataOut <= RxByte;
      next_RxCtrlOut <= `RX_PACKET_STREAM;
      next_CRCData <= RxByte;
      next_CRC5_8Bit <= 1'b1;
      next_CRC5En <= 1'b1;
      end
      end
      endcase
      next_RxDataOutWEn <= 1'b1;
      NextState_prRxByte <= `TOKEN_FIN;
    end
    `TOKEN_FIN:
    begin
      next_CRC5En <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `TOKEN_WAIT_CRC:
    begin
      if (CRC5UpdateRdy == 1'b1)
      begin
        NextState_prRxByte <= `TOKEN_CHK_STRM;
      end
    end
    `CHK_SYNC_DO:
    begin
      if (RxByte == `SYNC_BYTE)
      next_RXByteStMachCurrState <= `CHECK_PID_ST;
      else
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `IDLE_CHK_START:
    begin
      if (RxCtrl == `DATA_START)
      next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_prRxByte <= `START_PRBY;
  else
    CurrState_prRxByte <= NextState_prRxByte;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RxDataOut <= 8'h00;
    RxCtrlOut <= 8'h00;
    RxDataOutWEn <= 1'b0;
    rstCRC <= 1'b0;
    CRCData <= 8'h00;
    CRC5En <= 1'b0;
    CRC5_8Bit <= 1'b0;
    CRC16En <= 1'b0;
    processRxByteRdy <= 1'b1;
    RxByte <= 8'h00;
    RxCtrl <= 8'h00;
    RXByteStMachCurrState <= `IDLE_BYTE_ST;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    RxOverflow <= 1'b0;
    RxTimeOut <= 1'b0;
    NAKRxed <= 1'b0;
    stallRxed <= 1'b0;
    ACKRxed <= 1'b0;
    dataSequence <= 1'b0;
    RXDataByteCnt <= 10'h00;
  end
  else
  begin
    RxDataOut <= next_RxDataOut;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOutWEn <= next_RxDataOutWEn;
    rstCRC <= next_rstCRC;
    CRCData <= next_CRCData;
    CRC5En <= next_CRC5En;
    CRC5_8Bit <= next_CRC5_8Bit;
    CRC16En <= next_CRC16En;
    processRxByteRdy <= next_processRxByteRdy;
    RxByte <= next_RxByte;
    RxCtrl <= next_RxCtrl;
    RXByteStMachCurrState <= next_RXByteStMachCurrState;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    RxOverflow <= next_RxOverflow;
    RxTimeOut <= next_RxTimeOut;
    NAKRxed <= next_NAKRxed;
    stallRxed <= next_stallRxed;
    ACKRxed <= next_ACKRxed;
    dataSequence <= next_dataSequence;
    RXDataByteCnt <= next_RXDataByteCnt;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// processRxByte`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49			`module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);`
50			`input clk;`
51			`input [15:0]CRC16Result;`
52			`input CRC16UpdateRdy;`
53			`input [4:0]CRC5Result;`
54			`input CRC5UpdateRdy;`
55			`input processRxDataInWEn;`
56			`input rst;`
57			`input [7:0]RxByteIn;`
58			`input [7:0]RxCtrlIn;`
59			`output CRC16En;`
60			`output CRC5_8Bit;`
61			`output CRC5En;`
62			`output [7:0]CRCData;`
63			`output processRxByteRdy;`
64			`output rstCRC;`
65			`output [7:0]RxCtrlOut;`
66			`output [7:0]RxDataOut;`
67			`output RxDataOutWEn;`
68
69			`wire clk;`
70			`reg CRC16En, next_CRC16En;`
71			`wire [15:0]CRC16Result;`
72			`wire CRC16UpdateRdy;`
73			`reg CRC5_8Bit, next_CRC5_8Bit;`
74			`reg CRC5En, next_CRC5En;`
75			`wire [4:0]CRC5Result;`
76			`wire CRC5UpdateRdy;`
77			`reg [7:0]CRCData, next_CRCData;`
78			`reg processRxByteRdy, next_processRxByteRdy;`
79			`wire processRxDataInWEn;`
80			`wire rst;`
81			`reg rstCRC, next_rstCRC;`
82			`wire [7:0]RxByteIn;`
83			`wire [7:0]RxCtrlIn;`
84			`reg [7:0]RxCtrlOut, next_RxCtrlOut;`
85			`reg [7:0]RxDataOut, next_RxDataOut;`
86			`reg RxDataOutWEn, next_RxDataOutWEn;`
87
88			`// diagram signals declarations`
89			`reg ACKRxed, next_ACKRxed;`
90			`reg bitStuffError, next_bitStuffError;`
91			`reg CRCError, next_CRCError;`
92			`reg dataSequence, next_dataSequence;`
93			`reg NAKRxed, next_NAKRxed;`
94			`reg [7:0]RxByte, next_RxByte;`
95			`reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;`
96			`reg [7:0]RxCtrl, next_RxCtrl;`
97			`reg [9:0]RXDataByteCnt, next_RXDataByteCnt;`
98			`reg RxOverflow, next_RxOverflow;`
99			`reg [7:0]RxStatus;`
100			`reg RxTimeOut, next_RxTimeOut;`
101			`reg Signal1, next_Signal1;`
102			`reg stallRxed, next_stallRxed;`
103
104			`// BINARY ENCODED state machine: prRxByte`
105			`// State codes definitions:`
106			`define CHK_ST 4'b0000
107			`define START_PRBY 4'b0001
108			`define WAIT_BYTE 4'b0010
109			`define IDLE_CHK_START 4'b0011
110			`define CHK_SYNC_DO 4'b0100
111			`define CHK_PID_DO_CHK 4'b0101
112			`define CHK_PID_FIRST_BYTE_PROC 4'b0110
113			`define HSHAKE_FIN 4'b0111
114			`define HSHAKE_CHK 4'b1000
115			`define TOKEN_CHK_STRM 4'b1001
116			`define TOKEN_FIN 4'b1010
117			`define DATA_FIN 4'b1011
118			`define DATA_CHK_STRM 4'b1100
119			`define TOKEN_WAIT_CRC 4'b1101
120			`define DATA_WAIT_CRC 4'b1110
121
122			`reg [3:0]CurrState_prRxByte, NextState_prRxByte;`
123
124			`// Diagram actions (continuous assignments allowed only: assign ...)`
125			`always @`
126			`(next_CRCError or next_bitStuffError or`
127			`next_RxOverflow or next_NAKRxed or`
128			`next_stallRxed or next_ACKRxed or`
129			`next_dataSequence)`
130			`begin`
131			`RxStatus <=`
132			`{1'b0, next_dataSequence,`
133			`next_ACKRxed,`
134			`next_stallRxed, next_NAKRxed,`
135			`next_RxOverflow,`
136			`next_bitStuffError, next_CRCError };`
137			`end`
138
139
140			`// Machine: prRxByte`
141
142			`// NextState logic (combinatorial)`
143			`always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)`
144			`begin`
145			`NextState_prRxByte <= CurrState_prRxByte;`
146			`// Set default values for outputs and signals`
147			`next_RxByte <= RxByte;`
148			`next_RxCtrl <= RxCtrl;`
149			`next_RXByteStMachCurrState <= RXByteStMachCurrState;`
150			`next_CRCError <= CRCError;`
151			`next_bitStuffError <= bitStuffError;`
152			`next_RxOverflow <= RxOverflow;`
153			`next_RxTimeOut <= RxTimeOut;`
154			`next_NAKRxed <= NAKRxed;`
155			`next_stallRxed <= stallRxed;`
156			`next_ACKRxed <= ACKRxed;`
157			`next_dataSequence <= dataSequence;`
158			`next_RxDataOut <= RxDataOut;`
159			`next_RxCtrlOut <= RxCtrlOut;`
160			`next_RxDataOutWEn <= RxDataOutWEn;`
161			`next_rstCRC <= rstCRC;`
162			`next_CRCData <= CRCData;`
163			`next_CRC5En <= CRC5En;`
164			`next_CRC5_8Bit <= CRC5_8Bit;`
165			`next_CRC16En <= CRC16En;`
166			`next_RXDataByteCnt <= RXDataByteCnt;`
167			`next_processRxByteRdy <= processRxByteRdy;`
168			`case (CurrState_prRxByte) // synopsys parallel_case full_case`
169			`CHK_ST:
170			`begin`
171	18	sfielding	if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
172	5	sfielding	`begin`
173	18	sfielding	NextState_prRxByte <= `TOKEN_WAIT_CRC;
174			`end`
175			else if (RXByteStMachCurrState == `HS_BYTE_ST)
176			`begin`
177	7	sfielding	NextState_prRxByte <= `HSHAKE_CHK;
178			`end`
179	18	sfielding	else if (RXByteStMachCurrState == `CHECK_PID_ST)
180	7	sfielding	`begin`
181	18	sfielding	NextState_prRxByte <= `CHK_PID_DO_CHK;
182	5	sfielding	`end`
183	18	sfielding	else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
184	5	sfielding	`begin`
185	18	sfielding	NextState_prRxByte <= `CHK_SYNC_DO;
186	5	sfielding	`end`
187	7	sfielding	else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
188	5	sfielding	`begin`
189	7	sfielding	NextState_prRxByte <= `IDLE_CHK_START;
190	5	sfielding	`end`
191	18	sfielding	else if (RXByteStMachCurrState == `DATA_BYTE_ST)
192	5	sfielding	`begin`
193	18	sfielding	NextState_prRxByte <= `DATA_WAIT_CRC;
194	5	sfielding	`end`
195			`end`
196			`START_PRBY:
197			`begin`
198			`next_RxByte <= 8'h00;`
199			`next_RxCtrl <= 8'h00;`
200			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
201			`next_CRCError <= 1'b0;`
202			`next_bitStuffError <= 1'b0;`
203			`next_RxOverflow <= 1'b0;`
204			`next_RxTimeOut <= 1'b0;`
205			`next_NAKRxed <= 1'b0;`
206			`next_stallRxed <= 1'b0;`
207			`next_ACKRxed <= 1'b0;`
208			`next_dataSequence <= 1'b0;`
209			`next_RxDataOut <= 8'h00;`
210			`next_RxCtrlOut <= 8'h00;`
211			`next_RxDataOutWEn <= 1'b0;`
212			`next_rstCRC <= 1'b0;`
213			`next_CRCData <= 8'h00;`
214			`next_CRC5En <= 1'b0;`
215			`next_CRC5_8Bit <= 1'b0;`
216			`next_CRC16En <= 1'b0;`
217			`next_RXDataByteCnt <= 10'h00;`
218			`next_processRxByteRdy <= 1'b1;`
219			NextState_prRxByte <= `WAIT_BYTE;
220			`end`
221			`WAIT_BYTE:
222			`begin`
223			`if (processRxDataInWEn == 1'b1)`
224			`begin`
225			NextState_prRxByte <= `CHK_ST;
226			`next_RxByte <= RxByteIn;`
227			`next_RxCtrl <= RxCtrlIn;`
228			`next_processRxByteRdy <= 1'b0;`
229			`end`
230			`end`
231			`HSHAKE_FIN:
232			`begin`
233			`next_RxDataOutWEn <= 1'b0;`
234			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
235			NextState_prRxByte <= `WAIT_BYTE;
236			`next_processRxByteRdy <= 1'b1;`
237			`end`
238			`HSHAKE_CHK:
239			`begin`
240			NextState_prRxByte <= `HSHAKE_FIN;
241			if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
242			`next_RxOverflow <= 1'b1;`
243			`next_RxDataOut <= RxStatus;`
244			next_RxCtrlOut <= `RX_PACKET_STOP;
245			`next_RxDataOutWEn <= 1'b1;`
246			`end`
247			`CHK_PID_DO_CHK:
248			`begin`
249			`if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)`
250			`begin`
251			NextState_prRxByte <= `WAIT_BYTE;
252			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
253			`next_processRxByteRdy <= 1'b1;`
254			`end`
255			`else`
256			`begin`
257			NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
258			`next_CRCError <= 1'b0;`
259			`next_bitStuffError <= 1'b0;`
260			`next_RxOverflow <= 1'b0;`
261			`next_NAKRxed <= 1'b0;`
262			`next_stallRxed <= 1'b0;`
263			`next_ACKRxed <= 1'b0;`
264			`next_dataSequence <= 1'b0;`
265			`next_RxTimeOut <= 1'b0;`
266			`next_RXDataByteCnt <= 0;`
267			`next_RxDataOut <= RxByte;`
268			next_RxCtrlOut <= `RX_PACKET_START;
269			`next_RxDataOutWEn <= 1'b1;`
270			`next_rstCRC <= 1'b1;`
271			`end`
272			`end`
273			`CHK_PID_FIRST_BYTE_PROC:
274			`begin`
275			`next_rstCRC <= 1'b0;`
276			`next_RxDataOutWEn <= 1'b0;`
277			`case (RxByte[1:0] )`
278			`SPECIAL: //Special PID.
279			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
280			`TOKEN: //Token PID
281			`begin`
282			next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
283			`next_RXDataByteCnt <= 0;`
284			`end`
285			`HANDSHAKE: //Handshake PID
286			`begin`
287			`case (RxByte[3:2] )`
288			`2'b00:`
289			`next_ACKRxed <= 1'b1;`
290			`2'b10:`
291			`next_NAKRxed <= 1'b1;`
292			`2'b11:`
293			`next_stallRxed <= 1'b1;`
294			`default:`
295			`begin`
296			`$display ("Invalid Handshake PID detected in ProcessRXByte\n");`
297			`end`
298			`endcase`
299			next_RXByteStMachCurrState <= `HS_BYTE_ST;
300			`end`
301			`DATA: //Data PID
302			`begin`
303			`case (RxByte[3:2] )`
304			`2'b00:`
305			`next_dataSequence <= 1'b0;`
306			`2'b10:`
307			`next_dataSequence <= 1'b1;`
308			`default:`
309			`$display ("Invalid DATA PID detected in ProcessRXByte\n");`
310			`endcase`
311			next_RXByteStMachCurrState <= `DATA_BYTE_ST;
312			`next_RXDataByteCnt <= 0;`
313			`end`
314			`endcase`
315			NextState_prRxByte <= `WAIT_BYTE;
316			`next_processRxByteRdy <= 1'b1;`
317			`end`
318			`DATA_FIN:
319			`begin`
320			`next_CRC16En <= 1'b0;`
321			`next_RxDataOutWEn <= 1'b0;`
322			NextState_prRxByte <= `WAIT_BYTE;
323			`next_processRxByteRdy <= 1'b1;`
324			`end`
325			`DATA_CHK_STRM:
326			`begin`
327			`next_RXDataByteCnt <= RXDataByteCnt + 1'b1;`
328			`case (RxCtrl)`
329			`DATA_STOP:
330			`begin`
331			`if (CRC16Result != 16'hb001)`
332			`next_CRCError <= 1'b1;`
333			`next_RxDataOut <= RxStatus;`
334			next_RxCtrlOut <= `RX_PACKET_STOP;
335			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
336			`end`
337			`DATA_BIT_STUFF_ERROR:
338			`begin`
339			`next_bitStuffError <= 1'b1;`
340			`next_RxDataOut <= RxStatus;`
341			next_RxCtrlOut <= `RX_PACKET_STOP;
342			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
343			`end`
344			`DATA_STREAM:
345			`begin`
346			`next_RxDataOut <= RxByte;`
347			next_RxCtrlOut <= `RX_PACKET_STREAM;
348			`next_CRCData <= RxByte;`
349			`next_CRC16En <= 1'b1;`
350			`end`
351			`endcase`
352			`next_RxDataOutWEn <= 1'b1;`
353			NextState_prRxByte <= `DATA_FIN;
354			`end`
355			`DATA_WAIT_CRC:
356			`begin`
357			`if (CRC16UpdateRdy == 1'b1)`
358			`begin`
359			NextState_prRxByte <= `DATA_CHK_STRM;
360			`end`
361			`end`
362			`TOKEN_CHK_STRM:
363			`begin`
364			`next_RXDataByteCnt <= RXDataByteCnt + 1'b1;`
365			`case (RxCtrl)`
366			`DATA_STOP:
367			`begin`
368			`if (CRC5Result != 5'h6)`
369			`next_CRCError <= 1'b1;`
370			`next_RxDataOut <= RxStatus;`
371			next_RxCtrlOut <= `RX_PACKET_STOP;
372			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
373			`end`
374			`DATA_BIT_STUFF_ERROR:
375			`begin`
376			`next_bitStuffError <= 1'b1;`
377			`next_RxDataOut <= RxStatus;`
378			next_RxCtrlOut <= `RX_PACKET_STOP;
379			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
380			`end`
381			`DATA_STREAM:
382			`begin`
383			`if (RXDataByteCnt > 10'h2)`
384			`begin`
385			`next_RxOverflow <= 1'b1;`
386			`next_RxDataOut <= RxStatus;`
387			next_RxCtrlOut <= `RX_PACKET_STOP;
388			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
389			`end`
390			`else`
391			`begin`
392			`next_RxDataOut <= RxByte;`
393			next_RxCtrlOut <= `RX_PACKET_STREAM;
394			`next_CRCData <= RxByte;`
395			`next_CRC5_8Bit <= 1'b1;`
396			`next_CRC5En <= 1'b1;`
397			`end`
398			`end`
399			`endcase`
400			`next_RxDataOutWEn <= 1'b1;`
401			NextState_prRxByte <= `TOKEN_FIN;
402			`end`
403			`TOKEN_FIN:
404			`begin`
405			`next_CRC5En <= 1'b0;`
406			`next_RxDataOutWEn <= 1'b0;`
407			NextState_prRxByte <= `WAIT_BYTE;
408			`next_processRxByteRdy <= 1'b1;`
409			`end`
410			`TOKEN_WAIT_CRC:
411			`begin`
412			`if (CRC5UpdateRdy == 1'b1)`
413			`begin`
414			NextState_prRxByte <= `TOKEN_CHK_STRM;
415			`end`
416			`end`
417			`CHK_SYNC_DO:
418			`begin`
419			if (RxByte == `SYNC_BYTE)
420			next_RXByteStMachCurrState <= `CHECK_PID_ST;
421			`else`
422			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
423			NextState_prRxByte <= `WAIT_BYTE;
424			`next_processRxByteRdy <= 1'b1;`
425			`end`
426			`IDLE_CHK_START:
427			`begin`
428			if (RxCtrl == `DATA_START)
429			next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
430			NextState_prRxByte <= `WAIT_BYTE;
431			`next_processRxByteRdy <= 1'b1;`
432			`end`
433			`endcase`
434			`end`
435
436			`// Current State Logic (sequential)`
437			`always @ (posedge clk)`
438			`begin`
439			`if (rst)`
440			CurrState_prRxByte <= `START_PRBY;
441			`else`
442			`CurrState_prRxByte <= NextState_prRxByte;`
443			`end`
444
445			`// Registered outputs logic`
446			`always @ (posedge clk)`
447			`begin`
448			`if (rst)`
449			`begin`
450			`RxDataOut <= 8'h00;`
451			`RxCtrlOut <= 8'h00;`
452			`RxDataOutWEn <= 1'b0;`
453			`rstCRC <= 1'b0;`
454			`CRCData <= 8'h00;`
455			`CRC5En <= 1'b0;`
456			`CRC5_8Bit <= 1'b0;`
457			`CRC16En <= 1'b0;`
458			`processRxByteRdy <= 1'b1;`
459			`RxByte <= 8'h00;`
460			`RxCtrl <= 8'h00;`
461			RXByteStMachCurrState <= `IDLE_BYTE_ST;
462			`CRCError <= 1'b0;`
463			`bitStuffError <= 1'b0;`
464			`RxOverflow <= 1'b0;`
465			`RxTimeOut <= 1'b0;`
466			`NAKRxed <= 1'b0;`
467			`stallRxed <= 1'b0;`
468			`ACKRxed <= 1'b0;`
469			`dataSequence <= 1'b0;`
470			`RXDataByteCnt <= 10'h00;`
471			`end`
472			`else`
473			`begin`
474			`RxDataOut <= next_RxDataOut;`
475			`RxCtrlOut <= next_RxCtrlOut;`
476			`RxDataOutWEn <= next_RxDataOutWEn;`
477			`rstCRC <= next_rstCRC;`
478			`CRCData <= next_CRCData;`
479			`CRC5En <= next_CRC5En;`
480			`CRC5_8Bit <= next_CRC5_8Bit;`
481			`CRC16En <= next_CRC16En;`
482			`processRxByteRdy <= next_processRxByteRdy;`
483			`RxByte <= next_RxByte;`
484			`RxCtrl <= next_RxCtrl;`
485			`RXByteStMachCurrState <= next_RXByteStMachCurrState;`
486			`CRCError <= next_CRCError;`
487			`bitStuffError <= next_bitStuffError;`
488			`RxOverflow <= next_RxOverflow;`
489			`RxTimeOut <= next_RxTimeOut;`
490			`NAKRxed <= next_NAKRxed;`
491			`stallRxed <= next_stallRxed;`
492			`ACKRxed <= next_ACKRxed;`
493			`dataSequence <= next_dataSequence;`
494			`RXDataByteCnt <= next_RXDataByteCnt;`
495			`end`
496			`end`
497
498	2	sfielding	`endmodule`

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