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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Blame information for rev 21

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processTxByte
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
input   clk;
input   [1:0]JBit;
input   [1:0]KBit;
input   processTxByteWEn;
input   rst;
input   [7:0]TxByteCtrlIn;
input   TxByteFullSpeedRateIn;
input   [7:0]TxByteIn;
input   USBWireGnt;
input   USBWireRdy;
output  processTxByteRdy;
output  USBWireCtrl;
output  [1:0]USBWireData;
output  USBWireFullSpeedRate;
output  USBWireReq;
output  USBWireWEn;
 
wire    clk;
wire    [1:0]JBit;
wire    [1:0]KBit;
reg     processTxByteRdy, next_processTxByteRdy;
wire    processTxByteWEn;
wire    rst;
wire    [7:0]TxByteCtrlIn;
wire    TxByteFullSpeedRateIn;
wire    [7:0]TxByteIn;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0]USBWireData, next_USBWireData;
reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
 
// diagram signals declarations
reg  [3:0]i, next_i;
reg  [7:0]TxByte, next_TxByte;
reg  [7:0]TxByteCtrl, next_TxByteCtrl;
reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
reg  [1:0]TXLineState, next_TXLineState;
reg  [3:0]TXOneCount, next_TXOneCount;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 5'b00000
`define PTBY_WAIT_EN 5'b00001
`define SEND_BYTE_UPDATE_BYTE 5'b00010
`define SEND_BYTE_WAIT_RDY 5'b00011
`define SEND_BYTE_CHK 5'b00100
`define SEND_BYTE_BIT_STUFF 5'b00101
`define SEND_BYTE_WAIT_RDY2 5'b00110
`define SEND_BYTE_CHK_FIN 5'b00111
`define PTBY_WAIT_GNT 5'b01000
`define STOP_SND_SE0_2 5'b01001
`define STOP_SND_SE0_1 5'b01010
`define STOP_CHK 5'b01011
`define STOP_SND_J 5'b01100
`define STOP_SND_IDLE 5'b01101
`define STOP_FIN 5'b01110
`define WAIT_RDY_WIRE 5'b01111
`define WAIT_RDY_PKT 5'b10000
`define LS_START_SND_IDLE3 5'b10001
`define LS_START_SND_J1 5'b10010
`define LS_START_SND_IDLE1 5'b10011
`define LS_START_SND_IDLE2 5'b10100
`define LS_START_FIN 5'b10101
`define LS_START_W_RDY1 5'b10110
`define LS_START_W_RDY2 5'b10111
`define LS_START_W_RDY3 5'b11000
`define STOP_W_RDY1 5'b11001
`define STOP_W_RDY2 5'b11010
`define STOP_W_RDY3 5'b11011
`define STOP_W_RDY4 5'b11100
 
reg [4:0]CurrState_prcTxB, NextState_prcTxB;
 
 
// Machine: prcTxB
 
// NextState logic (combinatorial)
always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
begin
  NextState_prcTxB <= CurrState_prcTxB;
  // Set default values for outputs and signals
  next_processTxByteRdy <= processTxByteRdy;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_USBWireReq <= USBWireReq;
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_TxByte <= TxByte;
  next_TxByteCtrl <= TxByteCtrl;
  next_TXLineState <= TXLineState;
  next_TXOneCount <= TXOneCount;
  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
  case (CurrState_prcTxB)  // synopsys parallel_case full_case
    `START_PTBY:
    begin
      next_processTxByteRdy <= 1'b0;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_i <= 4'h0;
      next_TxByte <= 8'h00;
      next_TxByteCtrl <= 8'h00;
      next_TXLineState <= 2'b0;
      next_TXOneCount <= 4'h0;
      next_USBWireFullSpeedRate <= 1'b0;
      next_TxByteFullSpeedRate <= 1'b0;
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `PTBY_WAIT_EN:
    begin
      next_processTxByteRdy <= 1'b1;
      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
      begin
        NextState_prcTxB <= `PTBY_WAIT_GNT;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
        next_TXOneCount <= 4'h0;
        next_TXLineState <= JBit;
        next_USBWireReq <= 1'b1;
      end
      else if (processTxByteWEn == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
        next_i <= 4'h0;
      end
    end
    `PTBY_WAIT_GNT:
    begin
      if (USBWireGnt == 1'b1)
      begin
        NextState_prcTxB <= `WAIT_RDY_WIRE;
      end
    end
    `WAIT_RDY_WIRE:
    begin
      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE1;
      end
      else if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `WAIT_RDY_PKT;
        //actively drive the first J bit
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `WAIT_RDY_PKT:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      next_i <= 4'h0;
    end
    `SEND_BYTE_UPDATE_BYTE:
    begin
      next_i <= i + 1'b1;
      next_TxByte <= {1'b0, TxByte[7:1] };
      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
      next_TXOneCount <= TXOneCount + 1'b1;
      //increment 'TXOneCount'
      else                                        //else this is a zero bit
      begin
      next_TXOneCount <= 4'h0;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
      next_TXLineState <= KBit;
      //toggle the line state
      else
      next_TXLineState <= JBit;
      end
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
    end
    `SEND_BYTE_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `SEND_BYTE_CHK:
    begin
      next_USBWireWEn <= 1'b0;
      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
      begin
        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
      end
      else if (i != 4'h8)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      end
      else
      begin
        NextState_prcTxB <= `STOP_CHK;
      end
    end
    `SEND_BYTE_BIT_STUFF:
    begin
      next_TXOneCount <= 4'h0;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
      next_TXLineState <= KBit;
      //toggle the line state
      else
      next_TXLineState <= JBit;
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
    end
    `SEND_BYTE_WAIT_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `SEND_BYTE_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (i == 4'h8)
      begin
        NextState_prcTxB <= `STOP_CHK;
      end
      else
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      end
    end
    `STOP_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `STOP_W_RDY2;
    end
    `STOP_SND_SE0_1:
    begin
      NextState_prcTxB <= `STOP_W_RDY1;
    end
    `STOP_CHK:
    begin
      if (TxByteCtrl == `DATA_STOP)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_1;
      end
      else
      begin
        NextState_prcTxB <= `PTBY_WAIT_EN;
      end
    end
    `STOP_SND_J:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `STOP_W_RDY3;
    end
    `STOP_SND_IDLE:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `STOP_W_RDY4;
    end
    `STOP_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      //release the wire
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `STOP_W_RDY1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_W_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_J;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_W_RDY3:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_IDLE;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_W_RDY4:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_SND_IDLE3:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `LS_START_W_RDY2;
    end
    `LS_START_SND_J1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `LS_START_W_RDY3;
    end
    `LS_START_SND_IDLE1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_SND_IDLE2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `LS_START_W_RDY1;
    end
    `LS_START_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      next_i <= 4'h0;
    end
    `LS_START_W_RDY1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE3;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_W_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_J1;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_W_RDY3:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_FIN;
        //Drive the first JBit
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_prcTxB <= `START_PTBY;
  else
    CurrState_prcTxB <= NextState_prcTxB;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    processTxByteRdy <= 1'b0;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    USBWireReq <= 1'b0;
    USBWireWEn <= 1'b0;
    USBWireFullSpeedRate <= 1'b0;
    i <= 4'h0;
    TxByte <= 8'h00;
    TxByteCtrl <= 8'h00;
    TXLineState <= 2'b0;
    TXOneCount <= 4'h0;
    TxByteFullSpeedRate <= 1'b0;
  end
  else
  begin
    processTxByteRdy <= next_processTxByteRdy;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    USBWireReq <= next_USBWireReq;
    USBWireWEn <= next_USBWireWEn;
    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
    i <= next_i;
    TxByte <= next_TxByte;
    TxByteCtrl <= next_TxByteCtrl;
    TXLineState <= next_TXLineState;
    TXOneCount <= next_TXOneCount;
    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// processTxByte`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49	14	sfielding	`module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);`
50	5	sfielding	`input clk;`
51			`input [1:0]JBit;`
52			`input [1:0]KBit;`
53			`input processTxByteWEn;`
54			`input rst;`
55			`input [7:0]TxByteCtrlIn;`
56	14	sfielding	`input TxByteFullSpeedRateIn;`
57	5	sfielding	`input [7:0]TxByteIn;`
58			`input USBWireGnt;`
59			`input USBWireRdy;`
60			`output processTxByteRdy;`
61			`output USBWireCtrl;`
62			`output [1:0]USBWireData;`
63	14	sfielding	`output USBWireFullSpeedRate;`
64	5	sfielding	`output USBWireReq;`
65			`output USBWireWEn;`
66
67			`wire clk;`
68			`wire [1:0]JBit;`
69			`wire [1:0]KBit;`
70			`reg processTxByteRdy, next_processTxByteRdy;`
71			`wire processTxByteWEn;`
72			`wire rst;`
73			`wire [7:0]TxByteCtrlIn;`
74	14	sfielding	`wire TxByteFullSpeedRateIn;`
75	5	sfielding	`wire [7:0]TxByteIn;`
76			`reg USBWireCtrl, next_USBWireCtrl;`
77			`reg [1:0]USBWireData, next_USBWireData;`
78	14	sfielding	`reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;`
79	5	sfielding	`wire USBWireGnt;`
80			`wire USBWireRdy;`
81			`reg USBWireReq, next_USBWireReq;`
82			`reg USBWireWEn, next_USBWireWEn;`
83
84			`// diagram signals declarations`
85			`reg [3:0]i, next_i;`
86			`reg [7:0]TxByte, next_TxByte;`
87			`reg [7:0]TxByteCtrl, next_TxByteCtrl;`
88	14	sfielding	`reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;`
89	5	sfielding	`reg [1:0]TXLineState, next_TXLineState;`
90			`reg [3:0]TXOneCount, next_TXOneCount;`
91
92			`// BINARY ENCODED state machine: prcTxB`
93			`// State codes definitions:`
94	9	sfielding	`define START_PTBY 5'b00000
95			`define PTBY_WAIT_EN 5'b00001
96			`define SEND_BYTE_UPDATE_BYTE 5'b00010
97			`define SEND_BYTE_WAIT_RDY 5'b00011
98			`define SEND_BYTE_CHK 5'b00100
99			`define SEND_BYTE_BIT_STUFF 5'b00101
100			`define SEND_BYTE_WAIT_RDY2 5'b00110
101			`define SEND_BYTE_CHK_FIN 5'b00111
102			`define PTBY_WAIT_GNT 5'b01000
103			`define STOP_SND_SE0_2 5'b01001
104			`define STOP_SND_SE0_1 5'b01010
105			`define STOP_CHK 5'b01011
106			`define STOP_SND_J 5'b01100
107			`define STOP_SND_IDLE 5'b01101
108			`define STOP_FIN 5'b01110
109			`define WAIT_RDY_WIRE 5'b01111
110			`define WAIT_RDY_PKT 5'b10000
111			`define LS_START_SND_IDLE3 5'b10001
112			`define LS_START_SND_J1 5'b10010
113			`define LS_START_SND_IDLE1 5'b10011
114			`define LS_START_SND_IDLE2 5'b10100
115			`define LS_START_FIN 5'b10101
116	14	sfielding	`define LS_START_W_RDY1 5'b10110
117			`define LS_START_W_RDY2 5'b10111
118			`define LS_START_W_RDY3 5'b11000
119			`define STOP_W_RDY1 5'b11001
120			`define STOP_W_RDY2 5'b11010
121			`define STOP_W_RDY3 5'b11011
122			`define STOP_W_RDY4 5'b11100
123	5	sfielding
124	9	sfielding	`reg [4:0]CurrState_prcTxB, NextState_prcTxB;`
125	5	sfielding
126
127			`// Machine: prcTxB`
128
129			`// NextState logic (combinatorial)`
130	14	sfielding	`always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)`
131	5	sfielding	`begin`
132			`NextState_prcTxB <= CurrState_prcTxB;`
133			`// Set default values for outputs and signals`
134			`next_processTxByteRdy <= processTxByteRdy;`
135			`next_USBWireData <= USBWireData;`
136			`next_USBWireCtrl <= USBWireCtrl;`
137			`next_USBWireReq <= USBWireReq;`
138			`next_USBWireWEn <= USBWireWEn;`
139			`next_i <= i;`
140			`next_TxByte <= TxByte;`
141			`next_TxByteCtrl <= TxByteCtrl;`
142			`next_TXLineState <= TXLineState;`
143			`next_TXOneCount <= TXOneCount;`
144	14	sfielding	`next_USBWireFullSpeedRate <= USBWireFullSpeedRate;`
145			`next_TxByteFullSpeedRate <= TxByteFullSpeedRate;`
146	5	sfielding	`case (CurrState_prcTxB) // synopsys parallel_case full_case`
147			`START_PTBY:
148			`begin`
149			`next_processTxByteRdy <= 1'b0;`
150			`next_USBWireData <= 2'b00;`
151			next_USBWireCtrl <= `TRI_STATE;
152			`next_USBWireReq <= 1'b0;`
153			`next_USBWireWEn <= 1'b0;`
154			`next_i <= 4'h0;`
155			`next_TxByte <= 8'h00;`
156			`next_TxByteCtrl <= 8'h00;`
157			`next_TXLineState <= 2'b0;`
158			`next_TXOneCount <= 4'h0;`
159	14	sfielding	`next_USBWireFullSpeedRate <= 1'b0;`
160			`next_TxByteFullSpeedRate <= 1'b0;`
161	5	sfielding	NextState_prcTxB <= `PTBY_WAIT_EN;
162			`end`
163			`PTBY_WAIT_EN:
164			`begin`
165			`next_processTxByteRdy <= 1'b1;`
166			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
167			`begin`
168			NextState_prcTxB <= `PTBY_WAIT_GNT;
169			`next_processTxByteRdy <= 1'b0;`
170			`next_TxByte <= TxByteIn;`
171			`next_TxByteCtrl <= TxByteCtrlIn;`
172	14	sfielding	`next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;`
173			`next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;`
174	12	sfielding	`next_TXOneCount <= 4'h0;`
175	5	sfielding	`next_TXLineState <= JBit;`
176			`next_USBWireReq <= 1'b1;`
177			`end`
178			`else if (processTxByteWEn == 1'b1)`
179			`begin`
180			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
181			`next_processTxByteRdy <= 1'b0;`
182			`next_TxByte <= TxByteIn;`
183			`next_TxByteCtrl <= TxByteCtrlIn;`
184	14	sfielding	`next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;`
185			`next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;`
186	5	sfielding	`next_i <= 4'h0;`
187			`end`
188			`end`
189			`PTBY_WAIT_GNT:
190			`begin`
191			`if (USBWireGnt == 1'b1)`
192			`begin`
193	9	sfielding	NextState_prcTxB <= `WAIT_RDY_WIRE;
194	5	sfielding	`end`
195			`end`
196	9	sfielding	`WAIT_RDY_WIRE:
197			`begin`
198	14	sfielding	`if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))`
199	9	sfielding	`begin`
200			NextState_prcTxB <= `LS_START_SND_IDLE1;
201			`end`
202			`else if (USBWireRdy == 1'b1)`
203			`begin`
204			NextState_prcTxB <= `WAIT_RDY_PKT;
205			`//actively drive the first J bit`
206			`next_USBWireData <= JBit;`
207			next_USBWireCtrl <= `DRIVE;
208			`next_USBWireWEn <= 1'b1;`
209			`end`
210			`end`
211			`WAIT_RDY_PKT:
212			`begin`
213			`next_USBWireWEn <= 1'b0;`
214			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
215			`next_i <= 4'h0;`
216			`end`
217	5	sfielding	`SEND_BYTE_UPDATE_BYTE:
218			`begin`
219			`next_i <= i + 1'b1;`
220			`next_TxByte <= {1'b0, TxByte[7:1] };`
221			`if (TxByte[0] == 1'b1) //If this bit is 1, then`
222			`next_TXOneCount <= TXOneCount + 1'b1;`
223			`//increment 'TXOneCount'`
224			`else //else this is a zero bit`
225			`begin`
226	12	sfielding	`next_TXOneCount <= 4'h0;`
227	5	sfielding	`//reset 'TXOneCount'`
228			`if (TXLineState == JBit)`
229			`next_TXLineState <= KBit;`
230			`//toggle the line state`
231			`else`
232			`next_TXLineState <= JBit;`
233			`end`
234			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
235			`end`
236			`SEND_BYTE_WAIT_RDY:
237			`begin`
238			`if (USBWireRdy == 1'b1)`
239			`begin`
240			NextState_prcTxB <= `SEND_BYTE_CHK;
241			`next_USBWireWEn <= 1'b1;`
242			`next_USBWireData <= TXLineState;`
243			next_USBWireCtrl <= `DRIVE;
244			`end`
245			`end`
246			`SEND_BYTE_CHK:
247			`begin`
248			`next_USBWireWEn <= 1'b0;`
249	12	sfielding	if (TXOneCount == `MAX_CONSEC_SAME_BITS)
250	5	sfielding	`begin`
251			NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
252			`end`
253			`else if (i != 4'h8)`
254			`begin`
255			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
256			`end`
257			`else`
258			`begin`
259			NextState_prcTxB <= `STOP_CHK;
260			`end`
261			`end`
262			`SEND_BYTE_BIT_STUFF:
263			`begin`
264	12	sfielding	`next_TXOneCount <= 4'h0;`
265	5	sfielding	`//reset 'TXOneCount'`
266			`if (TXLineState == JBit)`
267			`next_TXLineState <= KBit;`
268			`//toggle the line state`
269			`else`
270			`next_TXLineState <= JBit;`
271			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
272			`end`
273			`SEND_BYTE_WAIT_RDY2:
274			`begin`
275			`if (USBWireRdy == 1'b1)`
276			`begin`
277			NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
278			`next_USBWireWEn <= 1'b1;`
279			`next_USBWireData <= TXLineState;`
280			next_USBWireCtrl <= `DRIVE;
281			`end`
282			`end`
283			`SEND_BYTE_CHK_FIN:
284			`begin`
285			`next_USBWireWEn <= 1'b0;`
286			`if (i == 4'h8)`
287			`begin`
288			NextState_prcTxB <= `STOP_CHK;
289			`end`
290			`else`
291			`begin`
292			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
293			`end`
294			`end`
295			`STOP_SND_SE0_2:
296			`begin`
297			`next_USBWireWEn <= 1'b0;`
298	14	sfielding	NextState_prcTxB <= `STOP_W_RDY2;
299	5	sfielding	`end`
300			`STOP_SND_SE0_1:
301			`begin`
302	14	sfielding	NextState_prcTxB <= `STOP_W_RDY1;
303	5	sfielding	`end`
304			`STOP_CHK:
305			`begin`
306			if (TxByteCtrl == `DATA_STOP)
307			`begin`
308			NextState_prcTxB <= `STOP_SND_SE0_1;
309			`end`
310			`else`
311			`begin`
312			NextState_prcTxB <= `PTBY_WAIT_EN;
313			`end`
314			`end`
315			`STOP_SND_J:
316			`begin`
317			`next_USBWireWEn <= 1'b0;`
318	14	sfielding	NextState_prcTxB <= `STOP_W_RDY3;
319			`end`
320			`STOP_SND_IDLE:
321			`begin`
322			`next_USBWireWEn <= 1'b0;`
323			NextState_prcTxB <= `STOP_W_RDY4;
324			`end`
325			`STOP_FIN:
326			`begin`
327			`next_USBWireWEn <= 1'b0;`
328			`next_USBWireReq <= 1'b0;`
329			`//release the wire`
330			NextState_prcTxB <= `PTBY_WAIT_EN;
331			`end`
332			`STOP_W_RDY1:
333			`begin`
334	5	sfielding	`if (USBWireRdy == 1'b1)`
335			`begin`
336	14	sfielding	NextState_prcTxB <= `STOP_SND_SE0_2;
337			`next_USBWireWEn <= 1'b1;`
338			next_USBWireData <= `SE0;
339			next_USBWireCtrl <= `DRIVE;
340			`end`
341			`end`
342			`STOP_W_RDY2:
343			`begin`
344			`if (USBWireRdy == 1'b1)`
345			`begin`
346			NextState_prcTxB <= `STOP_SND_J;
347			`next_USBWireWEn <= 1'b1;`
348			next_USBWireData <= `SE0;
349			next_USBWireCtrl <= `DRIVE;
350			`end`
351			`end`
352			`STOP_W_RDY3:
353			`begin`
354			`if (USBWireRdy == 1'b1)`
355			`begin`
356	5	sfielding	NextState_prcTxB <= `STOP_SND_IDLE;
357			`next_USBWireWEn <= 1'b1;`
358			`next_USBWireData <= JBit;`
359			next_USBWireCtrl <= `DRIVE;
360			`end`
361			`end`
362	14	sfielding	`STOP_W_RDY4:
363	5	sfielding	`begin`
364			`if (USBWireRdy == 1'b1)`
365			`begin`
366			NextState_prcTxB <= `STOP_FIN;
367			`next_USBWireWEn <= 1'b1;`
368			`next_USBWireData <= JBit;`
369			next_USBWireCtrl <= `TRI_STATE;
370			`end`
371			`end`
372	14	sfielding	`LS_START_SND_IDLE3:
373	5	sfielding	`begin`
374			`next_USBWireWEn <= 1'b0;`
375	14	sfielding	NextState_prcTxB <= `LS_START_W_RDY2;
376	5	sfielding	`end`
377	14	sfielding	`LS_START_SND_J1:
378	9	sfielding	`begin`
379			`next_USBWireWEn <= 1'b0;`
380	14	sfielding	NextState_prcTxB <= `LS_START_W_RDY3;
381			`end`
382			`LS_START_SND_IDLE1:
383			`begin`
384	9	sfielding	`if (USBWireRdy == 1'b1)`
385			`begin`
386	14	sfielding	NextState_prcTxB <= `LS_START_SND_IDLE2;
387	9	sfielding	`next_USBWireWEn <= 1'b1;`
388			`next_USBWireData <= JBit;`
389			next_USBWireCtrl <= `TRI_STATE;
390			`end`
391			`end`
392	14	sfielding	`LS_START_SND_IDLE2:
393	9	sfielding	`begin`
394			`next_USBWireWEn <= 1'b0;`
395	14	sfielding	NextState_prcTxB <= `LS_START_W_RDY1;
396			`end`
397			`LS_START_FIN:
398			`begin`
399			`next_USBWireWEn <= 1'b0;`
400			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
401			`next_i <= 4'h0;`
402			`end`
403			`LS_START_W_RDY1:
404			`begin`
405	9	sfielding	`if (USBWireRdy == 1'b1)`
406			`begin`
407	14	sfielding	NextState_prcTxB <= `LS_START_SND_IDLE3;
408	9	sfielding	`next_USBWireWEn <= 1'b1;`
409			`next_USBWireData <= JBit;`
410	14	sfielding	next_USBWireCtrl <= `TRI_STATE;
411	9	sfielding	`end`
412			`end`
413	14	sfielding	`LS_START_W_RDY2:
414	9	sfielding	`begin`
415			`if (USBWireRdy == 1'b1)`
416			`begin`
417	14	sfielding	NextState_prcTxB <= `LS_START_SND_J1;
418	9	sfielding	`next_USBWireWEn <= 1'b1;`
419			`next_USBWireData <= JBit;`
420			next_USBWireCtrl <= `TRI_STATE;
421			`end`
422			`end`
423	14	sfielding	`LS_START_W_RDY3:
424	9	sfielding	`begin`
425			`if (USBWireRdy == 1'b1)`
426			`begin`
427	14	sfielding	NextState_prcTxB <= `LS_START_FIN;
428			`//Drive the first JBit`
429	9	sfielding	`next_USBWireWEn <= 1'b1;`
430			`next_USBWireData <= JBit;`
431	14	sfielding	next_USBWireCtrl <= `DRIVE;
432	9	sfielding	`end`
433			`end`
434	5	sfielding	`endcase`
435			`end`
436
437			`// Current State Logic (sequential)`
438			`always @ (posedge clk)`
439			`begin`
440			`if (rst)`
441			CurrState_prcTxB <= `START_PTBY;
442			`else`
443			`CurrState_prcTxB <= NextState_prcTxB;`
444			`end`
445
446			`// Registered outputs logic`
447			`always @ (posedge clk)`
448			`begin`
449			`if (rst)`
450			`begin`
451			`processTxByteRdy <= 1'b0;`
452			`USBWireData <= 2'b00;`
453			USBWireCtrl <= `TRI_STATE;
454			`USBWireReq <= 1'b0;`
455			`USBWireWEn <= 1'b0;`
456	14	sfielding	`USBWireFullSpeedRate <= 1'b0;`
457	5	sfielding	`i <= 4'h0;`
458			`TxByte <= 8'h00;`
459			`TxByteCtrl <= 8'h00;`
460			`TXLineState <= 2'b0;`
461			`TXOneCount <= 4'h0;`
462	14	sfielding	`TxByteFullSpeedRate <= 1'b0;`
463	5	sfielding	`end`
464			`else`
465			`begin`
466			`processTxByteRdy <= next_processTxByteRdy;`
467			`USBWireData <= next_USBWireData;`
468			`USBWireCtrl <= next_USBWireCtrl;`
469			`USBWireReq <= next_USBWireReq;`
470			`USBWireWEn <= next_USBWireWEn;`
471	14	sfielding	`USBWireFullSpeedRate <= next_USBWireFullSpeedRate;`
472	5	sfielding	`i <= next_i;`
473			`TxByte <= next_TxByte;`
474			`TxByteCtrl <= next_TxByteCtrl;`
475			`TXLineState <= next_TXLineState;`
476			`TXOneCount <= next_TXOneCount;`
477	14	sfielding	`TxByteFullSpeedRate <= next_TxByteFullSpeedRate;`
478	5	sfielding	`end`
479			`end`
480
481	2	sfielding	`endmodule`

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