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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processTxByte
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: processTxByte.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
input   clk;
input   [1:0]JBit;
input   [1:0]KBit;
input   processTxByteWEn;
input   rst;
input   [7:0]TxByteCtrlIn;
input   [7:0]TxByteIn;
input   USBWireGnt;
input   USBWireRdy;
output  processTxByteRdy;
output  USBWireCtrl;
output  [1:0]USBWireData;
output  USBWireReq;
output  USBWireWEn;
 
wire    clk;
wire    [1:0]JBit;
wire    [1:0]KBit;
reg     processTxByteRdy, next_processTxByteRdy;
wire    processTxByteWEn;
wire    rst;
wire    [7:0]TxByteCtrlIn;
wire    [7:0]TxByteIn;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0]USBWireData, next_USBWireData;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
 
// diagram signals declarations
reg  [3:0]i, next_i;
reg  [7:0]TxByte, next_TxByte;
reg  [7:0]TxByteCtrl, next_TxByteCtrl;
reg  [1:0]TXLineState, next_TXLineState;
reg  [3:0]TXOneCount, next_TXOneCount;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 4'b0000
`define PTBY_WAIT_EN 4'b0001
`define SEND_BYTE_UPDATE_BYTE 4'b0010
`define SEND_BYTE_WAIT_RDY 4'b0011
`define SEND_BYTE_CHK 4'b0100
`define SEND_BYTE_BIT_STUFF 4'b0101
`define SEND_BYTE_WAIT_RDY2 4'b0110
`define SEND_BYTE_CHK_FIN 4'b0111
`define PTBY_WAIT_GNT 4'b1000
`define STOP_SND_SE0_2 4'b1001
`define STOP_SND_SE0_1 4'b1010
`define STOP_CHK 4'b1011
`define STOP_SND_J 4'b1100
`define STOP_SND_IDLE 4'b1101
`define STOP_FIN 4'b1110
 
reg [3:0]CurrState_prcTxB, NextState_prcTxB;
 
 
// Machine: prcTxB
 
// NextState logic (combinatorial)
always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
begin
  NextState_prcTxB <= CurrState_prcTxB;
  // Set default values for outputs and signals
  next_processTxByteRdy <= processTxByteRdy;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_USBWireReq <= USBWireReq;
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_TxByte <= TxByte;
  next_TxByteCtrl <= TxByteCtrl;
  next_TXLineState <= TXLineState;
  next_TXOneCount <= TXOneCount;
  case (CurrState_prcTxB)  // synopsys parallel_case full_case
    `START_PTBY:
    begin
      next_processTxByteRdy <= 1'b0;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_i <= 4'h0;
      next_TxByte <= 8'h00;
      next_TxByteCtrl <= 8'h00;
      next_TXLineState <= 2'b0;
      next_TXOneCount <= 4'h0;
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `PTBY_WAIT_EN:
    begin
      next_processTxByteRdy <= 1'b1;
      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
      begin
        NextState_prcTxB <= `PTBY_WAIT_GNT;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_TXOneCount <= 1;
        next_TXLineState <= JBit;
        next_USBWireReq <= 1'b1;
      end
      else if (processTxByteWEn == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_i <= 4'h0;
      end
    end
    `PTBY_WAIT_GNT:
    begin
      if (USBWireGnt == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
        next_i <= 4'h0;
      end
    end
    `SEND_BYTE_UPDATE_BYTE:
    begin
      next_i <= i + 1'b1;
      next_TxByte <= {1'b0, TxByte[7:1] };
      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
      next_TXOneCount <= TXOneCount + 1'b1;
      //increment 'TXOneCount'
      else                                        //else this is a zero bit
      begin
      next_TXOneCount <= 4'h1;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
      next_TXLineState <= KBit;
      //toggle the line state
      else
      next_TXLineState <= JBit;
      end
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
    end
    `SEND_BYTE_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `SEND_BYTE_CHK:
    begin
      next_USBWireWEn <= 1'b0;
      if (TXOneCount == 4'h6)
      begin
        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
      end
      else if (i != 4'h8)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      end
      else
      begin
        NextState_prcTxB <= `STOP_CHK;
      end
    end
    `SEND_BYTE_BIT_STUFF:
    begin
      next_TXOneCount <= 4'h1;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
      next_TXLineState <= KBit;
      //toggle the line state
      else
      next_TXLineState <= JBit;
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
    end
    `SEND_BYTE_WAIT_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `SEND_BYTE_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (i == 4'h8)
      begin
        NextState_prcTxB <= `STOP_CHK;
      end
      else
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      end
    end
    `STOP_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_J;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_SND_SE0_1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_CHK:
    begin
      if (TxByteCtrl == `DATA_STOP)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_1;
      end
      else
      begin
        NextState_prcTxB <= `PTBY_WAIT_EN;
      end
    end
    `STOP_SND_J:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_IDLE;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_SND_IDLE:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `STOP_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      //release the wire
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_prcTxB <= `START_PTBY;
  else
    CurrState_prcTxB <= NextState_prcTxB;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    processTxByteRdy <= 1'b0;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    USBWireReq <= 1'b0;
    USBWireWEn <= 1'b0;
    i <= 4'h0;
    TxByte <= 8'h00;
    TxByteCtrl <= 8'h00;
    TXLineState <= 2'b0;
    TXOneCount <= 4'h0;
  end
  else
  begin
    processTxByteRdy <= next_processTxByteRdy;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    USBWireReq <= next_USBWireReq;
    USBWireWEn <= next_USBWireWEn;
    i <= next_i;
    TxByte <= next_TxByte;
    TxByteCtrl <= next_TxByteCtrl;
    TXLineState <= next_TXLineState;
    TXOneCount <= next_TXOneCount;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// processTxByte`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// $Id: processTxByte.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbSerialInterfaceEngine_h.v"
53			`include "usbConstants_h.v"
54
55			`module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);`
56			`input clk;`
57			`input [1:0]JBit;`
58			`input [1:0]KBit;`
59			`input processTxByteWEn;`
60			`input rst;`
61			`input [7:0]TxByteCtrlIn;`
62			`input [7:0]TxByteIn;`
63			`input USBWireGnt;`
64			`input USBWireRdy;`
65			`output processTxByteRdy;`
66			`output USBWireCtrl;`
67			`output [1:0]USBWireData;`
68			`output USBWireReq;`
69			`output USBWireWEn;`
70
71			`wire clk;`
72			`wire [1:0]JBit;`
73			`wire [1:0]KBit;`
74			`reg processTxByteRdy, next_processTxByteRdy;`
75			`wire processTxByteWEn;`
76			`wire rst;`
77			`wire [7:0]TxByteCtrlIn;`
78			`wire [7:0]TxByteIn;`
79			`reg USBWireCtrl, next_USBWireCtrl;`
80			`reg [1:0]USBWireData, next_USBWireData;`
81			`wire USBWireGnt;`
82			`wire USBWireRdy;`
83			`reg USBWireReq, next_USBWireReq;`
84			`reg USBWireWEn, next_USBWireWEn;`
85
86			`// diagram signals declarations`
87			`reg [3:0]i, next_i;`
88			`reg [7:0]TxByte, next_TxByte;`
89			`reg [7:0]TxByteCtrl, next_TxByteCtrl;`
90			`reg [1:0]TXLineState, next_TXLineState;`
91			`reg [3:0]TXOneCount, next_TXOneCount;`
92
93			`// BINARY ENCODED state machine: prcTxB`
94			`// State codes definitions:`
95			`define START_PTBY 4'b0000
96			`define PTBY_WAIT_EN 4'b0001
97			`define SEND_BYTE_UPDATE_BYTE 4'b0010
98			`define SEND_BYTE_WAIT_RDY 4'b0011
99			`define SEND_BYTE_CHK 4'b0100
100			`define SEND_BYTE_BIT_STUFF 4'b0101
101			`define SEND_BYTE_WAIT_RDY2 4'b0110
102			`define SEND_BYTE_CHK_FIN 4'b0111
103			`define PTBY_WAIT_GNT 4'b1000
104			`define STOP_SND_SE0_2 4'b1001
105			`define STOP_SND_SE0_1 4'b1010
106			`define STOP_CHK 4'b1011
107			`define STOP_SND_J 4'b1100
108			`define STOP_SND_IDLE 4'b1101
109			`define STOP_FIN 4'b1110
110
111			`reg [3:0]CurrState_prcTxB, NextState_prcTxB;`
112
113
114			`// Machine: prcTxB`
115
116			`// NextState logic (combinatorial)`
117			`always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)`
118			`begin`
119			`NextState_prcTxB <= CurrState_prcTxB;`
120			`// Set default values for outputs and signals`
121			`next_processTxByteRdy <= processTxByteRdy;`
122			`next_USBWireData <= USBWireData;`
123			`next_USBWireCtrl <= USBWireCtrl;`
124			`next_USBWireReq <= USBWireReq;`
125			`next_USBWireWEn <= USBWireWEn;`
126			`next_i <= i;`
127			`next_TxByte <= TxByte;`
128			`next_TxByteCtrl <= TxByteCtrl;`
129			`next_TXLineState <= TXLineState;`
130			`next_TXOneCount <= TXOneCount;`
131			`case (CurrState_prcTxB) // synopsys parallel_case full_case`
132			`START_PTBY:
133			`begin`
134			`next_processTxByteRdy <= 1'b0;`
135			`next_USBWireData <= 2'b00;`
136			next_USBWireCtrl <= `TRI_STATE;
137			`next_USBWireReq <= 1'b0;`
138			`next_USBWireWEn <= 1'b0;`
139			`next_i <= 4'h0;`
140			`next_TxByte <= 8'h00;`
141			`next_TxByteCtrl <= 8'h00;`
142			`next_TXLineState <= 2'b0;`
143			`next_TXOneCount <= 4'h0;`
144			NextState_prcTxB <= `PTBY_WAIT_EN;
145			`end`
146			`PTBY_WAIT_EN:
147			`begin`
148			`next_processTxByteRdy <= 1'b1;`
149			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
150			`begin`
151			NextState_prcTxB <= `PTBY_WAIT_GNT;
152			`next_processTxByteRdy <= 1'b0;`
153			`next_TxByte <= TxByteIn;`
154			`next_TxByteCtrl <= TxByteCtrlIn;`
155			`next_TXOneCount <= 1;`
156			`next_TXLineState <= JBit;`
157			`next_USBWireReq <= 1'b1;`
158			`end`
159			`else if (processTxByteWEn == 1'b1)`
160			`begin`
161			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
162			`next_processTxByteRdy <= 1'b0;`
163			`next_TxByte <= TxByteIn;`
164			`next_TxByteCtrl <= TxByteCtrlIn;`
165			`next_i <= 4'h0;`
166			`end`
167			`end`
168			`PTBY_WAIT_GNT:
169			`begin`
170			`if (USBWireGnt == 1'b1)`
171			`begin`
172			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
173			`next_i <= 4'h0;`
174			`end`
175			`end`
176			`SEND_BYTE_UPDATE_BYTE:
177			`begin`
178			`next_i <= i + 1'b1;`
179			`next_TxByte <= {1'b0, TxByte[7:1] };`
180			`if (TxByte[0] == 1'b1) //If this bit is 1, then`
181			`next_TXOneCount <= TXOneCount + 1'b1;`
182			`//increment 'TXOneCount'`
183			`else //else this is a zero bit`
184			`begin`
185			`next_TXOneCount <= 4'h1;`
186			`//reset 'TXOneCount'`
187			`if (TXLineState == JBit)`
188			`next_TXLineState <= KBit;`
189			`//toggle the line state`
190			`else`
191			`next_TXLineState <= JBit;`
192			`end`
193			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
194			`end`
195			`SEND_BYTE_WAIT_RDY:
196			`begin`
197			`if (USBWireRdy == 1'b1)`
198			`begin`
199			NextState_prcTxB <= `SEND_BYTE_CHK;
200			`next_USBWireWEn <= 1'b1;`
201			`next_USBWireData <= TXLineState;`
202			next_USBWireCtrl <= `DRIVE;
203			`end`
204			`end`
205			`SEND_BYTE_CHK:
206			`begin`
207			`next_USBWireWEn <= 1'b0;`
208			`if (TXOneCount == 4'h6)`
209			`begin`
210			NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
211			`end`
212			`else if (i != 4'h8)`
213			`begin`
214			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
215			`end`
216			`else`
217			`begin`
218			NextState_prcTxB <= `STOP_CHK;
219			`end`
220			`end`
221			`SEND_BYTE_BIT_STUFF:
222			`begin`
223			`next_TXOneCount <= 4'h1;`
224			`//reset 'TXOneCount'`
225			`if (TXLineState == JBit)`
226			`next_TXLineState <= KBit;`
227			`//toggle the line state`
228			`else`
229			`next_TXLineState <= JBit;`
230			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
231			`end`
232			`SEND_BYTE_WAIT_RDY2:
233			`begin`
234			`if (USBWireRdy == 1'b1)`
235			`begin`
236			NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
237			`next_USBWireWEn <= 1'b1;`
238			`next_USBWireData <= TXLineState;`
239			next_USBWireCtrl <= `DRIVE;
240			`end`
241			`end`
242			`SEND_BYTE_CHK_FIN:
243			`begin`
244			`next_USBWireWEn <= 1'b0;`
245			`if (i == 4'h8)`
246			`begin`
247			NextState_prcTxB <= `STOP_CHK;
248			`end`
249			`else`
250			`begin`
251			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
252			`end`
253			`end`
254			`STOP_SND_SE0_2:
255			`begin`
256			`next_USBWireWEn <= 1'b0;`
257			`if (USBWireRdy == 1'b1)`
258			`begin`
259			NextState_prcTxB <= `STOP_SND_J;
260			`next_USBWireWEn <= 1'b1;`
261			next_USBWireData <= `SE0;
262			next_USBWireCtrl <= `DRIVE;
263			`end`
264			`end`
265			`STOP_SND_SE0_1:
266			`begin`
267			`if (USBWireRdy == 1'b1)`
268			`begin`
269			NextState_prcTxB <= `STOP_SND_SE0_2;
270			`next_USBWireWEn <= 1'b1;`
271			next_USBWireData <= `SE0;
272			next_USBWireCtrl <= `DRIVE;
273			`end`
274			`end`
275			`STOP_CHK:
276			`begin`
277			if (TxByteCtrl == `DATA_STOP)
278			`begin`
279			NextState_prcTxB <= `STOP_SND_SE0_1;
280			`end`
281			`else`
282			`begin`
283			NextState_prcTxB <= `PTBY_WAIT_EN;
284			`end`
285			`end`
286			`STOP_SND_J:
287			`begin`
288			`next_USBWireWEn <= 1'b0;`
289			`if (USBWireRdy == 1'b1)`
290			`begin`
291			NextState_prcTxB <= `STOP_SND_IDLE;
292			`next_USBWireWEn <= 1'b1;`
293			`next_USBWireData <= JBit;`
294			next_USBWireCtrl <= `DRIVE;
295			`end`
296			`end`
297			`STOP_SND_IDLE:
298			`begin`
299			`next_USBWireWEn <= 1'b0;`
300			`if (USBWireRdy == 1'b1)`
301			`begin`
302			NextState_prcTxB <= `STOP_FIN;
303			`next_USBWireWEn <= 1'b1;`
304			`next_USBWireData <= JBit;`
305			next_USBWireCtrl <= `TRI_STATE;
306			`end`
307			`end`
308			`STOP_FIN:
309			`begin`
310			`next_USBWireWEn <= 1'b0;`
311			`next_USBWireReq <= 1'b0;`
312			`//release the wire`
313			NextState_prcTxB <= `PTBY_WAIT_EN;
314			`end`
315			`endcase`
316			`end`
317
318			`// Current State Logic (sequential)`
319			`always @ (posedge clk)`
320			`begin`
321			`if (rst)`
322			CurrState_prcTxB <= `START_PTBY;
323			`else`
324			`CurrState_prcTxB <= NextState_prcTxB;`
325			`end`
326
327			`// Registered outputs logic`
328			`always @ (posedge clk)`
329			`begin`
330			`if (rst)`
331			`begin`
332			`processTxByteRdy <= 1'b0;`
333			`USBWireData <= 2'b00;`
334			USBWireCtrl <= `TRI_STATE;
335			`USBWireReq <= 1'b0;`
336			`USBWireWEn <= 1'b0;`
337			`i <= 4'h0;`
338			`TxByte <= 8'h00;`
339			`TxByteCtrl <= 8'h00;`
340			`TXLineState <= 2'b0;`
341			`TXOneCount <= 4'h0;`
342			`end`
343			`else`
344			`begin`
345			`processTxByteRdy <= next_processTxByteRdy;`
346			`USBWireData <= next_USBWireData;`
347			`USBWireCtrl <= next_USBWireCtrl;`
348			`USBWireReq <= next_USBWireReq;`
349			`USBWireWEn <= next_USBWireWEn;`
350			`i <= next_i;`
351			`TxByte <= next_TxByte;`
352			`TxByteCtrl <= next_TxByteCtrl;`
353			`TXLineState <= next_TXLineState;`
354			`TXOneCount <= next_TXOneCount;`
355			`end`
356			`end`
357
358	2	sfielding	`endmodule`