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[/] [usbhostslave/] [trunk/] [RTL/] [buffers/] [TxFifoBI.v] - Blame information for rev 22

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1 22 sfielding
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// TxfifoBI.v                                                   ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "wishBoneBus_h.v"
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module TxfifoBI (
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  address, writeEn, strobe_i,
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  busClk,
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  usbClk,
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  rstSyncToBusClk,
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  fifoSelect,
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  busDataIn,
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  busDataOut,
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  fifoWEn,
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  forceEmptySyncToUsbClk,
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  forceEmptySyncToBusClk,
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  numElementsInFifo
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  );
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input [2:0] address;
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input writeEn;
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input strobe_i;
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input busClk;
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input usbClk;
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input rstSyncToBusClk;
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input [7:0] busDataIn;
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output [7:0] busDataOut;
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output fifoWEn;
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output forceEmptySyncToUsbClk;
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output forceEmptySyncToBusClk;
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input [15:0] numElementsInFifo;
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input fifoSelect;
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wire [2:0] address;
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wire writeEn;
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wire strobe_i;
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wire busClk;
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wire usbClk;
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wire rstSyncToBusClk;
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wire [7:0] busDataIn;
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wire [7:0] busDataOut;
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reg fifoWEn;
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reg forceEmptySyncToUsbClk;
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wire forceEmptySyncToBusClk;
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wire [15:0] numElementsInFifo;
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wire fifoSelect;
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reg [5:0] forceEmptyShift;
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reg forceEmpty;
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reg forceEmptySyncToUsbClkFirst;
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//sync write
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always @(posedge busClk)
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begin
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  if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
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  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
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    forceEmpty <= 1'b1;
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  else
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    forceEmpty <= 1'b0;
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end
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//generate 'forceEmptySyncToBusClk'
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//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
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always @(posedge busClk) begin
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  if (rstSyncToBusClk == 1'b1)
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    forceEmptyShift <= 6'b000000;
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  else begin
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    if (forceEmpty == 1'b1)
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      forceEmptyShift <= 6'b111111;
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    else
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      forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
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  end
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end
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assign forceEmptySyncToBusClk = forceEmptyShift[0];
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// double sync across clock domains to generate 'forceEmptySyncToWrClk'
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always @(posedge usbClk) begin
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    forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
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    forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
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end
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// async read mux
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assign busDataOut = 8'h00;
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//always @(address or fifoFull or numElementsInFifo)
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//begin
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//  case (address)
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//      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
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//      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
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//      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
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//      default: busDataOut <= 8'h00;
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//  endcase
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//end
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//generate fifo write strobe
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always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
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  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 &&
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  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
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    fifoWEn <= 1'b1;
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  else
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    fifoWEn <= 1'b0;
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end
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endmodule

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