OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [USBHostControlBI.v] - Blame information for rev 40

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 sfielding
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// USBHostControlBI.v                                           ////
4
////                                                              ////
5
//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
7
////                                                              ////
8
//// Module Description:                                          ////
9
//// 
10
////                                                              ////
11
//// To Do:                                                       ////
12
//// 
13
////                                                              ////
14
//// Author(s):                                                   ////
15
//// - Steve Fielding, sfielding@base2designs.com                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from <http://www.opencores.org/lgpl.shtml>                   ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
`include "usbHostControl_h.v"
46
 
47
module USBHostControlBI (address, dataIn, dataOut, writeEn,
48
  strobe_i,
49
  busClk,
50
  rstSyncToBusClk,
51
  usbClk,
52
  rstSyncToUsbClk,
53
  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
54
  TxTransTypeReg, TxSOFEnableReg,
55
  TxAddrReg, TxEndPReg, frameNumIn,
56
  RxPktStatusIn, RxPIDIn,
57
  connectStateIn,
58
  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
59
  hostControlSelect,
60
  clrTransReq,
61
  preambleEn,
62
  SOFSync,
63
  TxLineState,
64
  LineDirectControlEn,
65
  fullSpeedPol,
66
  fullSpeedRate,
67
  transReq,
68
  isoEn,
69
  SOFTimer
70
  );
71
input [3:0] address;
72
input [7:0] dataIn;
73
input writeEn;
74
input strobe_i;
75
input busClk;
76
input rstSyncToBusClk;
77
input usbClk;
78
input rstSyncToUsbClk;
79
output [7:0] dataOut;
80
output SOFSentIntOut;
81
output connEventIntOut;
82
output resumeIntOut;
83
output transDoneIntOut;
84
 
85
output [1:0] TxTransTypeReg;
86
output TxSOFEnableReg;
87
output [6:0] TxAddrReg;
88
output [3:0] TxEndPReg;
89
input [10:0] frameNumIn;
90
input [7:0] RxPktStatusIn;
91
input [3:0] RxPIDIn;
92
input [1:0] connectStateIn;
93
input SOFSentIn;
94
input connEventIn;
95
input resumeIntIn;
96
input transDoneIn;
97
input hostControlSelect;
98
input clrTransReq;
99
output preambleEn;
100
output SOFSync;
101
output [1:0] TxLineState;
102
output LineDirectControlEn;
103
output fullSpeedPol;
104
output fullSpeedRate;
105
output transReq;
106
output isoEn;     //enable isochronous mode
107
input [15:0] SOFTimer;
108
 
109
wire [3:0] address;
110
wire [7:0] dataIn;
111
wire writeEn;
112
wire strobe_i;
113
wire busClk;
114
wire rstSyncToBusClk;
115
wire usbClk;
116
wire rstSyncToUsbClk;
117
reg [7:0] dataOut;
118
 
119
reg SOFSentIntOut;
120
reg connEventIntOut;
121
reg resumeIntOut;
122
reg transDoneIntOut;
123
 
124
reg [1:0] TxTransTypeReg;
125 37 sfielding
reg [1:0] TxTransTypeReg_reg1;
126 22 sfielding
reg TxSOFEnableReg;
127 37 sfielding
reg TxSOFEnableReg_reg1;
128 22 sfielding
reg [6:0] TxAddrReg;
129 37 sfielding
reg [6:0] TxAddrReg_reg1;
130 22 sfielding
reg [3:0] TxEndPReg;
131 37 sfielding
reg [3:0] TxEndPReg_reg1;
132 22 sfielding
wire [10:0] frameNumIn;
133
wire [7:0] RxPktStatusIn;
134
wire [3:0] RxPIDIn;
135
wire [1:0] connectStateIn;
136
 
137
wire SOFSentIn;
138
wire connEventIn;
139
wire resumeIntIn;
140
wire transDoneIn;
141
wire hostControlSelect;
142
wire clrTransReq;
143
reg preambleEn;
144 37 sfielding
reg preambleEn_reg1;
145 22 sfielding
reg SOFSync;
146 37 sfielding
reg SOFSync_reg1;
147 22 sfielding
reg [1:0] TxLineState;
148 37 sfielding
reg [1:0] TxLineState_reg1;
149 22 sfielding
reg LineDirectControlEn;
150 37 sfielding
reg LineDirectControlEn_reg1;
151 22 sfielding
reg fullSpeedPol;
152 37 sfielding
reg fullSpeedPol_reg1;
153 22 sfielding
reg fullSpeedRate;
154 37 sfielding
reg fullSpeedRate_reg1;
155 22 sfielding
reg transReq;
156 37 sfielding
reg transReq_reg1;
157 22 sfielding
reg isoEn;
158 37 sfielding
reg isoEn_reg1;
159 22 sfielding
wire [15:0] SOFTimer;
160
 
161
//internal wire and regs
162
reg [1:0] TxControlReg;
163
reg [4:0] TxLineControlReg;
164
reg clrSOFReq;
165
reg clrConnEvtReq;
166
reg clrResInReq;
167
reg clrTransDoneReq;
168
reg SOFSentInt;
169
reg connEventInt;
170
reg resumeInt;
171
reg transDoneInt;
172
reg [3:0] interruptMaskReg;
173
reg setTransReq;
174 37 sfielding
reg [2:0] resumeIntInExtend;
175
reg [2:0] transDoneInExtend;
176
reg [2:0] connEventInExtend;
177
reg [2:0] SOFSentInExtend;
178
reg [2:0] clrTransReqExtend;
179 22 sfielding
 
180
//clock domain crossing sync registers
181
//STB = Sync To Busclk
182
reg [1:0] TxTransTypeRegSTB;
183
reg TxSOFEnableRegSTB;
184
reg [6:0] TxAddrRegSTB;
185
reg [3:0] TxEndPRegSTB;
186
reg preambleEnSTB;
187
reg SOFSyncSTB;
188
reg [1:0] TxLineStateSTB;
189
reg LineDirectControlEnSTB;
190
reg fullSpeedPolSTB;
191
reg fullSpeedRateSTB;
192
reg transReqSTB;
193
reg isoEnSTB;
194
reg [10:0] frameNumInSTB;
195 37 sfielding
reg [10:0] frameNumInSTB_reg1;
196 22 sfielding
reg [7:0] RxPktStatusInSTB;
197 37 sfielding
reg [7:0] RxPktStatusInSTB_reg1;
198 22 sfielding
reg [3:0] RxPIDInSTB;
199 37 sfielding
reg [3:0] RxPIDInSTB_reg1;
200 22 sfielding
reg [1:0] connectStateInSTB;
201 37 sfielding
reg [1:0] connectStateInSTB_reg1;
202
reg [2:0] SOFSentInSTB;
203
reg [2:0] connEventInSTB;
204
reg [2:0] resumeIntInSTB;
205
reg [2:0] transDoneInSTB;
206
reg [2:0] clrTransReqSTB;
207 22 sfielding
reg [15:0] SOFTimerSTB;
208 37 sfielding
reg [15:0] SOFTimerSTB_reg1;
209 22 sfielding
 
210
 
211
//sync write demux
212
always @(posedge busClk)
213
begin
214
  if (rstSyncToBusClk == 1'b1) begin
215
    isoEnSTB <= 1'b0;
216
    preambleEnSTB <= 1'b0;
217
    SOFSyncSTB <= 1'b0;
218
    TxTransTypeRegSTB <= 2'b00;
219
    TxLineControlReg <= 5'h00;
220
    TxSOFEnableRegSTB <= 1'b0;
221
    TxAddrRegSTB <= 7'h00;
222
    TxEndPRegSTB <= 4'h0;
223
    interruptMaskReg <= 4'h0;
224
  end
225
  else begin
226
    clrSOFReq <= 1'b0;
227
    clrConnEvtReq <= 1'b0;
228
    clrResInReq <= 1'b0;
229
    clrTransDoneReq <= 1'b0;
230
    setTransReq <= 1'b0;
231
    if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
232
    begin
233
      case (address)
234
        `TX_CONTROL_REG : begin
235
          isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
236
          preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
237
          SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
238
          setTransReq <= dataIn[`TRANS_REQ_BIT];
239
        end
240
        `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
241
        `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
242
        `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
243
        `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
244
        `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
245
        `INTERRUPT_STATUS_REG :  begin
246
          clrSOFReq <= dataIn[`SOF_SENT_BIT];
247
          clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
248
          clrResInReq <= dataIn[`RESUME_INT_BIT];
249
          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
250
        end
251
        `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
252
      endcase
253
    end
254
  end
255
end
256
 
257
//interrupt control
258
always @(posedge busClk)
259
begin
260
  if (rstSyncToBusClk == 1'b1) begin
261
    SOFSentInt <= 1'b0;
262
    connEventInt <= 1'b0;
263
    resumeInt <= 1'b0;
264
    transDoneInt <= 1'b0;
265
  end
266
  else begin
267 37 sfielding
    if (SOFSentInSTB[1] == 1'b1 && SOFSentInSTB[0] == 1'b0)
268 22 sfielding
      SOFSentInt <= 1'b1;
269
    else if (clrSOFReq == 1'b1)
270
      SOFSentInt <= 1'b0;
271
 
272 37 sfielding
    if (connEventInSTB[1] == 1'b1 && connEventInSTB[0] == 1'b0)
273 22 sfielding
      connEventInt <= 1'b1;
274
    else if (clrConnEvtReq == 1'b1)
275
      connEventInt <= 1'b0;
276
 
277 37 sfielding
    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
278 22 sfielding
      resumeInt <= 1'b1;
279
    else if (clrResInReq == 1'b1)
280
      resumeInt <= 1'b0;
281
 
282 37 sfielding
    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
283 22 sfielding
      transDoneInt <= 1'b1;
284
    else if (clrTransDoneReq == 1'b1)
285
      transDoneInt <= 1'b0;
286
  end
287
end
288
 
289
//mask interrupts
290 37 sfielding
always @(*) begin
291 22 sfielding
  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
292
  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
293
  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
294
  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
295
end
296
 
297
//transaction request set/clear
298
//Since 'busClk' can be a higher freq than 'usbClk',
299
//'setTransReq' must be delayed with respect to other control signals, thus
300
//ensuring that control signals have been clocked through to 'usbClk' clock
301
//domain before the transaction request is asserted.
302
//Not sure this is required because there is at least two 'usbClk' ticks between
303 37 sfielding
//detection of 'transReq' and sampling of related control signals.
304 22 sfielding
always @(posedge busClk)
305
begin
306
  if (rstSyncToBusClk == 1'b1) begin
307
    transReqSTB <= 1'b0;
308
  end
309
  else begin
310
    if (setTransReq == 1'b1)
311
      transReqSTB <= 1'b1;
312 37 sfielding
    else if (clrTransReqSTB[1] == 1'b1 && clrTransReqSTB[0] == 1'b0)
313 22 sfielding
      transReqSTB <= 1'b0;
314
  end
315
end
316
 
317
//break out control signals
318 37 sfielding
always @(*) begin
319 22 sfielding
  TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
320
  LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
321
  fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
322
  fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
323
end
324
 
325
// async read mux
326 37 sfielding
always @(*)
327 22 sfielding
begin
328
  case (address)
329
      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
330
      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
331
      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
332
      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
333
      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
334
      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
335
      `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
336
      `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
337
      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
338
      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
339
      `RX_STATUS_REG  : dataOut <= RxPktStatusInSTB;
340
      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDInSTB};
341
      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
342
      `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8];
343
      default: dataOut <= 8'h00;
344
  endcase
345
end
346
 
347
//re-sync from busClk to usbClk. 
348
always @(posedge usbClk) begin
349
  if (rstSyncToUsbClk == 1'b1) begin
350
    isoEn <= 1'b0;
351 37 sfielding
    isoEn_reg1 <= 1'b0;
352 22 sfielding
    preambleEn <= 1'b0;
353 37 sfielding
    preambleEn_reg1 <= 1'b0;
354 22 sfielding
    SOFSync <= 1'b0;
355 37 sfielding
    SOFSync_reg1 <= 1'b0;
356 22 sfielding
    TxTransTypeReg <= 2'b00;
357 37 sfielding
    TxTransTypeReg_reg1 <= 2'b00;
358 22 sfielding
    TxSOFEnableReg <= 1'b0;
359 37 sfielding
    TxSOFEnableReg_reg1 <= 1'b0;
360
    TxAddrReg <= {7{1'b0}};
361
    TxAddrReg_reg1 <= {7{1'b0}};
362 22 sfielding
    TxEndPReg <= 4'h0;
363 37 sfielding
    TxEndPReg_reg1 <= 4'h0;
364 22 sfielding
    TxLineState <= 2'b00;
365 37 sfielding
    TxLineState_reg1 <= 2'b00;
366 22 sfielding
    LineDirectControlEn <= 1'b0;
367 37 sfielding
    LineDirectControlEn_reg1 <= 1'b0;
368 22 sfielding
    fullSpeedPol <= 1'b0;
369 37 sfielding
    fullSpeedPol_reg1 <= 1'b0;
370 22 sfielding
    fullSpeedRate <= 1'b0;
371 37 sfielding
    fullSpeedRate_reg1 <= 1'b0;
372 22 sfielding
    transReq <= 1'b0;
373 37 sfielding
    transReq_reg1 <= 1'b0;
374 22 sfielding
  end
375
  else begin
376 37 sfielding
    isoEn_reg1 <= isoEnSTB;
377
    isoEn <= isoEn_reg1;
378
    preambleEn_reg1 <= preambleEnSTB;
379
    preambleEn <= preambleEn_reg1;
380
    SOFSync_reg1 <= SOFSyncSTB;
381
    SOFSync <= SOFSync_reg1;
382
    TxTransTypeReg_reg1 <= TxTransTypeRegSTB;
383
    TxTransTypeReg <= TxTransTypeReg_reg1;
384
    TxSOFEnableReg_reg1 <= TxSOFEnableRegSTB;
385
    TxSOFEnableReg <= TxSOFEnableReg_reg1;
386
    TxAddrReg_reg1 <= TxAddrRegSTB;
387
    TxAddrReg <= TxAddrReg_reg1;
388
    TxEndPReg_reg1 <= TxEndPRegSTB;
389
    TxEndPReg <= TxEndPReg_reg1;
390
    TxLineState_reg1 <= TxLineStateSTB;
391
    TxLineState <= TxLineState_reg1;
392
    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
393
    LineDirectControlEn <= LineDirectControlEn_reg1;
394
    fullSpeedPol_reg1 <= fullSpeedPolSTB;
395
    fullSpeedPol <= fullSpeedPol_reg1;
396
    fullSpeedRate_reg1 <= fullSpeedRateSTB;
397
    fullSpeedRate <= fullSpeedRate_reg1;
398
    transReq_reg1 <= transReqSTB;
399
    transReq <= transReq_reg1;
400 22 sfielding
  end
401
end
402
 
403 37 sfielding
//Extend  resumeIntIn etc from 1 tick to 3 ticks
404
always @(posedge usbClk) begin
405
  if (rstSyncToUsbClk == 1'b1) begin
406
    resumeIntInExtend <= 3'b000;
407
    transDoneInExtend <= 3'b000;
408
    connEventInExtend <= 3'b000;
409
    SOFSentInExtend <= 3'b000;
410
    clrTransReqExtend <= 3'b000;
411
  end
412
  else begin
413
    if (resumeIntIn == 1'b1)
414
      resumeIntInExtend <= 3'b111;
415
    else
416
      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
417
    if (transDoneIn == 1'b1)
418
      transDoneInExtend <= 3'b111;
419
    else
420
      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
421
    if (connEventIn == 1'b1)
422
      connEventInExtend <= 3'b111;
423
    else
424
      connEventInExtend <= {1'b0, connEventInExtend[2:1]};
425
    if (SOFSentIn == 1'b1)
426
      SOFSentInExtend <= 3'b111;
427
    else
428
      SOFSentInExtend <= {1'b0, SOFSentInExtend[2:1]};
429
    if (clrTransReq == 1'b1)
430
      clrTransReqExtend <= 3'b111;
431
    else
432
      clrTransReqExtend <= {1'b0, clrTransReqExtend[2:1]};
433
  end
434
end
435
 
436 22 sfielding
//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted 
437 37 sfielding
//for 3 'usbClk' ticks, busClk freq must be greater than or equal to usbClk/3 freq
438 22 sfielding
always @(posedge busClk) begin
439 37 sfielding
  if (rstSyncToBusClk == 1'b1) begin
440
    SOFSentInSTB <= 3'b000;
441
    connEventInSTB <= 3'b000;
442
    resumeIntInSTB <= 3'b000;
443
    transDoneInSTB <= 3'b000;
444
    clrTransReqSTB <= 3'b000;
445
    frameNumInSTB <= {11{1'b0}};
446
    frameNumInSTB_reg1 <= {11{1'b0}};
447
    RxPktStatusInSTB <= 8'h00;
448
    RxPktStatusInSTB_reg1 <= 8'h00;
449
    RxPIDInSTB <= 4'h0;
450
    RxPIDInSTB_reg1 <= 4'h0;
451
    connectStateInSTB <= 2'b00;
452
    connectStateInSTB_reg1 <= 2'b00;
453
    SOFTimerSTB <= 16'h0000;
454
    SOFTimerSTB_reg1 <= 16'h0000;
455
  end
456
  else begin
457
    frameNumInSTB_reg1 <= frameNumIn;
458
    frameNumInSTB <= frameNumInSTB_reg1;
459
    RxPktStatusInSTB_reg1 <= RxPktStatusIn;
460
    RxPktStatusInSTB <= RxPktStatusInSTB_reg1;
461
    RxPIDInSTB_reg1 <= RxPIDIn;
462
    RxPIDInSTB <= RxPIDInSTB_reg1;
463
    connectStateInSTB_reg1 <= connectStateIn;
464
    connectStateInSTB <= connectStateInSTB_reg1;
465
    SOFSentInSTB <= {SOFSentInExtend[0], SOFSentInSTB[2:1]};
466
    connEventInSTB <= {connEventInExtend[0], connEventInSTB[2:1]};
467
    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
468
    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
469
    clrTransReqSTB <= {clrTransReqExtend[0], clrTransReqSTB[2:1]};
470
    //FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
471
    //All the other multi-bit signals will be static at the time that they are
472
    //read, but 'SOFTimer' will not be static.
473
    SOFTimerSTB_reg1 <= SOFTimer;
474
    SOFTimerSTB <= SOFTimerSTB_reg1;
475
  end
476 22 sfielding
end
477
 
478
 
479
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.