URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [directcontrol.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log


 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// directControl
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: directcontrol.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
input   clk;
input   directControlEn;
input   [1:0]directControlLineState;
input   HCTxPortGnt;
input   HCTxPortRdy;
input   rst;
output  [7:0]HCTxPortCntl;
output  [7:0]HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
 
wire    clk;
wire    directControlEn;
wire    [1:0]directControlLineState;
reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0]HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    rst;
 
// BINARY ENCODED state machine: drctCntl
// State codes definitions:
`define START_DC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
 
reg [2:0]CurrState_drctCntl, NextState_drctCntl;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: drctCntl
 
// NextState logic (combinatorial)
always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
begin
  NextState_drctCntl <= CurrState_drctCntl;
  // Set default values for outputs and signals
  next_HCTxPortCntl <= HCTxPortCntl;
  next_HCTxPortData <= HCTxPortData;
  next_HCTxPortWEn <= HCTxPortWEn;
  next_HCTxPortReq <= HCTxPortReq;
  case (CurrState_drctCntl)  // synopsys parallel_case full_case
    `START_DC:
    begin
      NextState_drctCntl <= `CHK_DRCT_CNTL;
    end
    `CHK_DRCT_CNTL:
    begin
      if (directControlEn == 1'b1)
      begin
        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
        next_HCTxPortReq <= 1'b1;
      end
      else
      begin
        NextState_drctCntl <= `IDLE_WAIT_GNT;
        next_HCTxPortReq <= 1'b1;
      end
    end
    `DRCT_CNTL_WAIT_GNT:
    begin
      if (HCTxPortGnt == 1'b1)
      begin
        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
      end
    end
    `DRCT_CNTL_CHK_LOOP:
    begin
      next_HCTxPortWEn <= 1'b0;
      if (directControlEn == 1'b0)
      begin
        NextState_drctCntl <= `CHK_DRCT_CNTL;
        next_HCTxPortReq <= 1'b0;
      end
      else
      begin
        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
      end
    end
    `DRCT_CNTL_WAIT_RDY:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {6'b000000, directControlLineState};
        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
      end
    end
    `IDLE_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      next_HCTxPortReq <= 1'b0;
      NextState_drctCntl <= `CHK_DRCT_CNTL;
    end
    `IDLE_WAIT_GNT:
    begin
      if (HCTxPortGnt == 1'b1)
      begin
        NextState_drctCntl <= `IDLE_WAIT_RDY;
      end
    end
    `IDLE_WAIT_RDY:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_drctCntl <= `IDLE_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_IDLE;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_drctCntl <= `START_DC;
  else
    CurrState_drctCntl <= NextState_drctCntl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    HCTxPortCntl <= 8'h00;
    HCTxPortData <= 8'h00;
    HCTxPortWEn <= 1'b0;
    HCTxPortReq <= 1'b0;
  end
  else
  begin
    HCTxPortCntl <= next_HCTxPortCntl;
    HCTxPortData <= next_HCTxPortData;
    HCTxPortWEn <= next_HCTxPortWEn;
    HCTxPortReq <= next_HCTxPortReq;
  end
end
 
endmodule

Browse

Tools

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [directcontrol.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// directControl`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	7	sfielding	`// $Id: directcontrol.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $`
46	5	sfielding	`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51
52			`timescale 1ns / 1ps
53			`include "usbSerialInterfaceEngine_h.v"
54
55			`module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);`
56			`input clk;`
57			`input directControlEn;`
58			`input [1:0]directControlLineState;`
59			`input HCTxPortGnt;`
60			`input HCTxPortRdy;`
61			`input rst;`
62			`output [7:0]HCTxPortCntl;`
63			`output [7:0]HCTxPortData;`
64			`output HCTxPortReq;`
65			`output HCTxPortWEn;`
66
67			`wire clk;`
68			`wire directControlEn;`
69			`wire [1:0]directControlLineState;`
70			`reg [7:0]HCTxPortCntl, next_HCTxPortCntl;`
71			`reg [7:0]HCTxPortData, next_HCTxPortData;`
72			`wire HCTxPortGnt;`
73			`wire HCTxPortRdy;`
74			`reg HCTxPortReq, next_HCTxPortReq;`
75			`reg HCTxPortWEn, next_HCTxPortWEn;`
76			`wire rst;`
77
78			`// BINARY ENCODED state machine: drctCntl`
79			`// State codes definitions:`
80			`define START_DC 3'b000
81			`define CHK_DRCT_CNTL 3'b001
82			`define DRCT_CNTL_WAIT_GNT 3'b010
83			`define DRCT_CNTL_CHK_LOOP 3'b011
84			`define DRCT_CNTL_WAIT_RDY 3'b100
85			`define IDLE_FIN 3'b101
86			`define IDLE_WAIT_GNT 3'b110
87			`define IDLE_WAIT_RDY 3'b111
88
89			`reg [2:0]CurrState_drctCntl, NextState_drctCntl;`
90
91			`// Diagram actions (continuous assignments allowed only: assign ...)`
92			`// diagram ACTION`
93
94
95			`// Machine: drctCntl`
96
97			`// NextState logic (combinatorial)`
98			`always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)`
99			`begin`
100			`NextState_drctCntl <= CurrState_drctCntl;`
101			`// Set default values for outputs and signals`
102			`next_HCTxPortCntl <= HCTxPortCntl;`
103			`next_HCTxPortData <= HCTxPortData;`
104			`next_HCTxPortWEn <= HCTxPortWEn;`
105			`next_HCTxPortReq <= HCTxPortReq;`
106			`case (CurrState_drctCntl) // synopsys parallel_case full_case`
107			`START_DC:
108			`begin`
109			NextState_drctCntl <= `CHK_DRCT_CNTL;
110			`end`
111			`CHK_DRCT_CNTL:
112			`begin`
113			`if (directControlEn == 1'b1)`
114			`begin`
115			NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
116			`next_HCTxPortReq <= 1'b1;`
117			`end`
118			`else`
119			`begin`
120			NextState_drctCntl <= `IDLE_WAIT_GNT;
121			`next_HCTxPortReq <= 1'b1;`
122			`end`
123			`end`
124			`DRCT_CNTL_WAIT_GNT:
125			`begin`
126			`if (HCTxPortGnt == 1'b1)`
127			`begin`
128			NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
129			`end`
130			`end`
131			`DRCT_CNTL_CHK_LOOP:
132			`begin`
133			`next_HCTxPortWEn <= 1'b0;`
134			`if (directControlEn == 1'b0)`
135			`begin`
136			NextState_drctCntl <= `CHK_DRCT_CNTL;
137			`next_HCTxPortReq <= 1'b0;`
138			`end`
139			`else`
140			`begin`
141			NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
142			`end`
143			`end`
144			`DRCT_CNTL_WAIT_RDY:
145			`begin`
146			`if (HCTxPortRdy == 1'b1)`
147			`begin`
148			NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
149			`next_HCTxPortWEn <= 1'b1;`
150			`next_HCTxPortData <= {6'b000000, directControlLineState};`
151			next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
152			`end`
153			`end`
154			`IDLE_FIN:
155			`begin`
156			`next_HCTxPortWEn <= 1'b0;`
157			`next_HCTxPortReq <= 1'b0;`
158			NextState_drctCntl <= `CHK_DRCT_CNTL;
159			`end`
160			`IDLE_WAIT_GNT:
161			`begin`
162			`if (HCTxPortGnt == 1'b1)`
163			`begin`
164			NextState_drctCntl <= `IDLE_WAIT_RDY;
165			`end`
166			`end`
167			`IDLE_WAIT_RDY:
168			`begin`
169			`if (HCTxPortRdy == 1'b1)`
170			`begin`
171			NextState_drctCntl <= `IDLE_FIN;
172			`next_HCTxPortWEn <= 1'b1;`
173			`next_HCTxPortData <= 8'h00;`
174			next_HCTxPortCntl <= `TX_IDLE;
175			`end`
176			`end`
177			`endcase`
178			`end`
179
180			`// Current State Logic (sequential)`
181			`always @ (posedge clk)`
182			`begin`
183			`if (rst)`
184			CurrState_drctCntl <= `START_DC;
185			`else`
186			`CurrState_drctCntl <= NextState_drctCntl;`
187			`end`
188
189			`// Registered outputs logic`
190			`always @ (posedge clk)`
191			`begin`
192			`if (rst)`
193			`begin`
194			`HCTxPortCntl <= 8'h00;`
195			`HCTxPortData <= 8'h00;`
196			`HCTxPortWEn <= 1'b0;`
197			`HCTxPortReq <= 1'b0;`
198			`end`
199			`else`
200			`begin`
201			`HCTxPortCntl <= next_HCTxPortCntl;`
202			`HCTxPortData <= next_HCTxPortData;`
203			`HCTxPortWEn <= next_HCTxPortWEn;`
204			`HCTxPortReq <= next_HCTxPortReq;`
205			`end`
206			`end`
207
208	2	sfielding	`endmodule`