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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\getpacket.v
// Generated   : 09/22/04 06:01:21
// From        : c:\projects\USBHostSlave\RTL\hostController\getpacket.asf
// By          : FSM2VHDL ver. 4.0.5.2
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, clk, getPacketEn, rst);
input   [7:0] RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0] RXStreamStatusIn;
input   SIERxTimeOut;           // Single cycle pulse
input   clk;
input   getPacketEn;
input   rst;
output  [7:0] RXFifoData;
output  RXFifoWEn;
output  RXPacketRdy;
output  [7:0] RXPktStatus;
output  [3:0] RxPID;
 
wire    [7:0] RXDataIn;
wire    RXDataValid;
reg     [7:0] RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [7:0] RXPktStatus;
wire    [7:0] RXStreamStatusIn;
reg     [3:0] RxPID, next_RxPID;
wire    SIERxTimeOut;
wire    clk;
wire    getPacketEn;
wire    rst;
 
// diagram signals declarations
reg  ACKRxed, next_ACKRxed;
reg  CRCError, next_CRCError;
reg  NAKRxed, next_NAKRxed;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXByte, next_RXByte;
reg  RXOverflow, next_RXOverflow;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
reg  RXTimeOut, next_RXTimeOut;
reg  bitStuffError, next_bitStuffError;
reg  dataSequence, next_dataSequence;
reg  stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: getPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0] CurrState_getPkt;
reg [4:0] NextState_getPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(CRCError or bitStuffError or
  RXOverflow or RXTimeOut or
  NAKRxed or stallRxed or
  ACKRxed or dataSequence)
begin
    RXPktStatus = {
    dataSequence, ACKRxed,
    stallRxed, NAKRxed,
    RXTimeOut, RXOverflow,
    bitStuffError, CRCError};
end
 
 
//--------------------------------------------------------------------
// Machine: getPkt
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
begin : getPkt_NextState
        NextState_getPkt <= CurrState_getPkt;
        // Set default values for outputs and signals
        next_CRCError <= CRCError;
        next_bitStuffError <= bitStuffError;
        next_RXOverflow <= RXOverflow;
        next_RXTimeOut <= RXTimeOut;
        next_NAKRxed <= NAKRxed;
        next_stallRxed <= stallRxed;
        next_ACKRxed <= ACKRxed;
        next_dataSequence <= dataSequence;
        next_RXByte <= RXByte;
        next_RXStreamStatus <= RXStreamStatus;
        next_RxPID <= RxPID;
        next_RXPacketRdy <= RXPacketRdy;
        next_RXByteOldest <= RXByteOldest;
        next_RXByteOld <= RXByteOld;
        next_RXFifoWEn <= RXFifoWEn;
        next_RXFifoData <= RXFifoData;
        case (CurrState_getPkt) // synopsys parallel_case full_case
                `START_GP:
                        NextState_getPkt <= `WAIT_EN;
                `WAIT_PKT:
                begin
                        next_CRCError <= 1'b0;
                        next_bitStuffError <= 1'b0;
                        next_RXOverflow <= 1'b0;
                        next_RXTimeOut <= 1'b0;
                        next_NAKRxed <= 1'b0;
                        next_stallRxed <= 1'b0;
                        next_ACKRxed <= 1'b0;
                        next_dataSequence <= 1'b0;
                        if (SIERxTimeOut == 1'b1)
                        begin
                                NextState_getPkt <= `PKT_RDY;
                                next_RXTimeOut <= 1'b1;
                        end
                        else if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `CHK_PKT_START;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                end
                `CHK_PKT_START:
                        if (RXStreamStatus == `RX_PACKET_START)
                        begin
                                NextState_getPkt <= `PROC_PKT_CHK_PID;
                                next_RxPID <= RXByte[3:0];
                        end
                        else
                        begin
                                NextState_getPkt <= `PKT_RDY;
                                next_RXTimeOut <= 1'b1;
                        end
                `WAIT_EN:
                begin
                        next_RXPacketRdy <= 1'b0;
                        if (getPacketEn == 1'b1)
                                NextState_getPkt <= `WAIT_PKT;
                end
                `PKT_RDY:
                begin
                        next_RXPacketRdy <= 1'b1;
                        NextState_getPkt <= `WAIT_EN;
                end
                `PROC_PKT_CHK_PID:
                        if (RXByte[1:0] == `HANDSHAKE)
                                NextState_getPkt <= `PROC_PKT_HS;
                        else if (RXByte[1:0] == `DATA)
                                NextState_getPkt <= `PROC_PKT_DATA_W_D1;
                        else
                                NextState_getPkt <= `PKT_RDY;
                `PROC_PKT_HS:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PKT_RDY;
                                next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
                                next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
                                next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
                                next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
                        end
                `PROC_PKT_DATA_W_D1:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_CHK_D1:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_W_D2;
                                next_RXByteOldest <= RXByte;
                        end
                        else
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_W_D2:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_FIN:
                begin
                        next_CRCError <= RXByte[`CRC_ERROR_BIT];
                        next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
                        next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
                        NextState_getPkt <= `PKT_RDY;
                end
                `PROC_PKT_DATA_CHK_D2:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_W_D3;
                                next_RXByteOld <= RXByte;
                        end
                        else
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_W_D3:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_CHK_D3:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
                        else
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_LOOP_CHK_FIFO:
                        if (RXFifoFull == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
                                next_RXOverflow <= 1'b1;
                        end
                        else
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
                                next_RXFifoWEn <= 1'b1;
                                next_RXFifoData <= RXByteOldest;
                                next_RXByteOldest <= RXByteOld;
                                next_RXByteOld <= RXByte;
                        end
                `PROC_PKT_DATA_LOOP_FIFO_FULL:
                        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
                `PROC_PKT_DATA_LOOP_W_D:
                begin
                        next_RXFifoWEn <= 1'b0;
                        if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                        else if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                end
                `PROC_PKT_DATA_LOOP_DELAY:
                        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : getPkt_CurrentState
        if (rst)
                CurrState_getPkt <= `START_GP;
        else
                CurrState_getPkt <= NextState_getPkt;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : getPkt_RegOutput
        if (rst)
        begin
                RXByteOld <= 8'h00;
                RXByteOldest <= 8'h00;
                CRCError <= 1'b0;
                bitStuffError <= 1'b0;
                RXOverflow <= 1'b0;
                RXTimeOut <= 1'b0;
                NAKRxed <= 1'b0;
                stallRxed <= 1'b0;
                ACKRxed <= 1'b0;
                dataSequence <= 1'b0;
                RXByte <= 8'h00;
                RXStreamStatus <= 8'h00;
                RXPacketRdy <= 1'b0;
                RXFifoWEn <= 1'b0;
                RXFifoData <= 8'h00;
                RxPID <= 4'h0;
        end
        else
        begin
                RXByteOld <= next_RXByteOld;
                RXByteOldest <= next_RXByteOldest;
                CRCError <= next_CRCError;
                bitStuffError <= next_bitStuffError;
                RXOverflow <= next_RXOverflow;
                RXTimeOut <= next_RXTimeOut;
                NAKRxed <= next_NAKRxed;
                stallRxed <= next_stallRxed;
                ACKRxed <= next_ACKRxed;
                dataSequence <= next_dataSequence;
                RXByte <= next_RXByte;
                RXStreamStatus <= next_RXStreamStatus;
                RXPacketRdy <= next_RXPacketRdy;
                RXFifoWEn <= next_RXFifoWEn;
                RXFifoData <= next_RXFifoData;
                RxPID <= next_RxPID;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\getpacket.v`
11			`// Generated : 09/22/04 06:01:21`
12			`// From : c:\projects\USBHostSlave\RTL\hostController\getpacket.asf`
13			`// By : FSM2VHDL ver. 4.0.5.2`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`include "usbSerialInterfaceEngine_h.v"
22			`include "usbConstants_h.v"
23
24			`module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, clk, getPacketEn, rst);`
25			`input [7:0] RXDataIn;`
26			`input RXDataValid;`
27			`input RXFifoFull;`
28			`input [7:0] RXStreamStatusIn;`
29			`input SIERxTimeOut; // Single cycle pulse`
30			`input clk;`
31			`input getPacketEn;`
32			`input rst;`
33			`output [7:0] RXFifoData;`
34			`output RXFifoWEn;`
35			`output RXPacketRdy;`
36			`output [7:0] RXPktStatus;`
37			`output [3:0] RxPID;`
38
39			`wire [7:0] RXDataIn;`
40			`wire RXDataValid;`
41			`reg [7:0] RXFifoData, next_RXFifoData;`
42			`wire RXFifoFull;`
43			`reg RXFifoWEn, next_RXFifoWEn;`
44			`reg RXPacketRdy, next_RXPacketRdy;`
45			`reg [7:0] RXPktStatus;`
46			`wire [7:0] RXStreamStatusIn;`
47			`reg [3:0] RxPID, next_RxPID;`
48			`wire SIERxTimeOut;`
49			`wire clk;`
50			`wire getPacketEn;`
51			`wire rst;`
52
53			`// diagram signals declarations`
54			`reg ACKRxed, next_ACKRxed;`
55			`reg CRCError, next_CRCError;`
56			`reg NAKRxed, next_NAKRxed;`
57			`reg [7:0]RXByteOld, next_RXByteOld;`
58			`reg [7:0]RXByteOldest, next_RXByteOldest;`
59			`reg [7:0]RXByte, next_RXByte;`
60			`reg RXOverflow, next_RXOverflow;`
61			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
62			`reg RXTimeOut, next_RXTimeOut;`
63			`reg bitStuffError, next_bitStuffError;`
64			`reg dataSequence, next_dataSequence;`
65			`reg stallRxed, next_stallRxed;`
66
67			`// BINARY ENCODED state machine: getPkt`
68			`// State codes definitions:`
69			`define PROC_PKT_CHK_PID 5'b00000
70			`define PROC_PKT_HS 5'b00001
71			`define PROC_PKT_DATA_W_D1 5'b00010
72			`define PROC_PKT_DATA_CHK_D1 5'b00011
73			`define PROC_PKT_DATA_W_D2 5'b00100
74			`define PROC_PKT_DATA_FIN 5'b00101
75			`define PROC_PKT_DATA_CHK_D2 5'b00110
76			`define PROC_PKT_DATA_W_D3 5'b00111
77			`define PROC_PKT_DATA_CHK_D3 5'b01000
78			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
79			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
80			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
81			`define START_GP 5'b01100
82			`define WAIT_PKT 5'b01101
83			`define CHK_PKT_START 5'b01110
84			`define WAIT_EN 5'b01111
85			`define PKT_RDY 5'b10000
86			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
87
88			`reg [4:0] CurrState_getPkt;`
89			`reg [4:0] NextState_getPkt;`
90
91			`// Diagram actions (continuous assignments allowed only: assign ...)`
92			`always @`
93			`(CRCError or bitStuffError or`
94			`RXOverflow or RXTimeOut or`
95			`NAKRxed or stallRxed or`
96			`ACKRxed or dataSequence)`
97			`begin`
98			`RXPktStatus = {`
99			`dataSequence, ACKRxed,`
100			`stallRxed, NAKRxed,`
101			`RXTimeOut, RXOverflow,`
102			`bitStuffError, CRCError};`
103			`end`
104
105
106			`//--------------------------------------------------------------------`
107			`// Machine: getPkt`
108			`//--------------------------------------------------------------------`
109			`//----------------------------------`
110			`// NextState logic (combinatorial)`
111			`//----------------------------------`
112			`always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)`
113			`begin : getPkt_NextState`
114			`NextState_getPkt <= CurrState_getPkt;`
115			`// Set default values for outputs and signals`
116			`next_CRCError <= CRCError;`
117			`next_bitStuffError <= bitStuffError;`
118			`next_RXOverflow <= RXOverflow;`
119			`next_RXTimeOut <= RXTimeOut;`
120			`next_NAKRxed <= NAKRxed;`
121			`next_stallRxed <= stallRxed;`
122			`next_ACKRxed <= ACKRxed;`
123			`next_dataSequence <= dataSequence;`
124			`next_RXByte <= RXByte;`
125			`next_RXStreamStatus <= RXStreamStatus;`
126			`next_RxPID <= RxPID;`
127			`next_RXPacketRdy <= RXPacketRdy;`
128			`next_RXByteOldest <= RXByteOldest;`
129			`next_RXByteOld <= RXByteOld;`
130			`next_RXFifoWEn <= RXFifoWEn;`
131			`next_RXFifoData <= RXFifoData;`
132			`case (CurrState_getPkt) // synopsys parallel_case full_case`
133			`START_GP:
134			NextState_getPkt <= `WAIT_EN;
135			`WAIT_PKT:
136			`begin`
137			`next_CRCError <= 1'b0;`
138			`next_bitStuffError <= 1'b0;`
139			`next_RXOverflow <= 1'b0;`
140			`next_RXTimeOut <= 1'b0;`
141			`next_NAKRxed <= 1'b0;`
142			`next_stallRxed <= 1'b0;`
143			`next_ACKRxed <= 1'b0;`
144			`next_dataSequence <= 1'b0;`
145			`if (SIERxTimeOut == 1'b1)`
146			`begin`
147			NextState_getPkt <= `PKT_RDY;
148			`next_RXTimeOut <= 1'b1;`
149			`end`
150			`else if (RXDataValid == 1'b1)`
151			`begin`
152			NextState_getPkt <= `CHK_PKT_START;
153			`next_RXByte <= RXDataIn;`
154			`next_RXStreamStatus <= RXStreamStatusIn;`
155			`end`
156			`end`
157			`CHK_PKT_START:
158			if (RXStreamStatus == `RX_PACKET_START)
159			`begin`
160			NextState_getPkt <= `PROC_PKT_CHK_PID;
161			`next_RxPID <= RXByte[3:0];`
162			`end`
163			`else`
164			`begin`
165			NextState_getPkt <= `PKT_RDY;
166			`next_RXTimeOut <= 1'b1;`
167			`end`
168			`WAIT_EN:
169			`begin`
170			`next_RXPacketRdy <= 1'b0;`
171			`if (getPacketEn == 1'b1)`
172			NextState_getPkt <= `WAIT_PKT;
173			`end`
174			`PKT_RDY:
175			`begin`
176			`next_RXPacketRdy <= 1'b1;`
177			NextState_getPkt <= `WAIT_EN;
178			`end`
179			`PROC_PKT_CHK_PID:
180			if (RXByte[1:0] == `HANDSHAKE)
181			NextState_getPkt <= `PROC_PKT_HS;
182			else if (RXByte[1:0] == `DATA)
183			NextState_getPkt <= `PROC_PKT_DATA_W_D1;
184			`else`
185			NextState_getPkt <= `PKT_RDY;
186			`PROC_PKT_HS:
187			`if (RXDataValid == 1'b1)`
188			`begin`
189			NextState_getPkt <= `PKT_RDY;
190			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
191			next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
192			next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
193			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
194			`end`
195			`PROC_PKT_DATA_W_D1:
196			`if (RXDataValid == 1'b1)`
197			`begin`
198			NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
199			`next_RXByte <= RXDataIn;`
200			`next_RXStreamStatus <= RXStreamStatusIn;`
201			`end`
202			`PROC_PKT_DATA_CHK_D1:
203			if (RXStreamStatus == `RX_PACKET_STREAM)
204			`begin`
205			NextState_getPkt <= `PROC_PKT_DATA_W_D2;
206			`next_RXByteOldest <= RXByte;`
207			`end`
208			`else`
209			NextState_getPkt <= `PROC_PKT_DATA_FIN;
210			`PROC_PKT_DATA_W_D2:
211			`if (RXDataValid == 1'b1)`
212			`begin`
213			NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
214			`next_RXByte <= RXDataIn;`
215			`next_RXStreamStatus <= RXStreamStatusIn;`
216			`end`
217			`PROC_PKT_DATA_FIN:
218			`begin`
219			next_CRCError <= RXByte[`CRC_ERROR_BIT];
220			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
221			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
222			NextState_getPkt <= `PKT_RDY;
223			`end`
224			`PROC_PKT_DATA_CHK_D2:
225			if (RXStreamStatus == `RX_PACKET_STREAM)
226			`begin`
227			NextState_getPkt <= `PROC_PKT_DATA_W_D3;
228			`next_RXByteOld <= RXByte;`
229			`end`
230			`else`
231			NextState_getPkt <= `PROC_PKT_DATA_FIN;
232			`PROC_PKT_DATA_W_D3:
233			`if (RXDataValid == 1'b1)`
234			`begin`
235			NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
236			`next_RXByte <= RXDataIn;`
237			`next_RXStreamStatus <= RXStreamStatusIn;`
238			`end`
239			`PROC_PKT_DATA_CHK_D3:
240			if (RXStreamStatus == `RX_PACKET_STREAM)
241			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
242			`else`
243			NextState_getPkt <= `PROC_PKT_DATA_FIN;
244			`PROC_PKT_DATA_LOOP_CHK_FIFO:
245			`if (RXFifoFull == 1'b1)`
246			`begin`
247			NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
248			`next_RXOverflow <= 1'b1;`
249			`end`
250			`else`
251			`begin`
252			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
253			`next_RXFifoWEn <= 1'b1;`
254			`next_RXFifoData <= RXByteOldest;`
255			`next_RXByteOldest <= RXByteOld;`
256			`next_RXByteOld <= RXByte;`
257			`end`
258			`PROC_PKT_DATA_LOOP_FIFO_FULL:
259			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
260			`PROC_PKT_DATA_LOOP_W_D:
261			`begin`
262			`next_RXFifoWEn <= 1'b0;`
263			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
264			`begin`
265			NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
266			`next_RXByte <= RXDataIn;`
267			`next_RXStreamStatus <= RXStreamStatusIn;`
268			`end`
269			`else if (RXDataValid == 1'b1)`
270			`begin`
271			NextState_getPkt <= `PROC_PKT_DATA_FIN;
272			`next_RXByte <= RXDataIn;`
273			`next_RXStreamStatus <= RXStreamStatusIn;`
274			`end`
275			`end`
276			`PROC_PKT_DATA_LOOP_DELAY:
277			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
278			`endcase`
279			`end`
280
281			`//----------------------------------`
282			`// Current State Logic (sequential)`
283			`//----------------------------------`
284			`always @ (posedge clk)`
285			`begin : getPkt_CurrentState`
286			`if (rst)`
287			CurrState_getPkt <= `START_GP;
288			`else`
289			`CurrState_getPkt <= NextState_getPkt;`
290			`end`
291
292			`//----------------------------------`
293			`// Registered outputs logic`
294			`//----------------------------------`
295			`always @ (posedge clk)`
296			`begin : getPkt_RegOutput`
297			`if (rst)`
298			`begin`
299			`RXByteOld <= 8'h00;`
300			`RXByteOldest <= 8'h00;`
301			`CRCError <= 1'b0;`
302			`bitStuffError <= 1'b0;`
303			`RXOverflow <= 1'b0;`
304			`RXTimeOut <= 1'b0;`
305			`NAKRxed <= 1'b0;`
306			`stallRxed <= 1'b0;`
307			`ACKRxed <= 1'b0;`
308			`dataSequence <= 1'b0;`
309			`RXByte <= 8'h00;`
310			`RXStreamStatus <= 8'h00;`
311			`RXPacketRdy <= 1'b0;`
312			`RXFifoWEn <= 1'b0;`
313			`RXFifoData <= 8'h00;`
314			`RxPID <= 4'h0;`
315			`end`
316			`else`
317			`begin`
318			`RXByteOld <= next_RXByteOld;`
319			`RXByteOldest <= next_RXByteOldest;`
320			`CRCError <= next_CRCError;`
321			`bitStuffError <= next_bitStuffError;`
322			`RXOverflow <= next_RXOverflow;`
323			`RXTimeOut <= next_RXTimeOut;`
324			`NAKRxed <= next_NAKRxed;`
325			`stallRxed <= next_stallRxed;`
326			`ACKRxed <= next_ACKRxed;`
327			`dataSequence <= next_dataSequence;`
328			`RXByte <= next_RXByte;`
329			`RXStreamStatus <= next_RXStreamStatus;`
330			`RXPacketRdy <= next_RXPacketRdy;`
331			`RXFifoWEn <= next_RXFifoWEn;`
332			`RXFifoData <= next_RXFifoData;`
333			`RxPID <= next_RxPID;`
334			`end`
335			`end`
336
337			`endmodule`