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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// getpacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
 
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut, SIERxTimeOutEn);
input   clk;
input   getPacketEn;
input   rst;
input   [7:0]RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0]RXStreamStatusIn;
input   SIERxTimeOut;    // Single cycle pulse
output  [7:0]RXFifoData;
output  RXFifoWEn;
output  RXPacketRdy;
output  [3:0]RxPID;
output  [7:0]RXPktStatus;
output  SIERxTimeOutEn;
 
wire    clk;
wire    getPacketEn;
wire    rst;
wire    [7:0]RXDataIn;
wire    RXDataValid;
reg     [7:0]RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [3:0]RxPID, next_RxPID;
reg     [7:0]RXPktStatus;
wire    [7:0]RXStreamStatusIn;
wire    SIERxTimeOut;
reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
 
// diagram signals declarations
reg ACKRxed, next_ACKRxed;
reg bitStuffError, next_bitStuffError;
reg CRCError, next_CRCError;
reg dataSequence, next_dataSequence;
reg NAKRxed, next_NAKRxed;
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg RXOverflow, next_RXOverflow;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
reg RXTimeOut, next_RXTimeOut;
reg stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: getPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0]CurrState_getPkt, NextState_getPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(CRCError or bitStuffError or
RXOverflow or RXTimeOut or
NAKRxed or stallRxed or
ACKRxed or dataSequence)
begin
RXPktStatus <= {
dataSequence, ACKRxed,
stallRxed, NAKRxed,
RXTimeOut, RXOverflow,
bitStuffError, CRCError};
end
 
 
// Machine: getPkt
 
// NextState logic (combinatorial)
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_getPkt)
begin
  NextState_getPkt <= CurrState_getPkt;
  // Set default values for outputs and signals
  next_RXOverflow <= RXOverflow;
  next_NAKRxed <= NAKRxed;
  next_stallRxed <= stallRxed;
  next_ACKRxed <= ACKRxed;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RXByteOldest <= RXByteOldest;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_dataSequence <= dataSequence;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXTimeOut <= RXTimeOut;
  next_RxPID <= RxPID;
  next_SIERxTimeOutEn <= SIERxTimeOutEn;
  case (CurrState_getPkt)  // synopsys parallel_case full_case
    `START_GP:
    begin
      NextState_getPkt <= `WAIT_EN;
    end
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_NAKRxed <= 1'b0;
      next_stallRxed <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      next_SIERxTimeOutEn <= 1'b1;
      if (SIERxTimeOut == 1'b1)
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `CHK_PKT_START:
    begin
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_getPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      next_SIERxTimeOutEn <= 1'b0;
      if (getPacketEn == 1'b1)
      begin
        NextState_getPkt <= `WAIT_PKT;
      end
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_getPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
    begin
      if (RXByte[1:0] == `HANDSHAKE)
      begin
        NextState_getPkt <= `PROC_PKT_HS;
      end
      else if (RXByte[1:0] == `DATA)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
      end
      else
      begin
        NextState_getPkt <= `PKT_RDY;
      end
    end
    `PROC_PKT_HS:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    end
    `PROC_PKT_DATA_W_D1:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D1:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D2:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_getPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D3:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D3:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
    begin
      if (RXFifoFull == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
    begin
      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
    begin
      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_getPkt <= `START_GP;
  else
    CurrState_getPkt <= NextState_getPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    RXPacketRdy <= 1'b0;
    RxPID <= 4'h0;
    SIERxTimeOutEn <= 1'b0;
    RXOverflow <= 1'b0;
    NAKRxed <= 1'b0;
    stallRxed <= 1'b0;
    ACKRxed <= 1'b0;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXByteOldest <= 8'h00;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    dataSequence <= 1'b0;
    RXByteOld <= 8'h00;
    RXTimeOut <= 1'b0;
  end
  else
  begin
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    RXPacketRdy <= next_RXPacketRdy;
    RxPID <= next_RxPID;
    SIERxTimeOutEn <= next_SIERxTimeOutEn;
    RXOverflow <= next_RXOverflow;
    NAKRxed <= next_NAKRxed;
    stallRxed <= next_stallRxed;
    ACKRxed <= next_ACKRxed;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXByteOldest <= next_RXByteOldest;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    dataSequence <= next_dataSequence;
    RXByteOld <= next_RXByteOld;
    RXTimeOut <= next_RXTimeOut;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// getpacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	9	sfielding	`timescale 1ns / 1ps
46
47	5	sfielding	`include "usbSerialInterfaceEngine_h.v"
48			`include "usbConstants_h.v"
49
50	20	sfielding	`module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut, SIERxTimeOutEn);`
51	5	sfielding	`input clk;`
52			`input getPacketEn;`
53			`input rst;`
54			`input [7:0]RXDataIn;`
55			`input RXDataValid;`
56			`input RXFifoFull;`
57			`input [7:0]RXStreamStatusIn;`
58			`input SIERxTimeOut; // Single cycle pulse`
59			`output [7:0]RXFifoData;`
60			`output RXFifoWEn;`
61			`output RXPacketRdy;`
62			`output [3:0]RxPID;`
63			`output [7:0]RXPktStatus;`
64	20	sfielding	`output SIERxTimeOutEn;`
65	5	sfielding
66			`wire clk;`
67			`wire getPacketEn;`
68			`wire rst;`
69			`wire [7:0]RXDataIn;`
70			`wire RXDataValid;`
71			`reg [7:0]RXFifoData, next_RXFifoData;`
72			`wire RXFifoFull;`
73			`reg RXFifoWEn, next_RXFifoWEn;`
74			`reg RXPacketRdy, next_RXPacketRdy;`
75			`reg [3:0]RxPID, next_RxPID;`
76			`reg [7:0]RXPktStatus;`
77			`wire [7:0]RXStreamStatusIn;`
78			`wire SIERxTimeOut;`
79	20	sfielding	`reg SIERxTimeOutEn, next_SIERxTimeOutEn;`
80	5	sfielding
81			`// diagram signals declarations`
82			`reg ACKRxed, next_ACKRxed;`
83			`reg bitStuffError, next_bitStuffError;`
84			`reg CRCError, next_CRCError;`
85			`reg dataSequence, next_dataSequence;`
86			`reg NAKRxed, next_NAKRxed;`
87			`reg [7:0]RXByte, next_RXByte;`
88			`reg [7:0]RXByteOld, next_RXByteOld;`
89			`reg [7:0]RXByteOldest, next_RXByteOldest;`
90			`reg RXOverflow, next_RXOverflow;`
91			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
92			`reg RXTimeOut, next_RXTimeOut;`
93			`reg stallRxed, next_stallRxed;`
94
95			`// BINARY ENCODED state machine: getPkt`
96			`// State codes definitions:`
97			`define PROC_PKT_CHK_PID 5'b00000
98			`define PROC_PKT_HS 5'b00001
99			`define PROC_PKT_DATA_W_D1 5'b00010
100			`define PROC_PKT_DATA_CHK_D1 5'b00011
101			`define PROC_PKT_DATA_W_D2 5'b00100
102			`define PROC_PKT_DATA_FIN 5'b00101
103			`define PROC_PKT_DATA_CHK_D2 5'b00110
104			`define PROC_PKT_DATA_W_D3 5'b00111
105			`define PROC_PKT_DATA_CHK_D3 5'b01000
106			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
107			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
108			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
109			`define START_GP 5'b01100
110			`define WAIT_PKT 5'b01101
111			`define CHK_PKT_START 5'b01110
112			`define WAIT_EN 5'b01111
113			`define PKT_RDY 5'b10000
114			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
115
116			`reg [4:0]CurrState_getPkt, NextState_getPkt;`
117
118			`// Diagram actions (continuous assignments allowed only: assign ...)`
119			`always @`
120			`(CRCError or bitStuffError or`
121			`RXOverflow or RXTimeOut or`
122			`NAKRxed or stallRxed or`
123			`ACKRxed or dataSequence)`
124			`begin`
125			`RXPktStatus <= {`
126			`dataSequence, ACKRxed,`
127			`stallRxed, NAKRxed,`
128			`RXTimeOut, RXOverflow,`
129			`bitStuffError, CRCError};`
130			`end`
131
132
133			`// Machine: getPkt`
134
135			`// NextState logic (combinatorial)`
136	20	sfielding	`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_getPkt)`
137	5	sfielding	`begin`
138			`NextState_getPkt <= CurrState_getPkt;`
139			`// Set default values for outputs and signals`
140			`next_RXOverflow <= RXOverflow;`
141			`next_NAKRxed <= NAKRxed;`
142			`next_stallRxed <= stallRxed;`
143			`next_ACKRxed <= ACKRxed;`
144			`next_RXByte <= RXByte;`
145			`next_RXStreamStatus <= RXStreamStatus;`
146			`next_RXByteOldest <= RXByteOldest;`
147			`next_CRCError <= CRCError;`
148			`next_bitStuffError <= bitStuffError;`
149			`next_dataSequence <= dataSequence;`
150			`next_RXByteOld <= RXByteOld;`
151			`next_RXFifoWEn <= RXFifoWEn;`
152			`next_RXFifoData <= RXFifoData;`
153			`next_RXPacketRdy <= RXPacketRdy;`
154			`next_RXTimeOut <= RXTimeOut;`
155			`next_RxPID <= RxPID;`
156	20	sfielding	`next_SIERxTimeOutEn <= SIERxTimeOutEn;`
157	5	sfielding	`case (CurrState_getPkt) // synopsys parallel_case full_case`
158			`START_GP:
159			`begin`
160			NextState_getPkt <= `WAIT_EN;
161			`end`
162			`WAIT_PKT:
163			`begin`
164			`next_CRCError <= 1'b0;`
165			`next_bitStuffError <= 1'b0;`
166			`next_RXOverflow <= 1'b0;`
167			`next_RXTimeOut <= 1'b0;`
168			`next_NAKRxed <= 1'b0;`
169			`next_stallRxed <= 1'b0;`
170			`next_ACKRxed <= 1'b0;`
171			`next_dataSequence <= 1'b0;`
172	20	sfielding	`next_SIERxTimeOutEn <= 1'b1;`
173	5	sfielding	`if (SIERxTimeOut == 1'b1)`
174			`begin`
175			NextState_getPkt <= `PKT_RDY;
176			`next_RXTimeOut <= 1'b1;`
177			`end`
178			`else if (RXDataValid == 1'b1)`
179			`begin`
180			NextState_getPkt <= `CHK_PKT_START;
181			`next_RXByte <= RXDataIn;`
182			`next_RXStreamStatus <= RXStreamStatusIn;`
183			`end`
184			`end`
185			`CHK_PKT_START:
186			`begin`
187			if (RXStreamStatus == `RX_PACKET_START)
188			`begin`
189			NextState_getPkt <= `PROC_PKT_CHK_PID;
190			`next_RxPID <= RXByte[3:0];`
191			`end`
192			`else`
193			`begin`
194			NextState_getPkt <= `PKT_RDY;
195			`next_RXTimeOut <= 1'b1;`
196			`end`
197			`end`
198			`WAIT_EN:
199			`begin`
200			`next_RXPacketRdy <= 1'b0;`
201	20	sfielding	`next_SIERxTimeOutEn <= 1'b0;`
202	5	sfielding	`if (getPacketEn == 1'b1)`
203			`begin`
204			NextState_getPkt <= `WAIT_PKT;
205			`end`
206			`end`
207			`PKT_RDY:
208			`begin`
209			`next_RXPacketRdy <= 1'b1;`
210			NextState_getPkt <= `WAIT_EN;
211			`end`
212			`PROC_PKT_CHK_PID:
213			`begin`
214			if (RXByte[1:0] == `HANDSHAKE)
215			`begin`
216			NextState_getPkt <= `PROC_PKT_HS;
217			`end`
218			else if (RXByte[1:0] == `DATA)
219			`begin`
220			NextState_getPkt <= `PROC_PKT_DATA_W_D1;
221			`end`
222			`else`
223			`begin`
224			NextState_getPkt <= `PKT_RDY;
225			`end`
226			`end`
227			`PROC_PKT_HS:
228			`begin`
229			`if (RXDataValid == 1'b1)`
230			`begin`
231			NextState_getPkt <= `PKT_RDY;
232			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
233			next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
234			next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
235			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
236			`end`
237			`end`
238			`PROC_PKT_DATA_W_D1:
239			`begin`
240			`if (RXDataValid == 1'b1)`
241			`begin`
242			NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
243			`next_RXByte <= RXDataIn;`
244			`next_RXStreamStatus <= RXStreamStatusIn;`
245			`end`
246			`end`
247			`PROC_PKT_DATA_CHK_D1:
248			`begin`
249			if (RXStreamStatus == `RX_PACKET_STREAM)
250			`begin`
251			NextState_getPkt <= `PROC_PKT_DATA_W_D2;
252			`next_RXByteOldest <= RXByte;`
253			`end`
254			`else`
255			`begin`
256			NextState_getPkt <= `PROC_PKT_DATA_FIN;
257			`end`
258			`end`
259			`PROC_PKT_DATA_W_D2:
260			`begin`
261			`if (RXDataValid == 1'b1)`
262			`begin`
263			NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
264			`next_RXByte <= RXDataIn;`
265			`next_RXStreamStatus <= RXStreamStatusIn;`
266			`end`
267			`end`
268			`PROC_PKT_DATA_FIN:
269			`begin`
270			next_CRCError <= RXByte[`CRC_ERROR_BIT];
271			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
272			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
273			NextState_getPkt <= `PKT_RDY;
274			`end`
275			`PROC_PKT_DATA_CHK_D2:
276			`begin`
277			if (RXStreamStatus == `RX_PACKET_STREAM)
278			`begin`
279			NextState_getPkt <= `PROC_PKT_DATA_W_D3;
280			`next_RXByteOld <= RXByte;`
281			`end`
282			`else`
283			`begin`
284			NextState_getPkt <= `PROC_PKT_DATA_FIN;
285			`end`
286			`end`
287			`PROC_PKT_DATA_W_D3:
288			`begin`
289			`if (RXDataValid == 1'b1)`
290			`begin`
291			NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
292			`next_RXByte <= RXDataIn;`
293			`next_RXStreamStatus <= RXStreamStatusIn;`
294			`end`
295			`end`
296			`PROC_PKT_DATA_CHK_D3:
297			`begin`
298			if (RXStreamStatus == `RX_PACKET_STREAM)
299			`begin`
300			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
301			`end`
302			`else`
303			`begin`
304			NextState_getPkt <= `PROC_PKT_DATA_FIN;
305			`end`
306			`end`
307			`PROC_PKT_DATA_LOOP_CHK_FIFO:
308			`begin`
309			`if (RXFifoFull == 1'b1)`
310			`begin`
311			NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
312			`next_RXOverflow <= 1'b1;`
313			`end`
314			`else`
315			`begin`
316			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
317			`next_RXFifoWEn <= 1'b1;`
318			`next_RXFifoData <= RXByteOldest;`
319			`next_RXByteOldest <= RXByteOld;`
320			`next_RXByteOld <= RXByte;`
321			`end`
322			`end`
323			`PROC_PKT_DATA_LOOP_FIFO_FULL:
324			`begin`
325			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
326			`end`
327			`PROC_PKT_DATA_LOOP_W_D:
328			`begin`
329			`next_RXFifoWEn <= 1'b0;`
330			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
331			`begin`
332			NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
333			`next_RXByte <= RXDataIn;`
334			`next_RXStreamStatus <= RXStreamStatusIn;`
335			`end`
336			`else if (RXDataValid == 1'b1)`
337			`begin`
338			NextState_getPkt <= `PROC_PKT_DATA_FIN;
339			`next_RXByte <= RXDataIn;`
340			`next_RXStreamStatus <= RXStreamStatusIn;`
341			`end`
342			`end`
343			`PROC_PKT_DATA_LOOP_DELAY:
344			`begin`
345			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
346			`end`
347			`endcase`
348			`end`
349
350			`// Current State Logic (sequential)`
351			`always @ (posedge clk)`
352			`begin`
353			`if (rst)`
354			CurrState_getPkt <= `START_GP;
355			`else`
356			`CurrState_getPkt <= NextState_getPkt;`
357			`end`
358
359			`// Registered outputs logic`
360			`always @ (posedge clk)`
361			`begin`
362			`if (rst)`
363			`begin`
364			`RXFifoWEn <= 1'b0;`
365			`RXFifoData <= 8'h00;`
366			`RXPacketRdy <= 1'b0;`
367			`RxPID <= 4'h0;`
368	20	sfielding	`SIERxTimeOutEn <= 1'b0;`
369	5	sfielding	`RXOverflow <= 1'b0;`
370			`NAKRxed <= 1'b0;`
371			`stallRxed <= 1'b0;`
372			`ACKRxed <= 1'b0;`
373			`RXByte <= 8'h00;`
374			`RXStreamStatus <= 8'h00;`
375			`RXByteOldest <= 8'h00;`
376			`CRCError <= 1'b0;`
377			`bitStuffError <= 1'b0;`
378			`dataSequence <= 1'b0;`
379			`RXByteOld <= 8'h00;`
380			`RXTimeOut <= 1'b0;`
381			`end`
382			`else`
383			`begin`
384			`RXFifoWEn <= next_RXFifoWEn;`
385			`RXFifoData <= next_RXFifoData;`
386			`RXPacketRdy <= next_RXPacketRdy;`
387			`RxPID <= next_RxPID;`
388	20	sfielding	`SIERxTimeOutEn <= next_SIERxTimeOutEn;`
389	5	sfielding	`RXOverflow <= next_RXOverflow;`
390			`NAKRxed <= next_NAKRxed;`
391			`stallRxed <= next_stallRxed;`
392			`ACKRxed <= next_ACKRxed;`
393			`RXByte <= next_RXByte;`
394			`RXStreamStatus <= next_RXStreamStatus;`
395			`RXByteOldest <= next_RXByteOldest;`
396			`CRCError <= next_CRCError;`
397			`bitStuffError <= next_bitStuffError;`
398			`dataSequence <= next_dataSequence;`
399			`RXByteOld <= next_RXByteOld;`
400			`RXTimeOut <= next_RXTimeOut;`
401			`end`
402			`end`
403
404	2	sfielding	`endmodule`

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