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// File        : ../RTL/hostController/getpacket.v
// Generated   : 10/06/06 19:35:26
// From        : ../RTL/hostController/getpacket.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// getpacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, SIERxTimeOutEn, clk, getPacketEn, rst);
input   [7:0] RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0] RXStreamStatusIn;
input   SIERxTimeOut;           // Single cycle pulse
input   clk;
input   getPacketEn;
input   rst;
output  [7:0] RXFifoData;
output  RXFifoWEn;
output  RXPacketRdy;
output  [7:0] RXPktStatus;
output  [3:0] RxPID;
output  SIERxTimeOutEn;
 
wire    [7:0] RXDataIn;
wire    RXDataValid;
reg     [7:0] RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [7:0] RXPktStatus;
wire    [7:0] RXStreamStatusIn;
reg     [3:0] RxPID, next_RxPID;
wire    SIERxTimeOut;
reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
wire    clk;
wire    getPacketEn;
wire    rst;
 
// diagram signals declarations
reg  ACKRxed, next_ACKRxed;
reg  CRCError, next_CRCError;
reg  NAKRxed, next_NAKRxed;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXByte, next_RXByte;
reg  RXOverflow, next_RXOverflow;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
reg  RXTimeOut, next_RXTimeOut;
reg  bitStuffError, next_bitStuffError;
reg  dataSequence, next_dataSequence;
reg  stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: getPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0] CurrState_getPkt;
reg [4:0] NextState_getPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
 
always @
(CRCError or bitStuffError or
  RXOverflow or RXTimeOut or
  NAKRxed or stallRxed or
  ACKRxed or dataSequence)
begin
    RXPktStatus <= {
    dataSequence, ACKRxed,
    stallRxed, NAKRxed,
    RXTimeOut, RXOverflow,
    bitStuffError, CRCError};
end
 
//--------------------------------------------------------------------
// Machine: getPkt
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
begin : getPkt_NextState
        NextState_getPkt <= CurrState_getPkt;
        // Set default values for outputs and signals
        next_CRCError <= CRCError;
        next_bitStuffError <= bitStuffError;
        next_RXOverflow <= RXOverflow;
        next_RXTimeOut <= RXTimeOut;
        next_NAKRxed <= NAKRxed;
        next_stallRxed <= stallRxed;
        next_ACKRxed <= ACKRxed;
        next_dataSequence <= dataSequence;
        next_SIERxTimeOutEn <= SIERxTimeOutEn;
        next_RXByte <= RXByte;
        next_RXStreamStatus <= RXStreamStatus;
        next_RxPID <= RxPID;
        next_RXPacketRdy <= RXPacketRdy;
        next_RXByteOldest <= RXByteOldest;
        next_RXByteOld <= RXByteOld;
        next_RXFifoWEn <= RXFifoWEn;
        next_RXFifoData <= RXFifoData;
        case (CurrState_getPkt)
                `START_GP:
                        NextState_getPkt <= `WAIT_EN;
                `WAIT_PKT:
                begin
                        next_CRCError <= 1'b0;
                        next_bitStuffError <= 1'b0;
                        next_RXOverflow <= 1'b0;
                        next_RXTimeOut <= 1'b0;
                        next_NAKRxed <= 1'b0;
                        next_stallRxed <= 1'b0;
                        next_ACKRxed <= 1'b0;
                        next_dataSequence <= 1'b0;
                        next_SIERxTimeOutEn <= 1'b1;
                        if (SIERxTimeOut == 1'b1)
                        begin
                                NextState_getPkt <= `PKT_RDY;
                                next_RXTimeOut <= 1'b1;
                        end
                        else if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `CHK_PKT_START;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                end
                `CHK_PKT_START:
                        if (RXStreamStatus == `RX_PACKET_START)
                        begin
                                NextState_getPkt <= `PROC_PKT_CHK_PID;
                                next_RxPID <= RXByte[3:0];
                        end
                        else
                        begin
                                NextState_getPkt <= `PKT_RDY;
                                next_RXTimeOut <= 1'b1;
                        end
                `WAIT_EN:
                begin
                        next_RXPacketRdy <= 1'b0;
                        next_SIERxTimeOutEn <= 1'b0;
                        if (getPacketEn == 1'b1)
                                NextState_getPkt <= `WAIT_PKT;
                end
                `PKT_RDY:
                begin
                        next_RXPacketRdy <= 1'b1;
                        NextState_getPkt <= `WAIT_EN;
                end
                `PROC_PKT_CHK_PID:
                        if (RXByte[1:0] == `HANDSHAKE)
                                NextState_getPkt <= `PROC_PKT_HS;
                        else if (RXByte[1:0] == `DATA)
                                NextState_getPkt <= `PROC_PKT_DATA_W_D1;
                        else
                                NextState_getPkt <= `PKT_RDY;
                `PROC_PKT_HS:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PKT_RDY;
                                next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
                                next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
                                next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
                                next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
                        end
                `PROC_PKT_DATA_W_D1:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_CHK_D1:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_W_D2;
                                next_RXByteOldest <= RXByte;
                        end
                        else
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_W_D2:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_FIN:
                begin
                        next_CRCError <= RXByte[`CRC_ERROR_BIT];
                        next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
                        next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
                        NextState_getPkt <= `PKT_RDY;
                end
                `PROC_PKT_DATA_CHK_D2:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_W_D3;
                                next_RXByteOld <= RXByte;
                        end
                        else
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_W_D3:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_CHK_D3:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
                        else
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_LOOP_CHK_FIFO:
                        if (RXFifoFull == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
                                next_RXOverflow <= 1'b1;
                        end
                        else
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
                                next_RXFifoWEn <= 1'b1;
                                next_RXFifoData <= RXByteOldest;
                                next_RXByteOldest <= RXByteOld;
                                next_RXByteOld <= RXByte;
                        end
                `PROC_PKT_DATA_LOOP_FIFO_FULL:
                        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
                `PROC_PKT_DATA_LOOP_W_D:
                begin
                        next_RXFifoWEn <= 1'b0;
                        if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                        else if (RXDataValid == 1'b1)
                        begin
                                NextState_getPkt <= `PROC_PKT_DATA_FIN;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                end
                `PROC_PKT_DATA_LOOP_DELAY:
                        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : getPkt_CurrentState
        if (rst)
                CurrState_getPkt <= `START_GP;
        else
                CurrState_getPkt <= NextState_getPkt;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : getPkt_RegOutput
        if (rst)
        begin
                RXByteOld <= 8'h00;
                RXByteOldest <= 8'h00;
                CRCError <= 1'b0;
                bitStuffError <= 1'b0;
                RXOverflow <= 1'b0;
                RXTimeOut <= 1'b0;
                NAKRxed <= 1'b0;
                stallRxed <= 1'b0;
                ACKRxed <= 1'b0;
                dataSequence <= 1'b0;
                RXByte <= 8'h00;
                RXStreamStatus <= 8'h00;
                RXPacketRdy <= 1'b0;
                RXFifoWEn <= 1'b0;
                RXFifoData <= 8'h00;
                RxPID <= 4'h0;
                SIERxTimeOutEn <= 1'b0;
        end
        else
        begin
                RXByteOld <= next_RXByteOld;
                RXByteOldest <= next_RXByteOldest;
                CRCError <= next_CRCError;
                bitStuffError <= next_bitStuffError;
                RXOverflow <= next_RXOverflow;
                RXTimeOut <= next_RXTimeOut;
                NAKRxed <= next_NAKRxed;
                stallRxed <= next_stallRxed;
                ACKRxed <= next_ACKRxed;
                dataSequence <= next_dataSequence;
                RXByte <= next_RXByte;
                RXStreamStatus <= next_RXStreamStatus;
                RXPacketRdy <= next_RXPacketRdy;
                RXFifoWEn <= next_RXFifoWEn;
                RXFifoData <= next_RXFifoData;
                RxPID <= next_RxPID;
                SIERxTimeOutEn <= next_SIERxTimeOutEn;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2	22	sfielding	`// File : ../RTL/hostController/getpacket.v`
3			`// Generated : 10/06/06 19:35:26`
4			`// From : ../RTL/hostController/getpacket.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7	5	sfielding	`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// getpacket`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50	22	sfielding	`include "timescale.v"
51	9	sfielding
52	5	sfielding	`include "usbSerialInterfaceEngine_h.v"
53			`include "usbConstants_h.v"
54
55	22	sfielding	`module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, SIERxTimeOutEn, clk, getPacketEn, rst);`
56			`input [7:0] RXDataIn;`
57			`input RXDataValid;`
58			`input RXFifoFull;`
59			`input [7:0] RXStreamStatusIn;`
60			`input SIERxTimeOut; // Single cycle pulse`
61	5	sfielding	`input clk;`
62			`input getPacketEn;`
63			`input rst;`
64	22	sfielding	`output [7:0] RXFifoData;`
65	5	sfielding	`output RXFifoWEn;`
66			`output RXPacketRdy;`
67	22	sfielding	`output [7:0] RXPktStatus;`
68			`output [3:0] RxPID;`
69	20	sfielding	`output SIERxTimeOutEn;`
70	5	sfielding
71	22	sfielding	`wire [7:0] RXDataIn;`
72	5	sfielding	`wire RXDataValid;`
73	22	sfielding	`reg [7:0] RXFifoData, next_RXFifoData;`
74	5	sfielding	`wire RXFifoFull;`
75			`reg RXFifoWEn, next_RXFifoWEn;`
76			`reg RXPacketRdy, next_RXPacketRdy;`
77	22	sfielding	`reg [7:0] RXPktStatus;`
78			`wire [7:0] RXStreamStatusIn;`
79			`reg [3:0] RxPID, next_RxPID;`
80	5	sfielding	`wire SIERxTimeOut;`
81	20	sfielding	`reg SIERxTimeOutEn, next_SIERxTimeOutEn;`
82	22	sfielding	`wire clk;`
83			`wire getPacketEn;`
84			`wire rst;`
85	5	sfielding
86			`// diagram signals declarations`
87	22	sfielding	`reg ACKRxed, next_ACKRxed;`
88			`reg CRCError, next_CRCError;`
89			`reg NAKRxed, next_NAKRxed;`
90	5	sfielding	`reg [7:0]RXByteOld, next_RXByteOld;`
91			`reg [7:0]RXByteOldest, next_RXByteOldest;`
92	22	sfielding	`reg [7:0]RXByte, next_RXByte;`
93			`reg RXOverflow, next_RXOverflow;`
94	5	sfielding	`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
95	22	sfielding	`reg RXTimeOut, next_RXTimeOut;`
96			`reg bitStuffError, next_bitStuffError;`
97			`reg dataSequence, next_dataSequence;`
98			`reg stallRxed, next_stallRxed;`
99	5	sfielding
100			`// BINARY ENCODED state machine: getPkt`
101			`// State codes definitions:`
102			`define PROC_PKT_CHK_PID 5'b00000
103			`define PROC_PKT_HS 5'b00001
104			`define PROC_PKT_DATA_W_D1 5'b00010
105			`define PROC_PKT_DATA_CHK_D1 5'b00011
106			`define PROC_PKT_DATA_W_D2 5'b00100
107			`define PROC_PKT_DATA_FIN 5'b00101
108			`define PROC_PKT_DATA_CHK_D2 5'b00110
109			`define PROC_PKT_DATA_W_D3 5'b00111
110			`define PROC_PKT_DATA_CHK_D3 5'b01000
111			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
112			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
113			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
114			`define START_GP 5'b01100
115			`define WAIT_PKT 5'b01101
116			`define CHK_PKT_START 5'b01110
117			`define WAIT_EN 5'b01111
118			`define PKT_RDY 5'b10000
119			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
120
121	22	sfielding	`reg [4:0] CurrState_getPkt;`
122			`reg [4:0] NextState_getPkt;`
123	5	sfielding
124			`// Diagram actions (continuous assignments allowed only: assign ...)`
125	22	sfielding
126	5	sfielding	`always @`
127			`(CRCError or bitStuffError or`
128	22	sfielding	`RXOverflow or RXTimeOut or`
129			`NAKRxed or stallRxed or`
130			`ACKRxed or dataSequence)`
131	5	sfielding	`begin`
132	22	sfielding	`RXPktStatus <= {`
133			`dataSequence, ACKRxed,`
134			`stallRxed, NAKRxed,`
135			`RXTimeOut, RXOverflow,`
136			`bitStuffError, CRCError};`
137	5	sfielding	`end`
138
139	22	sfielding	`//--------------------------------------------------------------------`
140	5	sfielding	`// Machine: getPkt`
141	22	sfielding	`//--------------------------------------------------------------------`
142			`//----------------------------------`
143			`// Next State Logic (combinatorial)`
144			`//----------------------------------`
145			`always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)`
146			`begin : getPkt_NextState`
147			`NextState_getPkt <= CurrState_getPkt;`
148			`// Set default values for outputs and signals`
149			`next_CRCError <= CRCError;`
150			`next_bitStuffError <= bitStuffError;`
151			`next_RXOverflow <= RXOverflow;`
152			`next_RXTimeOut <= RXTimeOut;`
153			`next_NAKRxed <= NAKRxed;`
154			`next_stallRxed <= stallRxed;`
155			`next_ACKRxed <= ACKRxed;`
156			`next_dataSequence <= dataSequence;`
157			`next_SIERxTimeOutEn <= SIERxTimeOutEn;`
158			`next_RXByte <= RXByte;`
159			`next_RXStreamStatus <= RXStreamStatus;`
160			`next_RxPID <= RxPID;`
161			`next_RXPacketRdy <= RXPacketRdy;`
162			`next_RXByteOldest <= RXByteOldest;`
163			`next_RXByteOld <= RXByteOld;`
164			`next_RXFifoWEn <= RXFifoWEn;`
165			`next_RXFifoData <= RXFifoData;`
166			`case (CurrState_getPkt)`
167			`START_GP:
168			NextState_getPkt <= `WAIT_EN;
169			`WAIT_PKT:
170			`begin`
171			`next_CRCError <= 1'b0;`
172			`next_bitStuffError <= 1'b0;`
173			`next_RXOverflow <= 1'b0;`
174			`next_RXTimeOut <= 1'b0;`
175			`next_NAKRxed <= 1'b0;`
176			`next_stallRxed <= 1'b0;`
177			`next_ACKRxed <= 1'b0;`
178			`next_dataSequence <= 1'b0;`
179			`next_SIERxTimeOutEn <= 1'b1;`
180			`if (SIERxTimeOut == 1'b1)`
181			`begin`
182			NextState_getPkt <= `PKT_RDY;
183			`next_RXTimeOut <= 1'b1;`
184			`end`
185			`else if (RXDataValid == 1'b1)`
186			`begin`
187			NextState_getPkt <= `CHK_PKT_START;
188			`next_RXByte <= RXDataIn;`
189			`next_RXStreamStatus <= RXStreamStatusIn;`
190			`end`
191			`end`
192			`CHK_PKT_START:
193			if (RXStreamStatus == `RX_PACKET_START)
194			`begin`
195			NextState_getPkt <= `PROC_PKT_CHK_PID;
196			`next_RxPID <= RXByte[3:0];`
197			`end`
198			`else`
199			`begin`
200			NextState_getPkt <= `PKT_RDY;
201			`next_RXTimeOut <= 1'b1;`
202			`end`
203			`WAIT_EN:
204			`begin`
205			`next_RXPacketRdy <= 1'b0;`
206			`next_SIERxTimeOutEn <= 1'b0;`
207			`if (getPacketEn == 1'b1)`
208			NextState_getPkt <= `WAIT_PKT;
209			`end`
210			`PKT_RDY:
211			`begin`
212			`next_RXPacketRdy <= 1'b1;`
213			NextState_getPkt <= `WAIT_EN;
214			`end`
215			`PROC_PKT_CHK_PID:
216			if (RXByte[1:0] == `HANDSHAKE)
217			NextState_getPkt <= `PROC_PKT_HS;
218			else if (RXByte[1:0] == `DATA)
219			NextState_getPkt <= `PROC_PKT_DATA_W_D1;
220			`else`
221			NextState_getPkt <= `PKT_RDY;
222			`PROC_PKT_HS:
223			`if (RXDataValid == 1'b1)`
224			`begin`
225			NextState_getPkt <= `PKT_RDY;
226			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
227			next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
228			next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
229			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
230			`end`
231			`PROC_PKT_DATA_W_D1:
232			`if (RXDataValid == 1'b1)`
233			`begin`
234			NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
235			`next_RXByte <= RXDataIn;`
236			`next_RXStreamStatus <= RXStreamStatusIn;`
237			`end`
238			`PROC_PKT_DATA_CHK_D1:
239			if (RXStreamStatus == `RX_PACKET_STREAM)
240			`begin`
241			NextState_getPkt <= `PROC_PKT_DATA_W_D2;
242			`next_RXByteOldest <= RXByte;`
243			`end`
244			`else`
245			NextState_getPkt <= `PROC_PKT_DATA_FIN;
246			`PROC_PKT_DATA_W_D2:
247			`if (RXDataValid == 1'b1)`
248			`begin`
249			NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
250			`next_RXByte <= RXDataIn;`
251			`next_RXStreamStatus <= RXStreamStatusIn;`
252			`end`
253			`PROC_PKT_DATA_FIN:
254			`begin`
255			next_CRCError <= RXByte[`CRC_ERROR_BIT];
256			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
257			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
258			NextState_getPkt <= `PKT_RDY;
259			`end`
260			`PROC_PKT_DATA_CHK_D2:
261			if (RXStreamStatus == `RX_PACKET_STREAM)
262			`begin`
263			NextState_getPkt <= `PROC_PKT_DATA_W_D3;
264			`next_RXByteOld <= RXByte;`
265			`end`
266			`else`
267			NextState_getPkt <= `PROC_PKT_DATA_FIN;
268			`PROC_PKT_DATA_W_D3:
269			`if (RXDataValid == 1'b1)`
270			`begin`
271			NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
272			`next_RXByte <= RXDataIn;`
273			`next_RXStreamStatus <= RXStreamStatusIn;`
274			`end`
275			`PROC_PKT_DATA_CHK_D3:
276			if (RXStreamStatus == `RX_PACKET_STREAM)
277			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
278			`else`
279			NextState_getPkt <= `PROC_PKT_DATA_FIN;
280			`PROC_PKT_DATA_LOOP_CHK_FIFO:
281			`if (RXFifoFull == 1'b1)`
282			`begin`
283			NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
284			`next_RXOverflow <= 1'b1;`
285			`end`
286			`else`
287			`begin`
288			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
289			`next_RXFifoWEn <= 1'b1;`
290			`next_RXFifoData <= RXByteOldest;`
291			`next_RXByteOldest <= RXByteOld;`
292			`next_RXByteOld <= RXByte;`
293			`end`
294			`PROC_PKT_DATA_LOOP_FIFO_FULL:
295			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
296			`PROC_PKT_DATA_LOOP_W_D:
297			`begin`
298			`next_RXFifoWEn <= 1'b0;`
299			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
300			`begin`
301			NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
302			`next_RXByte <= RXDataIn;`
303			`next_RXStreamStatus <= RXStreamStatusIn;`
304			`end`
305			`else if (RXDataValid == 1'b1)`
306			`begin`
307			NextState_getPkt <= `PROC_PKT_DATA_FIN;
308			`next_RXByte <= RXDataIn;`
309			`next_RXStreamStatus <= RXStreamStatusIn;`
310			`end`
311			`end`
312			`PROC_PKT_DATA_LOOP_DELAY:
313			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
314			`endcase`
315	5	sfielding	`end`
316
317	22	sfielding	`//----------------------------------`
318	5	sfielding	`// Current State Logic (sequential)`
319	22	sfielding	`//----------------------------------`
320	5	sfielding	`always @ (posedge clk)`
321	22	sfielding	`begin : getPkt_CurrentState`
322			`if (rst)`
323			CurrState_getPkt <= `START_GP;
324			`else`
325			`CurrState_getPkt <= NextState_getPkt;`
326	5	sfielding	`end`
327
328	22	sfielding	`//----------------------------------`
329	5	sfielding	`// Registered outputs logic`
330	22	sfielding	`//----------------------------------`
331	5	sfielding	`always @ (posedge clk)`
332	22	sfielding	`begin : getPkt_RegOutput`
333			`if (rst)`
334			`begin`
335			`RXByteOld <= 8'h00;`
336			`RXByteOldest <= 8'h00;`
337			`CRCError <= 1'b0;`
338			`bitStuffError <= 1'b0;`
339			`RXOverflow <= 1'b0;`
340			`RXTimeOut <= 1'b0;`
341			`NAKRxed <= 1'b0;`
342			`stallRxed <= 1'b0;`
343			`ACKRxed <= 1'b0;`
344			`dataSequence <= 1'b0;`
345			`RXByte <= 8'h00;`
346			`RXStreamStatus <= 8'h00;`
347			`RXPacketRdy <= 1'b0;`
348			`RXFifoWEn <= 1'b0;`
349			`RXFifoData <= 8'h00;`
350			`RxPID <= 4'h0;`
351			`SIERxTimeOutEn <= 1'b0;`
352			`end`
353			`else`
354			`begin`
355			`RXByteOld <= next_RXByteOld;`
356			`RXByteOldest <= next_RXByteOldest;`
357			`CRCError <= next_CRCError;`
358			`bitStuffError <= next_bitStuffError;`
359			`RXOverflow <= next_RXOverflow;`
360			`RXTimeOut <= next_RXTimeOut;`
361			`NAKRxed <= next_NAKRxed;`
362			`stallRxed <= next_stallRxed;`
363			`ACKRxed <= next_ACKRxed;`
364			`dataSequence <= next_dataSequence;`
365			`RXByte <= next_RXByte;`
366			`RXStreamStatus <= next_RXStreamStatus;`
367			`RXPacketRdy <= next_RXPacketRdy;`
368			`RXFifoWEn <= next_RXFifoWEn;`
369			`RXFifoData <= next_RXFifoData;`
370			`RxPID <= next_RxPID;`
371			`SIERxTimeOutEn <= next_SIERxTimeOutEn;`
372			`end`
373	5	sfielding	`end`
374
375	2	sfielding	`endmodule`

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