URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// getpacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: getpacket.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
input   clk;
input   getPacketEn;
input   rst;
input   [7:0]RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0]RXStreamStatusIn;
input   SIERxTimeOut;    // Single cycle pulse
output  [7:0]RXFifoData;
output  RXFifoWEn;
output  RXPacketRdy;
output  [3:0]RxPID;
output  [7:0]RXPktStatus;
 
wire    clk;
wire    getPacketEn;
wire    rst;
wire    [7:0]RXDataIn;
wire    RXDataValid;
reg     [7:0]RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [3:0]RxPID, next_RxPID;
reg     [7:0]RXPktStatus;
wire    [7:0]RXStreamStatusIn;
wire    SIERxTimeOut;
 
// diagram signals declarations
reg ACKRxed, next_ACKRxed;
reg bitStuffError, next_bitStuffError;
reg CRCError, next_CRCError;
reg dataSequence, next_dataSequence;
reg NAKRxed, next_NAKRxed;
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg RXOverflow, next_RXOverflow;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
reg RXTimeOut, next_RXTimeOut;
reg stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: getPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0]CurrState_getPkt, NextState_getPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(CRCError or bitStuffError or
RXOverflow or RXTimeOut or
NAKRxed or stallRxed or
ACKRxed or dataSequence)
begin
RXPktStatus <= {
dataSequence, ACKRxed,
stallRxed, NAKRxed,
RXTimeOut, RXOverflow,
bitStuffError, CRCError};
end
 
 
// Machine: getPkt
 
// NextState logic (combinatorial)
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
begin
  NextState_getPkt <= CurrState_getPkt;
  // Set default values for outputs and signals
  next_RXOverflow <= RXOverflow;
  next_NAKRxed <= NAKRxed;
  next_stallRxed <= stallRxed;
  next_ACKRxed <= ACKRxed;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RXByteOldest <= RXByteOldest;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_dataSequence <= dataSequence;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXTimeOut <= RXTimeOut;
  next_RxPID <= RxPID;
  case (CurrState_getPkt)  // synopsys parallel_case full_case
    `START_GP:
    begin
      NextState_getPkt <= `WAIT_EN;
    end
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_NAKRxed <= 1'b0;
      next_stallRxed <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      if (SIERxTimeOut == 1'b1)
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `CHK_PKT_START:
    begin
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_getPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      if (getPacketEn == 1'b1)
      begin
        NextState_getPkt <= `WAIT_PKT;
      end
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_getPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
    begin
      if (RXByte[1:0] == `HANDSHAKE)
      begin
        NextState_getPkt <= `PROC_PKT_HS;
      end
      else if (RXByte[1:0] == `DATA)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
      end
      else
      begin
        NextState_getPkt <= `PKT_RDY;
      end
    end
    `PROC_PKT_HS:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    end
    `PROC_PKT_DATA_W_D1:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D1:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D2:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_getPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D3:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D3:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
    begin
      if (RXFifoFull == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
    begin
      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
    begin
      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_getPkt <= `START_GP;
  else
    CurrState_getPkt <= NextState_getPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    RXPacketRdy <= 1'b0;
    RxPID <= 4'h0;
    RXOverflow <= 1'b0;
    NAKRxed <= 1'b0;
    stallRxed <= 1'b0;
    ACKRxed <= 1'b0;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXByteOldest <= 8'h00;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    dataSequence <= 1'b0;
    RXByteOld <= 8'h00;
    RXTimeOut <= 1'b0;
  end
  else
  begin
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    RXPacketRdy <= next_RXPacketRdy;
    RxPID <= next_RxPID;
    RXOverflow <= next_RXOverflow;
    NAKRxed <= next_NAKRxed;
    stallRxed <= next_stallRxed;
    ACKRxed <= next_ACKRxed;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXByteOldest <= next_RXByteOldest;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    dataSequence <= next_dataSequence;
    RXByteOld <= next_RXByteOld;
    RXTimeOut <= next_RXTimeOut;
  end
end
 
endmodule

Browse

Tools

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// getpacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// $Id: getpacket.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbConstants_h.v"
53
54			`module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);`
55			`input clk;`
56			`input getPacketEn;`
57			`input rst;`
58			`input [7:0]RXDataIn;`
59			`input RXDataValid;`
60			`input RXFifoFull;`
61			`input [7:0]RXStreamStatusIn;`
62			`input SIERxTimeOut; // Single cycle pulse`
63			`output [7:0]RXFifoData;`
64			`output RXFifoWEn;`
65			`output RXPacketRdy;`
66			`output [3:0]RxPID;`
67			`output [7:0]RXPktStatus;`
68
69			`wire clk;`
70			`wire getPacketEn;`
71			`wire rst;`
72			`wire [7:0]RXDataIn;`
73			`wire RXDataValid;`
74			`reg [7:0]RXFifoData, next_RXFifoData;`
75			`wire RXFifoFull;`
76			`reg RXFifoWEn, next_RXFifoWEn;`
77			`reg RXPacketRdy, next_RXPacketRdy;`
78			`reg [3:0]RxPID, next_RxPID;`
79			`reg [7:0]RXPktStatus;`
80			`wire [7:0]RXStreamStatusIn;`
81			`wire SIERxTimeOut;`
82
83			`// diagram signals declarations`
84			`reg ACKRxed, next_ACKRxed;`
85			`reg bitStuffError, next_bitStuffError;`
86			`reg CRCError, next_CRCError;`
87			`reg dataSequence, next_dataSequence;`
88			`reg NAKRxed, next_NAKRxed;`
89			`reg [7:0]RXByte, next_RXByte;`
90			`reg [7:0]RXByteOld, next_RXByteOld;`
91			`reg [7:0]RXByteOldest, next_RXByteOldest;`
92			`reg RXOverflow, next_RXOverflow;`
93			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
94			`reg RXTimeOut, next_RXTimeOut;`
95			`reg stallRxed, next_stallRxed;`
96
97			`// BINARY ENCODED state machine: getPkt`
98			`// State codes definitions:`
99			`define PROC_PKT_CHK_PID 5'b00000
100			`define PROC_PKT_HS 5'b00001
101			`define PROC_PKT_DATA_W_D1 5'b00010
102			`define PROC_PKT_DATA_CHK_D1 5'b00011
103			`define PROC_PKT_DATA_W_D2 5'b00100
104			`define PROC_PKT_DATA_FIN 5'b00101
105			`define PROC_PKT_DATA_CHK_D2 5'b00110
106			`define PROC_PKT_DATA_W_D3 5'b00111
107			`define PROC_PKT_DATA_CHK_D3 5'b01000
108			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
109			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
110			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
111			`define START_GP 5'b01100
112			`define WAIT_PKT 5'b01101
113			`define CHK_PKT_START 5'b01110
114			`define WAIT_EN 5'b01111
115			`define PKT_RDY 5'b10000
116			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
117
118			`reg [4:0]CurrState_getPkt, NextState_getPkt;`
119
120			`// Diagram actions (continuous assignments allowed only: assign ...)`
121			`always @`
122			`(CRCError or bitStuffError or`
123			`RXOverflow or RXTimeOut or`
124			`NAKRxed or stallRxed or`
125			`ACKRxed or dataSequence)`
126			`begin`
127			`RXPktStatus <= {`
128			`dataSequence, ACKRxed,`
129			`stallRxed, NAKRxed,`
130			`RXTimeOut, RXOverflow,`
131			`bitStuffError, CRCError};`
132			`end`
133
134
135			`// Machine: getPkt`
136
137			`// NextState logic (combinatorial)`
138			`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)`
139			`begin`
140			`NextState_getPkt <= CurrState_getPkt;`
141			`// Set default values for outputs and signals`
142			`next_RXOverflow <= RXOverflow;`
143			`next_NAKRxed <= NAKRxed;`
144			`next_stallRxed <= stallRxed;`
145			`next_ACKRxed <= ACKRxed;`
146			`next_RXByte <= RXByte;`
147			`next_RXStreamStatus <= RXStreamStatus;`
148			`next_RXByteOldest <= RXByteOldest;`
149			`next_CRCError <= CRCError;`
150			`next_bitStuffError <= bitStuffError;`
151			`next_dataSequence <= dataSequence;`
152			`next_RXByteOld <= RXByteOld;`
153			`next_RXFifoWEn <= RXFifoWEn;`
154			`next_RXFifoData <= RXFifoData;`
155			`next_RXPacketRdy <= RXPacketRdy;`
156			`next_RXTimeOut <= RXTimeOut;`
157			`next_RxPID <= RxPID;`
158			`case (CurrState_getPkt) // synopsys parallel_case full_case`
159			`START_GP:
160			`begin`
161			NextState_getPkt <= `WAIT_EN;
162			`end`
163			`WAIT_PKT:
164			`begin`
165			`next_CRCError <= 1'b0;`
166			`next_bitStuffError <= 1'b0;`
167			`next_RXOverflow <= 1'b0;`
168			`next_RXTimeOut <= 1'b0;`
169			`next_NAKRxed <= 1'b0;`
170			`next_stallRxed <= 1'b0;`
171			`next_ACKRxed <= 1'b0;`
172			`next_dataSequence <= 1'b0;`
173			`if (SIERxTimeOut == 1'b1)`
174			`begin`
175			NextState_getPkt <= `PKT_RDY;
176			`next_RXTimeOut <= 1'b1;`
177			`end`
178			`else if (RXDataValid == 1'b1)`
179			`begin`
180			NextState_getPkt <= `CHK_PKT_START;
181			`next_RXByte <= RXDataIn;`
182			`next_RXStreamStatus <= RXStreamStatusIn;`
183			`end`
184			`end`
185			`CHK_PKT_START:
186			`begin`
187			if (RXStreamStatus == `RX_PACKET_START)
188			`begin`
189			NextState_getPkt <= `PROC_PKT_CHK_PID;
190			`next_RxPID <= RXByte[3:0];`
191			`end`
192			`else`
193			`begin`
194			NextState_getPkt <= `PKT_RDY;
195			`next_RXTimeOut <= 1'b1;`
196			`end`
197			`end`
198			`WAIT_EN:
199			`begin`
200			`next_RXPacketRdy <= 1'b0;`
201			`if (getPacketEn == 1'b1)`
202			`begin`
203			NextState_getPkt <= `WAIT_PKT;
204			`end`
205			`end`
206			`PKT_RDY:
207			`begin`
208			`next_RXPacketRdy <= 1'b1;`
209			NextState_getPkt <= `WAIT_EN;
210			`end`
211			`PROC_PKT_CHK_PID:
212			`begin`
213			if (RXByte[1:0] == `HANDSHAKE)
214			`begin`
215			NextState_getPkt <= `PROC_PKT_HS;
216			`end`
217			else if (RXByte[1:0] == `DATA)
218			`begin`
219			NextState_getPkt <= `PROC_PKT_DATA_W_D1;
220			`end`
221			`else`
222			`begin`
223			NextState_getPkt <= `PKT_RDY;
224			`end`
225			`end`
226			`PROC_PKT_HS:
227			`begin`
228			`if (RXDataValid == 1'b1)`
229			`begin`
230			NextState_getPkt <= `PKT_RDY;
231			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
232			next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
233			next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
234			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
235			`end`
236			`end`
237			`PROC_PKT_DATA_W_D1:
238			`begin`
239			`if (RXDataValid == 1'b1)`
240			`begin`
241			NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
242			`next_RXByte <= RXDataIn;`
243			`next_RXStreamStatus <= RXStreamStatusIn;`
244			`end`
245			`end`
246			`PROC_PKT_DATA_CHK_D1:
247			`begin`
248			if (RXStreamStatus == `RX_PACKET_STREAM)
249			`begin`
250			NextState_getPkt <= `PROC_PKT_DATA_W_D2;
251			`next_RXByteOldest <= RXByte;`
252			`end`
253			`else`
254			`begin`
255			NextState_getPkt <= `PROC_PKT_DATA_FIN;
256			`end`
257			`end`
258			`PROC_PKT_DATA_W_D2:
259			`begin`
260			`if (RXDataValid == 1'b1)`
261			`begin`
262			NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
263			`next_RXByte <= RXDataIn;`
264			`next_RXStreamStatus <= RXStreamStatusIn;`
265			`end`
266			`end`
267			`PROC_PKT_DATA_FIN:
268			`begin`
269			next_CRCError <= RXByte[`CRC_ERROR_BIT];
270			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
271			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
272			NextState_getPkt <= `PKT_RDY;
273			`end`
274			`PROC_PKT_DATA_CHK_D2:
275			`begin`
276			if (RXStreamStatus == `RX_PACKET_STREAM)
277			`begin`
278			NextState_getPkt <= `PROC_PKT_DATA_W_D3;
279			`next_RXByteOld <= RXByte;`
280			`end`
281			`else`
282			`begin`
283			NextState_getPkt <= `PROC_PKT_DATA_FIN;
284			`end`
285			`end`
286			`PROC_PKT_DATA_W_D3:
287			`begin`
288			`if (RXDataValid == 1'b1)`
289			`begin`
290			NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
291			`next_RXByte <= RXDataIn;`
292			`next_RXStreamStatus <= RXStreamStatusIn;`
293			`end`
294			`end`
295			`PROC_PKT_DATA_CHK_D3:
296			`begin`
297			if (RXStreamStatus == `RX_PACKET_STREAM)
298			`begin`
299			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
300			`end`
301			`else`
302			`begin`
303			NextState_getPkt <= `PROC_PKT_DATA_FIN;
304			`end`
305			`end`
306			`PROC_PKT_DATA_LOOP_CHK_FIFO:
307			`begin`
308			`if (RXFifoFull == 1'b1)`
309			`begin`
310			NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
311			`next_RXOverflow <= 1'b1;`
312			`end`
313			`else`
314			`begin`
315			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
316			`next_RXFifoWEn <= 1'b1;`
317			`next_RXFifoData <= RXByteOldest;`
318			`next_RXByteOldest <= RXByteOld;`
319			`next_RXByteOld <= RXByte;`
320			`end`
321			`end`
322			`PROC_PKT_DATA_LOOP_FIFO_FULL:
323			`begin`
324			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
325			`end`
326			`PROC_PKT_DATA_LOOP_W_D:
327			`begin`
328			`next_RXFifoWEn <= 1'b0;`
329			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
330			`begin`
331			NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
332			`next_RXByte <= RXDataIn;`
333			`next_RXStreamStatus <= RXStreamStatusIn;`
334			`end`
335			`else if (RXDataValid == 1'b1)`
336			`begin`
337			NextState_getPkt <= `PROC_PKT_DATA_FIN;
338			`next_RXByte <= RXDataIn;`
339			`next_RXStreamStatus <= RXStreamStatusIn;`
340			`end`
341			`end`
342			`PROC_PKT_DATA_LOOP_DELAY:
343			`begin`
344			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
345			`end`
346			`endcase`
347			`end`
348
349			`// Current State Logic (sequential)`
350			`always @ (posedge clk)`
351			`begin`
352			`if (rst)`
353			CurrState_getPkt <= `START_GP;
354			`else`
355			`CurrState_getPkt <= NextState_getPkt;`
356			`end`
357
358			`// Registered outputs logic`
359			`always @ (posedge clk)`
360			`begin`
361			`if (rst)`
362			`begin`
363			`RXFifoWEn <= 1'b0;`
364			`RXFifoData <= 8'h00;`
365			`RXPacketRdy <= 1'b0;`
366			`RxPID <= 4'h0;`
367			`RXOverflow <= 1'b0;`
368			`NAKRxed <= 1'b0;`
369			`stallRxed <= 1'b0;`
370			`ACKRxed <= 1'b0;`
371			`RXByte <= 8'h00;`
372			`RXStreamStatus <= 8'h00;`
373			`RXByteOldest <= 8'h00;`
374			`CRCError <= 1'b0;`
375			`bitStuffError <= 1'b0;`
376			`dataSequence <= 1'b0;`
377			`RXByteOld <= 8'h00;`
378			`RXTimeOut <= 1'b0;`
379			`end`
380			`else`
381			`begin`
382			`RXFifoWEn <= next_RXFifoWEn;`
383			`RXFifoData <= next_RXFifoData;`
384			`RXPacketRdy <= next_RXPacketRdy;`
385			`RxPID <= next_RxPID;`
386			`RXOverflow <= next_RXOverflow;`
387			`NAKRxed <= next_NAKRxed;`
388			`stallRxed <= next_stallRxed;`
389			`ACKRxed <= next_ACKRxed;`
390			`RXByte <= next_RXByte;`
391			`RXStreamStatus <= next_RXStreamStatus;`
392			`RXByteOldest <= next_RXByteOldest;`
393			`CRCError <= next_CRCError;`
394			`bitStuffError <= next_bitStuffError;`
395			`dataSequence <= next_dataSequence;`
396			`RXByteOld <= next_RXByteOld;`
397			`RXTimeOut <= next_RXTimeOut;`
398			`end`
399			`end`
400
401	2	sfielding	`endmodule`