URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.v] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log


 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// getpacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
 
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
input   clk;
input   getPacketEn;
input   rst;
input   [7:0]RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0]RXStreamStatusIn;
input   SIERxTimeOut;    // Single cycle pulse
output  [7:0]RXFifoData;
output  RXFifoWEn;
output  RXPacketRdy;
output  [3:0]RxPID;
output  [7:0]RXPktStatus;
 
wire    clk;
wire    getPacketEn;
wire    rst;
wire    [7:0]RXDataIn;
wire    RXDataValid;
reg     [7:0]RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [3:0]RxPID, next_RxPID;
reg     [7:0]RXPktStatus;
wire    [7:0]RXStreamStatusIn;
wire    SIERxTimeOut;
 
// diagram signals declarations
reg ACKRxed, next_ACKRxed;
reg bitStuffError, next_bitStuffError;
reg CRCError, next_CRCError;
reg dataSequence, next_dataSequence;
reg NAKRxed, next_NAKRxed;
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg RXOverflow, next_RXOverflow;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
reg RXTimeOut, next_RXTimeOut;
reg stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: getPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0]CurrState_getPkt, NextState_getPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(CRCError or bitStuffError or
RXOverflow or RXTimeOut or
NAKRxed or stallRxed or
ACKRxed or dataSequence)
begin
RXPktStatus <= {
dataSequence, ACKRxed,
stallRxed, NAKRxed,
RXTimeOut, RXOverflow,
bitStuffError, CRCError};
end
 
 
// Machine: getPkt
 
// NextState logic (combinatorial)
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
begin
  NextState_getPkt <= CurrState_getPkt;
  // Set default values for outputs and signals
  next_RXOverflow <= RXOverflow;
  next_NAKRxed <= NAKRxed;
  next_stallRxed <= stallRxed;
  next_ACKRxed <= ACKRxed;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RXByteOldest <= RXByteOldest;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_dataSequence <= dataSequence;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXTimeOut <= RXTimeOut;
  next_RxPID <= RxPID;
  case (CurrState_getPkt)  // synopsys parallel_case full_case
    `START_GP:
    begin
      NextState_getPkt <= `WAIT_EN;
    end
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_NAKRxed <= 1'b0;
      next_stallRxed <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      if (SIERxTimeOut == 1'b1)
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `CHK_PKT_START:
    begin
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_getPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      if (getPacketEn == 1'b1)
      begin
        NextState_getPkt <= `WAIT_PKT;
      end
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_getPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
    begin
      if (RXByte[1:0] == `HANDSHAKE)
      begin
        NextState_getPkt <= `PROC_PKT_HS;
      end
      else if (RXByte[1:0] == `DATA)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
      end
      else
      begin
        NextState_getPkt <= `PKT_RDY;
      end
    end
    `PROC_PKT_HS:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    end
    `PROC_PKT_DATA_W_D1:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D1:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D2:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_getPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D3:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D3:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
    begin
      if (RXFifoFull == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
    begin
      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_getPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
    begin
      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_getPkt <= `START_GP;
  else
    CurrState_getPkt <= NextState_getPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    RXPacketRdy <= 1'b0;
    RxPID <= 4'h0;
    RXOverflow <= 1'b0;
    NAKRxed <= 1'b0;
    stallRxed <= 1'b0;
    ACKRxed <= 1'b0;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXByteOldest <= 8'h00;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    dataSequence <= 1'b0;
    RXByteOld <= 8'h00;
    RXTimeOut <= 1'b0;
  end
  else
  begin
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    RXPacketRdy <= next_RXPacketRdy;
    RxPID <= next_RxPID;
    RXOverflow <= next_RXOverflow;
    NAKRxed <= next_NAKRxed;
    stallRxed <= next_stallRxed;
    ACKRxed <= next_ACKRxed;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXByteOldest <= next_RXByteOldest;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    dataSequence <= next_dataSequence;
    RXByteOld <= next_RXByteOld;
    RXTimeOut <= next_RXTimeOut;
  end
end
 
endmodule

Browse

Tools

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// getpacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	9	sfielding	`timescale 1ns / 1ps
46
47	5	sfielding	`include "usbSerialInterfaceEngine_h.v"
48			`include "usbConstants_h.v"
49
50			`module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);`
51			`input clk;`
52			`input getPacketEn;`
53			`input rst;`
54			`input [7:0]RXDataIn;`
55			`input RXDataValid;`
56			`input RXFifoFull;`
57			`input [7:0]RXStreamStatusIn;`
58			`input SIERxTimeOut; // Single cycle pulse`
59			`output [7:0]RXFifoData;`
60			`output RXFifoWEn;`
61			`output RXPacketRdy;`
62			`output [3:0]RxPID;`
63			`output [7:0]RXPktStatus;`
64
65			`wire clk;`
66			`wire getPacketEn;`
67			`wire rst;`
68			`wire [7:0]RXDataIn;`
69			`wire RXDataValid;`
70			`reg [7:0]RXFifoData, next_RXFifoData;`
71			`wire RXFifoFull;`
72			`reg RXFifoWEn, next_RXFifoWEn;`
73			`reg RXPacketRdy, next_RXPacketRdy;`
74			`reg [3:0]RxPID, next_RxPID;`
75			`reg [7:0]RXPktStatus;`
76			`wire [7:0]RXStreamStatusIn;`
77			`wire SIERxTimeOut;`
78
79			`// diagram signals declarations`
80			`reg ACKRxed, next_ACKRxed;`
81			`reg bitStuffError, next_bitStuffError;`
82			`reg CRCError, next_CRCError;`
83			`reg dataSequence, next_dataSequence;`
84			`reg NAKRxed, next_NAKRxed;`
85			`reg [7:0]RXByte, next_RXByte;`
86			`reg [7:0]RXByteOld, next_RXByteOld;`
87			`reg [7:0]RXByteOldest, next_RXByteOldest;`
88			`reg RXOverflow, next_RXOverflow;`
89			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
90			`reg RXTimeOut, next_RXTimeOut;`
91			`reg stallRxed, next_stallRxed;`
92
93			`// BINARY ENCODED state machine: getPkt`
94			`// State codes definitions:`
95			`define PROC_PKT_CHK_PID 5'b00000
96			`define PROC_PKT_HS 5'b00001
97			`define PROC_PKT_DATA_W_D1 5'b00010
98			`define PROC_PKT_DATA_CHK_D1 5'b00011
99			`define PROC_PKT_DATA_W_D2 5'b00100
100			`define PROC_PKT_DATA_FIN 5'b00101
101			`define PROC_PKT_DATA_CHK_D2 5'b00110
102			`define PROC_PKT_DATA_W_D3 5'b00111
103			`define PROC_PKT_DATA_CHK_D3 5'b01000
104			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
105			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
106			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
107			`define START_GP 5'b01100
108			`define WAIT_PKT 5'b01101
109			`define CHK_PKT_START 5'b01110
110			`define WAIT_EN 5'b01111
111			`define PKT_RDY 5'b10000
112			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
113
114			`reg [4:0]CurrState_getPkt, NextState_getPkt;`
115
116			`// Diagram actions (continuous assignments allowed only: assign ...)`
117			`always @`
118			`(CRCError or bitStuffError or`
119			`RXOverflow or RXTimeOut or`
120			`NAKRxed or stallRxed or`
121			`ACKRxed or dataSequence)`
122			`begin`
123			`RXPktStatus <= {`
124			`dataSequence, ACKRxed,`
125			`stallRxed, NAKRxed,`
126			`RXTimeOut, RXOverflow,`
127			`bitStuffError, CRCError};`
128			`end`
129
130
131			`// Machine: getPkt`
132
133			`// NextState logic (combinatorial)`
134			`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)`
135			`begin`
136			`NextState_getPkt <= CurrState_getPkt;`
137			`// Set default values for outputs and signals`
138			`next_RXOverflow <= RXOverflow;`
139			`next_NAKRxed <= NAKRxed;`
140			`next_stallRxed <= stallRxed;`
141			`next_ACKRxed <= ACKRxed;`
142			`next_RXByte <= RXByte;`
143			`next_RXStreamStatus <= RXStreamStatus;`
144			`next_RXByteOldest <= RXByteOldest;`
145			`next_CRCError <= CRCError;`
146			`next_bitStuffError <= bitStuffError;`
147			`next_dataSequence <= dataSequence;`
148			`next_RXByteOld <= RXByteOld;`
149			`next_RXFifoWEn <= RXFifoWEn;`
150			`next_RXFifoData <= RXFifoData;`
151			`next_RXPacketRdy <= RXPacketRdy;`
152			`next_RXTimeOut <= RXTimeOut;`
153			`next_RxPID <= RxPID;`
154			`case (CurrState_getPkt) // synopsys parallel_case full_case`
155			`START_GP:
156			`begin`
157			NextState_getPkt <= `WAIT_EN;
158			`end`
159			`WAIT_PKT:
160			`begin`
161			`next_CRCError <= 1'b0;`
162			`next_bitStuffError <= 1'b0;`
163			`next_RXOverflow <= 1'b0;`
164			`next_RXTimeOut <= 1'b0;`
165			`next_NAKRxed <= 1'b0;`
166			`next_stallRxed <= 1'b0;`
167			`next_ACKRxed <= 1'b0;`
168			`next_dataSequence <= 1'b0;`
169			`if (SIERxTimeOut == 1'b1)`
170			`begin`
171			NextState_getPkt <= `PKT_RDY;
172			`next_RXTimeOut <= 1'b1;`
173			`end`
174			`else if (RXDataValid == 1'b1)`
175			`begin`
176			NextState_getPkt <= `CHK_PKT_START;
177			`next_RXByte <= RXDataIn;`
178			`next_RXStreamStatus <= RXStreamStatusIn;`
179			`end`
180			`end`
181			`CHK_PKT_START:
182			`begin`
183			if (RXStreamStatus == `RX_PACKET_START)
184			`begin`
185			NextState_getPkt <= `PROC_PKT_CHK_PID;
186			`next_RxPID <= RXByte[3:0];`
187			`end`
188			`else`
189			`begin`
190			NextState_getPkt <= `PKT_RDY;
191			`next_RXTimeOut <= 1'b1;`
192			`end`
193			`end`
194			`WAIT_EN:
195			`begin`
196			`next_RXPacketRdy <= 1'b0;`
197			`if (getPacketEn == 1'b1)`
198			`begin`
199			NextState_getPkt <= `WAIT_PKT;
200			`end`
201			`end`
202			`PKT_RDY:
203			`begin`
204			`next_RXPacketRdy <= 1'b1;`
205			NextState_getPkt <= `WAIT_EN;
206			`end`
207			`PROC_PKT_CHK_PID:
208			`begin`
209			if (RXByte[1:0] == `HANDSHAKE)
210			`begin`
211			NextState_getPkt <= `PROC_PKT_HS;
212			`end`
213			else if (RXByte[1:0] == `DATA)
214			`begin`
215			NextState_getPkt <= `PROC_PKT_DATA_W_D1;
216			`end`
217			`else`
218			`begin`
219			NextState_getPkt <= `PKT_RDY;
220			`end`
221			`end`
222			`PROC_PKT_HS:
223			`begin`
224			`if (RXDataValid == 1'b1)`
225			`begin`
226			NextState_getPkt <= `PKT_RDY;
227			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
228			next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
229			next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
230			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
231			`end`
232			`end`
233			`PROC_PKT_DATA_W_D1:
234			`begin`
235			`if (RXDataValid == 1'b1)`
236			`begin`
237			NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
238			`next_RXByte <= RXDataIn;`
239			`next_RXStreamStatus <= RXStreamStatusIn;`
240			`end`
241			`end`
242			`PROC_PKT_DATA_CHK_D1:
243			`begin`
244			if (RXStreamStatus == `RX_PACKET_STREAM)
245			`begin`
246			NextState_getPkt <= `PROC_PKT_DATA_W_D2;
247			`next_RXByteOldest <= RXByte;`
248			`end`
249			`else`
250			`begin`
251			NextState_getPkt <= `PROC_PKT_DATA_FIN;
252			`end`
253			`end`
254			`PROC_PKT_DATA_W_D2:
255			`begin`
256			`if (RXDataValid == 1'b1)`
257			`begin`
258			NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
259			`next_RXByte <= RXDataIn;`
260			`next_RXStreamStatus <= RXStreamStatusIn;`
261			`end`
262			`end`
263			`PROC_PKT_DATA_FIN:
264			`begin`
265			next_CRCError <= RXByte[`CRC_ERROR_BIT];
266			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
267			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
268			NextState_getPkt <= `PKT_RDY;
269			`end`
270			`PROC_PKT_DATA_CHK_D2:
271			`begin`
272			if (RXStreamStatus == `RX_PACKET_STREAM)
273			`begin`
274			NextState_getPkt <= `PROC_PKT_DATA_W_D3;
275			`next_RXByteOld <= RXByte;`
276			`end`
277			`else`
278			`begin`
279			NextState_getPkt <= `PROC_PKT_DATA_FIN;
280			`end`
281			`end`
282			`PROC_PKT_DATA_W_D3:
283			`begin`
284			`if (RXDataValid == 1'b1)`
285			`begin`
286			NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
287			`next_RXByte <= RXDataIn;`
288			`next_RXStreamStatus <= RXStreamStatusIn;`
289			`end`
290			`end`
291			`PROC_PKT_DATA_CHK_D3:
292			`begin`
293			if (RXStreamStatus == `RX_PACKET_STREAM)
294			`begin`
295			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
296			`end`
297			`else`
298			`begin`
299			NextState_getPkt <= `PROC_PKT_DATA_FIN;
300			`end`
301			`end`
302			`PROC_PKT_DATA_LOOP_CHK_FIFO:
303			`begin`
304			`if (RXFifoFull == 1'b1)`
305			`begin`
306			NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
307			`next_RXOverflow <= 1'b1;`
308			`end`
309			`else`
310			`begin`
311			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
312			`next_RXFifoWEn <= 1'b1;`
313			`next_RXFifoData <= RXByteOldest;`
314			`next_RXByteOldest <= RXByteOld;`
315			`next_RXByteOld <= RXByte;`
316			`end`
317			`end`
318			`PROC_PKT_DATA_LOOP_FIFO_FULL:
319			`begin`
320			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
321			`end`
322			`PROC_PKT_DATA_LOOP_W_D:
323			`begin`
324			`next_RXFifoWEn <= 1'b0;`
325			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
326			`begin`
327			NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
328			`next_RXByte <= RXDataIn;`
329			`next_RXStreamStatus <= RXStreamStatusIn;`
330			`end`
331			`else if (RXDataValid == 1'b1)`
332			`begin`
333			NextState_getPkt <= `PROC_PKT_DATA_FIN;
334			`next_RXByte <= RXDataIn;`
335			`next_RXStreamStatus <= RXStreamStatusIn;`
336			`end`
337			`end`
338			`PROC_PKT_DATA_LOOP_DELAY:
339			`begin`
340			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
341			`end`
342			`endcase`
343			`end`
344
345			`// Current State Logic (sequential)`
346			`always @ (posedge clk)`
347			`begin`
348			`if (rst)`
349			CurrState_getPkt <= `START_GP;
350			`else`
351			`CurrState_getPkt <= NextState_getPkt;`
352			`end`
353
354			`// Registered outputs logic`
355			`always @ (posedge clk)`
356			`begin`
357			`if (rst)`
358			`begin`
359			`RXFifoWEn <= 1'b0;`
360			`RXFifoData <= 8'h00;`
361			`RXPacketRdy <= 1'b0;`
362			`RxPID <= 4'h0;`
363			`RXOverflow <= 1'b0;`
364			`NAKRxed <= 1'b0;`
365			`stallRxed <= 1'b0;`
366			`ACKRxed <= 1'b0;`
367			`RXByte <= 8'h00;`
368			`RXStreamStatus <= 8'h00;`
369			`RXByteOldest <= 8'h00;`
370			`CRCError <= 1'b0;`
371			`bitStuffError <= 1'b0;`
372			`dataSequence <= 1'b0;`
373			`RXByteOld <= 8'h00;`
374			`RXTimeOut <= 1'b0;`
375			`end`
376			`else`
377			`begin`
378			`RXFifoWEn <= next_RXFifoWEn;`
379			`RXFifoData <= next_RXFifoData;`
380			`RXPacketRdy <= next_RXPacketRdy;`
381			`RxPID <= next_RxPID;`
382			`RXOverflow <= next_RXOverflow;`
383			`NAKRxed <= next_NAKRxed;`
384			`stallRxed <= next_stallRxed;`
385			`ACKRxed <= next_ACKRxed;`
386			`RXByte <= next_RXByte;`
387			`RXStreamStatus <= next_RXStreamStatus;`
388			`RXByteOldest <= next_RXByteOldest;`
389			`CRCError <= next_CRCError;`
390			`bitStuffError <= next_bitStuffError;`
391			`dataSequence <= next_dataSequence;`
392			`RXByteOld <= next_RXByteOld;`
393			`RXTimeOut <= next_RXTimeOut;`
394			`end`
395			`end`
396
397	2	sfielding	`endmodule`