URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log


 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// hostController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbHostControl_h.v"
`include "usbConstants_h.v"
 
 
module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
input   clk;
input   getPacketRdy;
input   isoEn;
input   rst;
input   [7:0]RXStatus;
input   sendPacketArbiterGnt;
input   sendPacketRdy;
input   transReq;
input   [1:0]transType;
output  clearTXReq;
output  getPacketREn;
output  sendPacketArbiterReq;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  transDone;
 
reg     clearTXReq, next_clearTXReq;
wire    clk;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
wire    isoEn;
wire    rst;
wire    [7:0]RXStatus;
wire    sendPacketArbiterGnt;
reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     transDone, next_transDone;
wire    transReq;
wire    [1:0]transType;
 
// BINARY ENCODED state machine: hstCntrl
// State codes definitions:
`define START_HC 6'b000000
`define TX_REQ 6'b000001
`define CHK_TYPE 6'b000010
`define FLAG 6'b000011
`define IN_WAIT_DATA_RXED 6'b000100
`define IN_CHK_FOR_ERROR 6'b000101
`define IN_CLR_SP_WEN2 6'b000110
`define SETUP_CLR_SP_WEN1 6'b000111
`define SETUP_CLR_SP_WEN2 6'b001000
`define FIN 6'b001001
`define WAIT_GNT 6'b001010
`define SETUP_WAIT_PKT_RXED 6'b001011
`define IN_WAIT_IN_SENT 6'b001100
`define OUT0_WAIT_RX_DATA 6'b001101
`define OUT0_WAIT_DATA0_SENT 6'b001110
`define OUT0_WAIT_OUT_SENT 6'b001111
`define SETUP_HC_WAIT_RDY 6'b010000
`define IN_WAIT_SP_RDY1 6'b010001
`define IN_WAIT_SP_RDY2 6'b010010
`define OUT0_WAIT_SP_RDY1 6'b010011
`define SETUP_WAIT_SETUP_SENT 6'b010100
`define SETUP_WAIT_DATA_SENT 6'b010101
`define IN_CLR_SP_WEN1 6'b010110
`define IN_WAIT_ACK_SENT 6'b010111
`define OUT0_CLR_WEN1 6'b011000
`define OUT0_CLR_WEN2 6'b011001
`define OUT1_WAIT_RX_DATA 6'b011010
`define OUT1_WAIT_OUT_SENT 6'b011011
`define OUT1_WAIT_DATA1_SENT 6'b011100
`define OUT1_WAIT_SP_RDY1 6'b011101
`define OUT1_CLR_WEN1 6'b011110
`define OUT1_CLR_WEN2 6'b011111
`define OUT0_CHK_ISO 6'b100000
`define DEL1 6'b100001
`define DEL2 6'b100010
 
reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
 
 
// Machine: hstCntrl
 
// NextState logic (combinatorial)
always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
begin
  NextState_hstCntrl <= CurrState_hstCntrl;
  // Set default values for outputs and signals
  next_transDone <= transDone;
  next_clearTXReq <= clearTXReq;
  next_getPacketREn <= getPacketREn;
  next_sendPacketArbiterReq <= sendPacketArbiterReq;
  next_sendPacketPID <= sendPacketPID;
  next_sendPacketWEn <= sendPacketWEn;
  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
    `START_HC:
    begin
      NextState_hstCntrl <= `TX_REQ;
    end
    `TX_REQ:
    begin
      if (transReq == 1'b1)
      begin
        NextState_hstCntrl <= `WAIT_GNT;
        next_sendPacketArbiterReq <= 1'b1;
      end
    end
    `CHK_TYPE:
    begin
      if (transType == `OUTDATA0_TRANS)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
      end
      else if (transType == `IN_TRANS)
      begin
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
      end
      else if (transType == `SETUP_TRANS)
      begin
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
      end
      else if (transType == `OUTDATA1_TRANS)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
      end
    end
    `FLAG:
    begin
      next_transDone <= 1'b1;
      next_clearTXReq <= 1'b1;
      next_sendPacketArbiterReq <= 1'b0;
      NextState_hstCntrl <= `FIN;
    end
    `FIN:
    begin
      next_clearTXReq <= 1'b0;
      next_transDone <= 1'b0;
      //now wait for 'transReq' to clear
      NextState_hstCntrl <= `DEL1;
    end
    `WAIT_GNT:
    begin
      if (sendPacketArbiterGnt == 1'b1)
      begin
        NextState_hstCntrl <= `CHK_TYPE;
      end
    end
    `DEL1:
    begin
      NextState_hstCntrl <= `DEL2;
    end
    `DEL2:
    begin
      NextState_hstCntrl <= `TX_REQ;
    end
    `SETUP_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
    end
    `SETUP_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
    end
    `SETUP_WAIT_PKT_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `SETUP_HC_WAIT_RDY:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `SETUP;
      end
    end
    `SETUP_WAIT_SETUP_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    end
    `SETUP_WAIT_DATA_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_WAIT_DATA_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
      end
    end
    `IN_CHK_FOR_ERROR:
    begin
      if (isoEn == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
      begin
        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
      end
      else
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `IN_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
    end
    `IN_WAIT_IN_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `IN;
      end
    end
    `IN_WAIT_SP_RDY2:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `IN_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
    end
    `IN_WAIT_ACK_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT0_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT0_WAIT_DATA0_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CHK_ISO;
      end
    end
    `OUT0_WAIT_OUT_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    end
    `OUT0_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    end
    `OUT0_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
    end
    `OUT0_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
    end
    `OUT0_CHK_ISO:
    begin
      if (isoEn == 1'b0)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
      else
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT1_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT1_WAIT_OUT_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `OUT1_WAIT_DATA1_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    end
    `OUT1_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    end
    `OUT1_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
    end
    `OUT1_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_hstCntrl <= `START_HC;
  else
    CurrState_hstCntrl <= NextState_hstCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    transDone <= 1'b0;
    clearTXReq <= 1'b0;
    getPacketREn <= 1'b0;
    sendPacketArbiterReq <= 1'b0;
    sendPacketPID <= 4'b0;
    sendPacketWEn <= 1'b0;
  end
  else
  begin
    transDone <= next_transDone;
    clearTXReq <= next_clearTXReq;
    getPacketREn <= next_getPacketREn;
    sendPacketArbiterReq <= next_sendPacketArbiterReq;
    sendPacketPID <= next_sendPacketPID;
    sendPacketWEn <= next_sendPacketWEn;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// hostController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbHostControl_h.v"
47			`include "usbConstants_h.v"
48
49
50	14	sfielding	`module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);`
51	5	sfielding	`input clk;`
52			`input getPacketRdy;`
53	14	sfielding	`input isoEn;`
54	5	sfielding	`input rst;`
55			`input [7:0]RXStatus;`
56			`input sendPacketArbiterGnt;`
57			`input sendPacketRdy;`
58			`input transReq;`
59			`input [1:0]transType;`
60			`output clearTXReq;`
61			`output getPacketREn;`
62			`output sendPacketArbiterReq;`
63			`output [3:0]sendPacketPID;`
64			`output sendPacketWEn;`
65			`output transDone;`
66
67			`reg clearTXReq, next_clearTXReq;`
68			`wire clk;`
69			`wire getPacketRdy;`
70			`reg getPacketREn, next_getPacketREn;`
71	14	sfielding	`wire isoEn;`
72	5	sfielding	`wire rst;`
73			`wire [7:0]RXStatus;`
74			`wire sendPacketArbiterGnt;`
75			`reg sendPacketArbiterReq, next_sendPacketArbiterReq;`
76			`reg [3:0]sendPacketPID, next_sendPacketPID;`
77			`wire sendPacketRdy;`
78			`reg sendPacketWEn, next_sendPacketWEn;`
79			`reg transDone, next_transDone;`
80			`wire transReq;`
81			`wire [1:0]transType;`
82
83			`// BINARY ENCODED state machine: hstCntrl`
84			`// State codes definitions:`
85	14	sfielding	`define START_HC 6'b000000
86			`define TX_REQ 6'b000001
87			`define CHK_TYPE 6'b000010
88			`define FLAG 6'b000011
89			`define IN_WAIT_DATA_RXED 6'b000100
90			`define IN_CHK_FOR_ERROR 6'b000101
91			`define IN_CLR_SP_WEN2 6'b000110
92			`define SETUP_CLR_SP_WEN1 6'b000111
93			`define SETUP_CLR_SP_WEN2 6'b001000
94			`define FIN 6'b001001
95			`define WAIT_GNT 6'b001010
96			`define SETUP_WAIT_PKT_RXED 6'b001011
97			`define IN_WAIT_IN_SENT 6'b001100
98			`define OUT0_WAIT_RX_DATA 6'b001101
99			`define OUT0_WAIT_DATA0_SENT 6'b001110
100			`define OUT0_WAIT_OUT_SENT 6'b001111
101			`define SETUP_HC_WAIT_RDY 6'b010000
102			`define IN_WAIT_SP_RDY1 6'b010001
103			`define IN_WAIT_SP_RDY2 6'b010010
104			`define OUT0_WAIT_SP_RDY1 6'b010011
105			`define SETUP_WAIT_SETUP_SENT 6'b010100
106			`define SETUP_WAIT_DATA_SENT 6'b010101
107			`define IN_CLR_SP_WEN1 6'b010110
108			`define IN_WAIT_ACK_SENT 6'b010111
109			`define OUT0_CLR_WEN1 6'b011000
110			`define OUT0_CLR_WEN2 6'b011001
111			`define OUT1_WAIT_RX_DATA 6'b011010
112			`define OUT1_WAIT_OUT_SENT 6'b011011
113			`define OUT1_WAIT_DATA1_SENT 6'b011100
114			`define OUT1_WAIT_SP_RDY1 6'b011101
115			`define OUT1_CLR_WEN1 6'b011110
116			`define OUT1_CLR_WEN2 6'b011111
117			`define OUT0_CHK_ISO 6'b100000
118	18	sfielding	`define DEL1 6'b100001
119			`define DEL2 6'b100010
120	5	sfielding
121	14	sfielding	`reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;`
122	5	sfielding
123
124			`// Machine: hstCntrl`
125
126			`// NextState logic (combinatorial)`
127	14	sfielding	`always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)`
128	5	sfielding	`begin`
129			`NextState_hstCntrl <= CurrState_hstCntrl;`
130			`// Set default values for outputs and signals`
131			`next_transDone <= transDone;`
132			`next_clearTXReq <= clearTXReq;`
133			`next_getPacketREn <= getPacketREn;`
134			`next_sendPacketArbiterReq <= sendPacketArbiterReq;`
135			`next_sendPacketPID <= sendPacketPID;`
136			`next_sendPacketWEn <= sendPacketWEn;`
137			`case (CurrState_hstCntrl) // synopsys parallel_case full_case`
138			`START_HC:
139			`begin`
140			NextState_hstCntrl <= `TX_REQ;
141			`end`
142			`TX_REQ:
143			`begin`
144			`if (transReq == 1'b1)`
145			`begin`
146			NextState_hstCntrl <= `WAIT_GNT;
147			`next_sendPacketArbiterReq <= 1'b1;`
148			`end`
149			`end`
150			`CHK_TYPE:
151			`begin`
152	14	sfielding	if (transType == `OUTDATA0_TRANS)
153	5	sfielding	`begin`
154	14	sfielding	NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
155			`end`
156			else if (transType == `IN_TRANS)
157			`begin`
158	9	sfielding	NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
159			`end`
160	14	sfielding	else if (transType == `SETUP_TRANS)
161	9	sfielding	`begin`
162	14	sfielding	NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
163	7	sfielding	`end`
164	9	sfielding	else if (transType == `OUTDATA1_TRANS)
165	7	sfielding	`begin`
166	9	sfielding	NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
167	5	sfielding	`end`
168			`end`
169			`FLAG:
170			`begin`
171			`next_transDone <= 1'b1;`
172			`next_clearTXReq <= 1'b1;`
173			`next_sendPacketArbiterReq <= 1'b0;`
174			NextState_hstCntrl <= `FIN;
175			`end`
176			`FIN:
177			`begin`
178	18	sfielding	`next_clearTXReq <= 1'b0;`
179	5	sfielding	`next_transDone <= 1'b0;`
180	18	sfielding	`//now wait for 'transReq' to clear`
181			NextState_hstCntrl <= `DEL1;
182	5	sfielding	`end`
183			`WAIT_GNT:
184			`begin`
185			`if (sendPacketArbiterGnt == 1'b1)`
186			`begin`
187			NextState_hstCntrl <= `CHK_TYPE;
188			`end`
189			`end`
190	18	sfielding	`DEL1:
191			`begin`
192			NextState_hstCntrl <= `DEL2;
193			`end`
194			`DEL2:
195			`begin`
196			NextState_hstCntrl <= `TX_REQ;
197			`end`
198	5	sfielding	`SETUP_CLR_SP_WEN1:
199			`begin`
200			`next_sendPacketWEn <= 1'b0;`
201			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
202			`end`
203			`SETUP_CLR_SP_WEN2:
204			`begin`
205			`next_sendPacketWEn <= 1'b0;`
206			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
207			`end`
208			`SETUP_WAIT_PKT_RXED:
209			`begin`
210			`next_getPacketREn <= 1'b0;`
211			`if (getPacketRdy == 1'b1)`
212			`begin`
213			NextState_hstCntrl <= `FLAG;
214			`end`
215			`end`
216			`SETUP_HC_WAIT_RDY:
217			`begin`
218			`if (sendPacketRdy == 1'b1)`
219			`begin`
220			NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
221			`next_sendPacketWEn <= 1'b1;`
222			next_sendPacketPID <= `SETUP;
223			`end`
224			`end`
225			`SETUP_WAIT_SETUP_SENT:
226			`begin`
227			`if (sendPacketRdy == 1'b1)`
228			`begin`
229			NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
230			`next_sendPacketWEn <= 1'b1;`
231			next_sendPacketPID <= `DATA0;
232			`end`
233			`end`
234			`SETUP_WAIT_DATA_SENT:
235			`begin`
236			`if (sendPacketRdy == 1'b1)`
237			`begin`
238			NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
239			`next_getPacketREn <= 1'b1;`
240			`end`
241			`end`
242			`IN_WAIT_DATA_RXED:
243			`begin`
244			`next_getPacketREn <= 1'b0;`
245			`if (getPacketRdy == 1'b1)`
246			`begin`
247			NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
248			`end`
249			`end`
250			`IN_CHK_FOR_ERROR:
251			`begin`
252	14	sfielding	`if (isoEn == 1'b1)`
253			`begin`
254			NextState_hstCntrl <= `FLAG;
255			`end`
256			else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
257	5	sfielding	RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
258			RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
259			RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
260			RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
261			RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
262			`begin`
263			NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
264			`end`
265			`else`
266			`begin`
267			NextState_hstCntrl <= `FLAG;
268			`end`
269			`end`
270			`IN_CLR_SP_WEN2:
271			`begin`
272			`next_sendPacketWEn <= 1'b0;`
273			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
274			`end`
275			`IN_WAIT_IN_SENT:
276			`begin`
277			`if (sendPacketRdy == 1'b1)`
278			`begin`
279			NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
280			`next_getPacketREn <= 1'b1;`
281			`end`
282			`end`
283			`IN_WAIT_SP_RDY1:
284			`begin`
285			`if (sendPacketRdy == 1'b1)`
286			`begin`
287			NextState_hstCntrl <= `IN_CLR_SP_WEN1;
288			`next_sendPacketWEn <= 1'b1;`
289			next_sendPacketPID <= `IN;
290			`end`
291			`end`
292			`IN_WAIT_SP_RDY2:
293			`begin`
294			`if (sendPacketRdy == 1'b1)`
295			`begin`
296			NextState_hstCntrl <= `IN_CLR_SP_WEN2;
297			`next_sendPacketWEn <= 1'b1;`
298			next_sendPacketPID <= `ACK;
299			`end`
300			`end`
301			`IN_CLR_SP_WEN1:
302			`begin`
303			`next_sendPacketWEn <= 1'b0;`
304			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
305			`end`
306			`IN_WAIT_ACK_SENT:
307			`begin`
308			`if (sendPacketRdy == 1'b1)`
309			`begin`
310			NextState_hstCntrl <= `FLAG;
311			`end`
312			`end`
313			`OUT0_WAIT_RX_DATA:
314			`begin`
315			`next_getPacketREn <= 1'b0;`
316			`if (getPacketRdy == 1'b1)`
317			`begin`
318			NextState_hstCntrl <= `FLAG;
319			`end`
320			`end`
321			`OUT0_WAIT_DATA0_SENT:
322			`begin`
323			`if (sendPacketRdy == 1'b1)`
324			`begin`
325	14	sfielding	NextState_hstCntrl <= `OUT0_CHK_ISO;
326	5	sfielding	`end`
327			`end`
328			`OUT0_WAIT_OUT_SENT:
329			`begin`
330			`if (sendPacketRdy == 1'b1)`
331			`begin`
332			NextState_hstCntrl <= `OUT0_CLR_WEN2;
333			`next_sendPacketWEn <= 1'b1;`
334			next_sendPacketPID <= `DATA0;
335			`end`
336			`end`
337			`OUT0_WAIT_SP_RDY1:
338			`begin`
339			`if (sendPacketRdy == 1'b1)`
340			`begin`
341			NextState_hstCntrl <= `OUT0_CLR_WEN1;
342			`next_sendPacketWEn <= 1'b1;`
343			next_sendPacketPID <= `OUT;
344			`end`
345			`end`
346			`OUT0_CLR_WEN1:
347			`begin`
348			`next_sendPacketWEn <= 1'b0;`
349			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
350			`end`
351			`OUT0_CLR_WEN2:
352			`begin`
353			`next_sendPacketWEn <= 1'b0;`
354			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
355			`end`
356	14	sfielding	`OUT0_CHK_ISO:
357			`begin`
358			`if (isoEn == 1'b0)`
359			`begin`
360			NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
361			`next_getPacketREn <= 1'b1;`
362			`end`
363			`else`
364			`begin`
365			NextState_hstCntrl <= `FLAG;
366			`end`
367			`end`
368	5	sfielding	`OUT1_WAIT_RX_DATA:
369			`begin`
370			`next_getPacketREn <= 1'b0;`
371			`if (getPacketRdy == 1'b1)`
372			`begin`
373			NextState_hstCntrl <= `FLAG;
374			`end`
375			`end`
376			`OUT1_WAIT_OUT_SENT:
377			`begin`
378			`if (sendPacketRdy == 1'b1)`
379			`begin`
380			NextState_hstCntrl <= `OUT1_CLR_WEN2;
381			`next_sendPacketWEn <= 1'b1;`
382			next_sendPacketPID <= `DATA1;
383			`end`
384			`end`
385			`OUT1_WAIT_DATA1_SENT:
386			`begin`
387			`if (sendPacketRdy == 1'b1)`
388			`begin`
389			NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
390			`next_getPacketREn <= 1'b1;`
391			`end`
392			`end`
393			`OUT1_WAIT_SP_RDY1:
394			`begin`
395			`if (sendPacketRdy == 1'b1)`
396			`begin`
397			NextState_hstCntrl <= `OUT1_CLR_WEN1;
398			`next_sendPacketWEn <= 1'b1;`
399			next_sendPacketPID <= `OUT;
400			`end`
401			`end`
402			`OUT1_CLR_WEN1:
403			`begin`
404			`next_sendPacketWEn <= 1'b0;`
405			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
406			`end`
407			`OUT1_CLR_WEN2:
408			`begin`
409			`next_sendPacketWEn <= 1'b0;`
410			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
411			`end`
412			`endcase`
413			`end`
414
415			`// Current State Logic (sequential)`
416			`always @ (posedge clk)`
417			`begin`
418			`if (rst)`
419			CurrState_hstCntrl <= `START_HC;
420			`else`
421			`CurrState_hstCntrl <= NextState_hstCntrl;`
422			`end`
423
424			`// Registered outputs logic`
425			`always @ (posedge clk)`
426			`begin`
427			`if (rst)`
428			`begin`
429			`transDone <= 1'b0;`
430			`clearTXReq <= 1'b0;`
431			`getPacketREn <= 1'b0;`
432			`sendPacketArbiterReq <= 1'b0;`
433			`sendPacketPID <= 4'b0;`
434			`sendPacketWEn <= 1'b0;`
435			`end`
436			`else`
437			`begin`
438			`transDone <= next_transDone;`
439			`clearTXReq <= next_clearTXReq;`
440			`getPacketREn <= next_getPacketREn;`
441			`sendPacketArbiterReq <= next_sendPacketArbiterReq;`
442			`sendPacketPID <= next_sendPacketPID;`
443			`sendPacketWEn <= next_sendPacketWEn;`
444			`end`
445			`end`
446
447	2	sfielding	`endmodule`

Browse

Tools

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Blame information for rev 18