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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hostcontroller.v
// Generated   : 09/14/04 22:52:06
// From        : c:\projects\USBHostSlave\RTL\hostController\hostcontroller.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbHostControl_h.v"
`include "usbConstants_h.v"
 
 
module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
input   [7:0] RXStatus;
input   clk;
input   getPacketRdy;
input   rst;
input   sendPacketArbiterGnt;
input   sendPacketRdy;
input   transReq;
input   [1:0] transType;
output  clearTXReq;
output  getPacketREn;
output  sendPacketArbiterReq;
output  [3:0] sendPacketPID;
output  sendPacketWEn;
output  transDone;
 
wire    [7:0] RXStatus;
reg     clearTXReq, next_clearTXReq;
wire    clk;
reg     getPacketREn, next_getPacketREn;
wire    getPacketRdy;
wire    rst;
wire    sendPacketArbiterGnt;
reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
reg     [3:0] sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     transDone, next_transDone;
wire    transReq;
wire    [1:0] transType;
 
// BINARY ENCODED state machine: hstCntrl
// State codes definitions:
`define START_HC 5'b00000
`define TX_REQ 5'b00001
`define CHK_TYPE 5'b00010
`define FLAG 5'b00011
`define IN_WAIT_DATA_RXED 5'b00100
`define IN_CHK_FOR_ERROR 5'b00101
`define IN_CLR_SP_WEN2 5'b00110
`define SETUP_CLR_SP_WEN1 5'b00111
`define SETUP_CLR_SP_WEN2 5'b01000
`define FIN 5'b01001
`define WAIT_GNT 5'b01010
`define SETUP_WAIT_PKT_RXED 5'b01011
`define IN_WAIT_IN_SENT 5'b01100
`define OUT0_WAIT_RX_DATA 5'b01101
`define OUT0_WAIT_DATA0_SENT 5'b01110
`define OUT0_WAIT_OUT_SENT 5'b01111
`define SETUP_HC_WAIT_RDY 5'b10000
`define IN_WAIT_SP_RDY1 5'b10001
`define IN_WAIT_SP_RDY2 5'b10010
`define OUT0_WAIT_SP_RDY1 5'b10011
`define SETUP_WAIT_SETUP_SENT 5'b10100
`define SETUP_WAIT_DATA_SENT 5'b10101
`define IN_CLR_SP_WEN1 5'b10110
`define IN_WAIT_ACK_SENT 5'b10111
`define OUT0_CLR_WEN1 5'b11000
`define OUT0_CLR_WEN2 5'b11001
`define OUT1_WAIT_RX_DATA 5'b11010
`define OUT1_WAIT_OUT_SENT 5'b11011
`define OUT1_WAIT_DATA1_SENT 5'b11100
`define OUT1_WAIT_SP_RDY1 5'b11101
`define OUT1_CLR_WEN1 5'b11110
`define OUT1_CLR_WEN2 5'b11111
 
reg [4:0] CurrState_hstCntrl;
reg [4:0] NextState_hstCntrl;
 
 
//--------------------------------------------------------------------
// Machine: hstCntrl
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
begin : hstCntrl_NextState
        NextState_hstCntrl <= CurrState_hstCntrl;
        // Set default values for outputs and signals
        next_sendPacketArbiterReq <= sendPacketArbiterReq;
        next_transDone <= transDone;
        next_clearTXReq <= clearTXReq;
        next_sendPacketWEn <= sendPacketWEn;
        next_getPacketREn <= getPacketREn;
        next_sendPacketPID <= sendPacketPID;
        case (CurrState_hstCntrl) // synopsys parallel_case full_case
                `START_HC:
                        NextState_hstCntrl <= `TX_REQ;
                `TX_REQ:
                        if (transReq == 1'b1)
                        begin
                                NextState_hstCntrl <= `WAIT_GNT;
                                next_sendPacketArbiterReq <= 1'b1;
                        end
                `CHK_TYPE:
                        if (transType == `IN_TRANS)
                                NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
                        else if (transType == `OUTDATA0_TRANS)
                                NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
                        else if (transType == `OUTDATA1_TRANS)
                                NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
                        else if (transType == `SETUP_TRANS)
                                NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
                `FLAG:
                begin
                        next_transDone <= 1'b1;
                        next_clearTXReq <= 1'b1;
                        next_sendPacketArbiterReq <= 1'b0;
                        NextState_hstCntrl <= `FIN;
                end
                `FIN:
                begin
                        next_transDone <= 1'b0;
                        next_clearTXReq <= 1'b0;
                        NextState_hstCntrl <= `TX_REQ;
                end
                `WAIT_GNT:
                        if (sendPacketArbiterGnt == 1'b1)
                                NextState_hstCntrl <= `CHK_TYPE;
                `SETUP_CLR_SP_WEN1:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
                end
                `SETUP_CLR_SP_WEN2:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
                end
                `SETUP_WAIT_PKT_RXED:
                begin
                        next_getPacketREn <= 1'b0;
                        if (getPacketRdy == 1'b1)
                                NextState_hstCntrl <= `FLAG;
                end
                `SETUP_HC_WAIT_RDY:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `SETUP;
                        end
                `SETUP_WAIT_SETUP_SENT:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `DATA0;
                        end
                `SETUP_WAIT_DATA_SENT:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
                                next_getPacketREn <= 1'b1;
                        end
                `IN_WAIT_DATA_RXED:
                begin
                        next_getPacketREn <= 1'b0;
                        if (getPacketRdy == 1'b1)
                                NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
                end
                `IN_CHK_FOR_ERROR:
                        if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
                                RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
                                RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
                                RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
                                RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
                                RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
                                NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
                        else
                                NextState_hstCntrl <= `FLAG;
                `IN_CLR_SP_WEN2:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
                end
                `IN_WAIT_IN_SENT:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
                                next_getPacketREn <= 1'b1;
                        end
                `IN_WAIT_SP_RDY1:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `IN_CLR_SP_WEN1;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `IN;
                        end
                `IN_WAIT_SP_RDY2:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `IN_CLR_SP_WEN2;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `ACK;
                        end
                `IN_CLR_SP_WEN1:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `IN_WAIT_IN_SENT;
                end
                `IN_WAIT_ACK_SENT:
                        if (sendPacketRdy == 1'b1)
                                NextState_hstCntrl <= `FLAG;
                `OUT0_WAIT_RX_DATA:
                begin
                        next_getPacketREn <= 1'b0;
                        if (getPacketRdy == 1'b1)
                                NextState_hstCntrl <= `FLAG;
                end
                `OUT0_WAIT_DATA0_SENT:
                begin
                        next_sendPacketWEn <= 1'b0;
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
                                next_getPacketREn <= 1'b1;
                        end
                end
                `OUT0_WAIT_OUT_SENT:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `OUT0_CLR_WEN2;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `DATA0;
                        end
                `OUT0_WAIT_SP_RDY1:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `OUT0_CLR_WEN1;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `OUT;
                        end
                `OUT0_CLR_WEN1:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
                end
                `OUT0_CLR_WEN2:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
                end
                `OUT1_WAIT_RX_DATA:
                begin
                        next_getPacketREn <= 1'b0;
                        if (getPacketRdy == 1'b1)
                                NextState_hstCntrl <= `FLAG;
                end
                `OUT1_WAIT_OUT_SENT:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `OUT1_CLR_WEN2;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `DATA1;
                        end
                `OUT1_WAIT_DATA1_SENT:
                begin
                        next_sendPacketWEn <= 1'b0;
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
                                next_getPacketREn <= 1'b1;
                        end
                end
                `OUT1_WAIT_SP_RDY1:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_hstCntrl <= `OUT1_CLR_WEN1;
                                next_sendPacketWEn <= 1'b1;
                                next_sendPacketPID <= `OUT;
                        end
                `OUT1_CLR_WEN1:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
                end
                `OUT1_CLR_WEN2:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : hstCntrl_CurrentState
        if (rst)
                CurrState_hstCntrl <= `START_HC;
        else
                CurrState_hstCntrl <= NextState_hstCntrl;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : hstCntrl_RegOutput
        if (rst)
        begin
                transDone <= 1'b0;
                clearTXReq <= 1'b0;
                getPacketREn <= 1'b0;
                sendPacketArbiterReq <= 1'b0;
                sendPacketWEn <= 1'b0;
                sendPacketPID <= 4'b0;
        end
        else
        begin
                transDone <= next_transDone;
                clearTXReq <= next_clearTXReq;
                getPacketREn <= next_getPacketREn;
                sendPacketArbiterReq <= next_sendPacketArbiterReq;
                sendPacketWEn <= next_sendPacketWEn;
                sendPacketPID <= next_sendPacketPID;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author :`
6			`// Company :`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hostcontroller.v`
11			`// Generated : 09/14/04 22:52:06`
12			`// From : c:\projects\USBHostSlave\RTL\hostController\hostcontroller.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbHostControl_h.v"
23			`include "usbConstants_h.v"
24
25
26			`module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);`
27			`input [7:0] RXStatus;`
28			`input clk;`
29			`input getPacketRdy;`
30			`input rst;`
31			`input sendPacketArbiterGnt;`
32			`input sendPacketRdy;`
33			`input transReq;`
34			`input [1:0] transType;`
35			`output clearTXReq;`
36			`output getPacketREn;`
37			`output sendPacketArbiterReq;`
38			`output [3:0] sendPacketPID;`
39			`output sendPacketWEn;`
40			`output transDone;`
41
42			`wire [7:0] RXStatus;`
43			`reg clearTXReq, next_clearTXReq;`
44			`wire clk;`
45			`reg getPacketREn, next_getPacketREn;`
46			`wire getPacketRdy;`
47			`wire rst;`
48			`wire sendPacketArbiterGnt;`
49			`reg sendPacketArbiterReq, next_sendPacketArbiterReq;`
50			`reg [3:0] sendPacketPID, next_sendPacketPID;`
51			`wire sendPacketRdy;`
52			`reg sendPacketWEn, next_sendPacketWEn;`
53			`reg transDone, next_transDone;`
54			`wire transReq;`
55			`wire [1:0] transType;`
56
57			`// BINARY ENCODED state machine: hstCntrl`
58			`// State codes definitions:`
59			`define START_HC 5'b00000
60			`define TX_REQ 5'b00001
61			`define CHK_TYPE 5'b00010
62			`define FLAG 5'b00011
63			`define IN_WAIT_DATA_RXED 5'b00100
64			`define IN_CHK_FOR_ERROR 5'b00101
65			`define IN_CLR_SP_WEN2 5'b00110
66			`define SETUP_CLR_SP_WEN1 5'b00111
67			`define SETUP_CLR_SP_WEN2 5'b01000
68			`define FIN 5'b01001
69			`define WAIT_GNT 5'b01010
70			`define SETUP_WAIT_PKT_RXED 5'b01011
71			`define IN_WAIT_IN_SENT 5'b01100
72			`define OUT0_WAIT_RX_DATA 5'b01101
73			`define OUT0_WAIT_DATA0_SENT 5'b01110
74			`define OUT0_WAIT_OUT_SENT 5'b01111
75			`define SETUP_HC_WAIT_RDY 5'b10000
76			`define IN_WAIT_SP_RDY1 5'b10001
77			`define IN_WAIT_SP_RDY2 5'b10010
78			`define OUT0_WAIT_SP_RDY1 5'b10011
79			`define SETUP_WAIT_SETUP_SENT 5'b10100
80			`define SETUP_WAIT_DATA_SENT 5'b10101
81			`define IN_CLR_SP_WEN1 5'b10110
82			`define IN_WAIT_ACK_SENT 5'b10111
83			`define OUT0_CLR_WEN1 5'b11000
84			`define OUT0_CLR_WEN2 5'b11001
85			`define OUT1_WAIT_RX_DATA 5'b11010
86			`define OUT1_WAIT_OUT_SENT 5'b11011
87			`define OUT1_WAIT_DATA1_SENT 5'b11100
88			`define OUT1_WAIT_SP_RDY1 5'b11101
89			`define OUT1_CLR_WEN1 5'b11110
90			`define OUT1_CLR_WEN2 5'b11111
91
92			`reg [4:0] CurrState_hstCntrl;`
93			`reg [4:0] NextState_hstCntrl;`
94
95
96			`//--------------------------------------------------------------------`
97			`// Machine: hstCntrl`
98			`//--------------------------------------------------------------------`
99			`//----------------------------------`
100			`// NextState logic (combinatorial)`
101			`//----------------------------------`
102			`always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)`
103			`begin : hstCntrl_NextState`
104			`NextState_hstCntrl <= CurrState_hstCntrl;`
105			`// Set default values for outputs and signals`
106			`next_sendPacketArbiterReq <= sendPacketArbiterReq;`
107			`next_transDone <= transDone;`
108			`next_clearTXReq <= clearTXReq;`
109			`next_sendPacketWEn <= sendPacketWEn;`
110			`next_getPacketREn <= getPacketREn;`
111			`next_sendPacketPID <= sendPacketPID;`
112			`case (CurrState_hstCntrl) // synopsys parallel_case full_case`
113			`START_HC:
114			NextState_hstCntrl <= `TX_REQ;
115			`TX_REQ:
116			`if (transReq == 1'b1)`
117			`begin`
118			NextState_hstCntrl <= `WAIT_GNT;
119			`next_sendPacketArbiterReq <= 1'b1;`
120			`end`
121			`CHK_TYPE:
122			if (transType == `IN_TRANS)
123			NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
124			else if (transType == `OUTDATA0_TRANS)
125			NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
126			else if (transType == `OUTDATA1_TRANS)
127			NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
128			else if (transType == `SETUP_TRANS)
129			NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
130			`FLAG:
131			`begin`
132			`next_transDone <= 1'b1;`
133			`next_clearTXReq <= 1'b1;`
134			`next_sendPacketArbiterReq <= 1'b0;`
135			NextState_hstCntrl <= `FIN;
136			`end`
137			`FIN:
138			`begin`
139			`next_transDone <= 1'b0;`
140			`next_clearTXReq <= 1'b0;`
141			NextState_hstCntrl <= `TX_REQ;
142			`end`
143			`WAIT_GNT:
144			`if (sendPacketArbiterGnt == 1'b1)`
145			NextState_hstCntrl <= `CHK_TYPE;
146			`SETUP_CLR_SP_WEN1:
147			`begin`
148			`next_sendPacketWEn <= 1'b0;`
149			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
150			`end`
151			`SETUP_CLR_SP_WEN2:
152			`begin`
153			`next_sendPacketWEn <= 1'b0;`
154			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
155			`end`
156			`SETUP_WAIT_PKT_RXED:
157			`begin`
158			`next_getPacketREn <= 1'b0;`
159			`if (getPacketRdy == 1'b1)`
160			NextState_hstCntrl <= `FLAG;
161			`end`
162			`SETUP_HC_WAIT_RDY:
163			`if (sendPacketRdy == 1'b1)`
164			`begin`
165			NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
166			`next_sendPacketWEn <= 1'b1;`
167			next_sendPacketPID <= `SETUP;
168			`end`
169			`SETUP_WAIT_SETUP_SENT:
170			`if (sendPacketRdy == 1'b1)`
171			`begin`
172			NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
173			`next_sendPacketWEn <= 1'b1;`
174			next_sendPacketPID <= `DATA0;
175			`end`
176			`SETUP_WAIT_DATA_SENT:
177			`if (sendPacketRdy == 1'b1)`
178			`begin`
179			NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
180			`next_getPacketREn <= 1'b1;`
181			`end`
182			`IN_WAIT_DATA_RXED:
183			`begin`
184			`next_getPacketREn <= 1'b0;`
185			`if (getPacketRdy == 1'b1)`
186			NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
187			`end`
188			`IN_CHK_FOR_ERROR:
189			if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
190			RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
191			RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
192			RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
193			RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
194			RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
195			NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
196			`else`
197			NextState_hstCntrl <= `FLAG;
198			`IN_CLR_SP_WEN2:
199			`begin`
200			`next_sendPacketWEn <= 1'b0;`
201			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
202			`end`
203			`IN_WAIT_IN_SENT:
204			`if (sendPacketRdy == 1'b1)`
205			`begin`
206			NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
207			`next_getPacketREn <= 1'b1;`
208			`end`
209			`IN_WAIT_SP_RDY1:
210			`if (sendPacketRdy == 1'b1)`
211			`begin`
212			NextState_hstCntrl <= `IN_CLR_SP_WEN1;
213			`next_sendPacketWEn <= 1'b1;`
214			next_sendPacketPID <= `IN;
215			`end`
216			`IN_WAIT_SP_RDY2:
217			`if (sendPacketRdy == 1'b1)`
218			`begin`
219			NextState_hstCntrl <= `IN_CLR_SP_WEN2;
220			`next_sendPacketWEn <= 1'b1;`
221			next_sendPacketPID <= `ACK;
222			`end`
223			`IN_CLR_SP_WEN1:
224			`begin`
225			`next_sendPacketWEn <= 1'b0;`
226			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
227			`end`
228			`IN_WAIT_ACK_SENT:
229			`if (sendPacketRdy == 1'b1)`
230			NextState_hstCntrl <= `FLAG;
231			`OUT0_WAIT_RX_DATA:
232			`begin`
233			`next_getPacketREn <= 1'b0;`
234			`if (getPacketRdy == 1'b1)`
235			NextState_hstCntrl <= `FLAG;
236			`end`
237			`OUT0_WAIT_DATA0_SENT:
238			`begin`
239			`next_sendPacketWEn <= 1'b0;`
240			`if (sendPacketRdy == 1'b1)`
241			`begin`
242			NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
243			`next_getPacketREn <= 1'b1;`
244			`end`
245			`end`
246			`OUT0_WAIT_OUT_SENT:
247			`if (sendPacketRdy == 1'b1)`
248			`begin`
249			NextState_hstCntrl <= `OUT0_CLR_WEN2;
250			`next_sendPacketWEn <= 1'b1;`
251			next_sendPacketPID <= `DATA0;
252			`end`
253			`OUT0_WAIT_SP_RDY1:
254			`if (sendPacketRdy == 1'b1)`
255			`begin`
256			NextState_hstCntrl <= `OUT0_CLR_WEN1;
257			`next_sendPacketWEn <= 1'b1;`
258			next_sendPacketPID <= `OUT;
259			`end`
260			`OUT0_CLR_WEN1:
261			`begin`
262			`next_sendPacketWEn <= 1'b0;`
263			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
264			`end`
265			`OUT0_CLR_WEN2:
266			`begin`
267			`next_sendPacketWEn <= 1'b0;`
268			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
269			`end`
270			`OUT1_WAIT_RX_DATA:
271			`begin`
272			`next_getPacketREn <= 1'b0;`
273			`if (getPacketRdy == 1'b1)`
274			NextState_hstCntrl <= `FLAG;
275			`end`
276			`OUT1_WAIT_OUT_SENT:
277			`if (sendPacketRdy == 1'b1)`
278			`begin`
279			NextState_hstCntrl <= `OUT1_CLR_WEN2;
280			`next_sendPacketWEn <= 1'b1;`
281			next_sendPacketPID <= `DATA1;
282			`end`
283			`OUT1_WAIT_DATA1_SENT:
284			`begin`
285			`next_sendPacketWEn <= 1'b0;`
286			`if (sendPacketRdy == 1'b1)`
287			`begin`
288			NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
289			`next_getPacketREn <= 1'b1;`
290			`end`
291			`end`
292			`OUT1_WAIT_SP_RDY1:
293			`if (sendPacketRdy == 1'b1)`
294			`begin`
295			NextState_hstCntrl <= `OUT1_CLR_WEN1;
296			`next_sendPacketWEn <= 1'b1;`
297			next_sendPacketPID <= `OUT;
298			`end`
299			`OUT1_CLR_WEN1:
300			`begin`
301			`next_sendPacketWEn <= 1'b0;`
302			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
303			`end`
304			`OUT1_CLR_WEN2:
305			`begin`
306			`next_sendPacketWEn <= 1'b0;`
307			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
308			`end`
309			`endcase`
310			`end`
311
312			`//----------------------------------`
313			`// Current State Logic (sequential)`
314			`//----------------------------------`
315			`always @ (posedge clk)`
316			`begin : hstCntrl_CurrentState`
317			`if (rst)`
318			CurrState_hstCntrl <= `START_HC;
319			`else`
320			`CurrState_hstCntrl <= NextState_hstCntrl;`
321			`end`
322
323			`//----------------------------------`
324			`// Registered outputs logic`
325			`//----------------------------------`
326			`always @ (posedge clk)`
327			`begin : hstCntrl_RegOutput`
328			`if (rst)`
329			`begin`
330			`transDone <= 1'b0;`
331			`clearTXReq <= 1'b0;`
332			`getPacketREn <= 1'b0;`
333			`sendPacketArbiterReq <= 1'b0;`
334			`sendPacketWEn <= 1'b0;`
335			`sendPacketPID <= 4'b0;`
336			`end`
337			`else`
338			`begin`
339			`transDone <= next_transDone;`
340			`clearTXReq <= next_clearTXReq;`
341			`getPacketREn <= next_getPacketREn;`
342			`sendPacketArbiterReq <= next_sendPacketArbiterReq;`
343			`sendPacketWEn <= next_sendPacketWEn;`
344			`sendPacketPID <= next_sendPacketPID;`
345			`end`
346			`end`
347
348			`endmodule`