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// File        : ../RTL/hostController/hostcontroller.v
// Generated   : 10/15/06 20:31:18
// From        : ../RTL/hostController/hostcontroller.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// hostController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostControl_h.v"
`include "usbConstants_h.v"
 
 
module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
input   [7:0] RXStatus;
input   clk;
input   getPacketRdy;
input   isoEn;
input   rst;
input   sendPacketArbiterGnt;
input   sendPacketRdy;
input   transReq;
input   [1:0] transType;
output  clearTXReq;
output  getPacketREn;
output  sendPacketArbiterReq;
output  [3:0] sendPacketPID;
output  sendPacketWEn;
output  transDone;
 
wire    [7:0] RXStatus;
reg     clearTXReq, next_clearTXReq;
wire    clk;
reg     getPacketREn, next_getPacketREn;
wire    getPacketRdy;
wire    isoEn;
wire    rst;
wire    sendPacketArbiterGnt;
reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
reg     [3:0] sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     transDone, next_transDone;
wire    transReq;
wire    [1:0] transType;
 
// BINARY ENCODED state machine: hstCntrl
// State codes definitions:
`define START_HC 6'b000000
`define TX_REQ 6'b000001
`define CHK_TYPE 6'b000010
`define FLAG 6'b000011
`define IN_WAIT_DATA_RXED 6'b000100
`define IN_CHK_FOR_ERROR 6'b000101
`define IN_CLR_SP_WEN2 6'b000110
`define SETUP_CLR_SP_WEN1 6'b000111
`define SETUP_CLR_SP_WEN2 6'b001000
`define FIN 6'b001001
`define WAIT_GNT 6'b001010
`define SETUP_WAIT_PKT_RXED 6'b001011
`define IN_WAIT_IN_SENT 6'b001100
`define OUT0_WAIT_RX_DATA 6'b001101
`define OUT0_WAIT_DATA0_SENT 6'b001110
`define OUT0_WAIT_OUT_SENT 6'b001111
`define SETUP_HC_WAIT_RDY 6'b010000
`define IN_WAIT_SP_RDY1 6'b010001
`define IN_WAIT_SP_RDY2 6'b010010
`define OUT0_WAIT_SP_RDY1 6'b010011
`define SETUP_WAIT_SETUP_SENT 6'b010100
`define SETUP_WAIT_DATA_SENT 6'b010101
`define IN_CLR_SP_WEN1 6'b010110
`define IN_WAIT_ACK_SENT 6'b010111
`define OUT0_CLR_WEN1 6'b011000
`define OUT0_CLR_WEN2 6'b011001
`define OUT1_WAIT_RX_DATA 6'b011010
`define OUT1_WAIT_OUT_SENT 6'b011011
`define OUT1_WAIT_DATA1_SENT 6'b011100
`define OUT1_WAIT_SP_RDY1 6'b011101
`define OUT1_CLR_WEN1 6'b011110
`define OUT1_CLR_WEN2 6'b011111
`define OUT0_CHK_ISO 6'b100000
`define DEL1 6'b100001
`define DEL2 6'b100010
 
reg [5:0] CurrState_hstCntrl;
reg [5:0] NextState_hstCntrl;
 
 
//--------------------------------------------------------------------
// Machine: hstCntrl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
begin : hstCntrl_NextState
  NextState_hstCntrl <= CurrState_hstCntrl;
  // Set default values for outputs and signals
  next_sendPacketArbiterReq <= sendPacketArbiterReq;
  next_transDone <= transDone;
  next_clearTXReq <= clearTXReq;
  next_sendPacketWEn <= sendPacketWEn;
  next_getPacketREn <= getPacketREn;
  next_sendPacketPID <= sendPacketPID;
  case (CurrState_hstCntrl)
    `START_HC:
      NextState_hstCntrl <= `TX_REQ;
    `TX_REQ:
      if (transReq == 1'b1)
      begin
        NextState_hstCntrl <= `WAIT_GNT;
        next_sendPacketArbiterReq <= 1'b1;
      end
    `CHK_TYPE:
      if (transType == `IN_TRANS)
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
      else if (transType == `OUTDATA0_TRANS)
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
      else if (transType == `OUTDATA1_TRANS)
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
      else if (transType == `SETUP_TRANS)
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
    `FLAG:
    begin
      next_transDone <= 1'b1;
      next_clearTXReq <= 1'b1;
      next_sendPacketArbiterReq <= 1'b0;
      NextState_hstCntrl <= `FIN;
    end
    `FIN:
    begin
      next_clearTXReq <= 1'b0;
      next_transDone <= 1'b0;
      //now wait for 'transReq' to clear
      NextState_hstCntrl <= `DEL1;
    end
    `WAIT_GNT:
      if (sendPacketArbiterGnt == 1'b1)
        NextState_hstCntrl <= `CHK_TYPE;
    `DEL1:
      NextState_hstCntrl <= `DEL2;
    `DEL2:
      NextState_hstCntrl <= `TX_REQ;
    `SETUP_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
    end
    `SETUP_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
    end
    `SETUP_WAIT_PKT_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    end
    `SETUP_HC_WAIT_RDY:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `SETUP;
      end
    `SETUP_WAIT_SETUP_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    `SETUP_WAIT_DATA_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
        next_getPacketREn <= 1'b1;
      end
    `IN_WAIT_DATA_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
    end
    `IN_CHK_FOR_ERROR:
      if (isoEn == 1'b1)
        NextState_hstCntrl <= `FLAG;
      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
      else
        NextState_hstCntrl <= `FLAG;
    `IN_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
    end
    `IN_WAIT_IN_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
        next_getPacketREn <= 1'b1;
      end
    `IN_WAIT_SP_RDY1:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `IN;
      end
    `IN_WAIT_SP_RDY2:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    `IN_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
    end
    `IN_WAIT_ACK_SENT:
      if (sendPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    `OUT0_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    end
    `OUT0_WAIT_DATA0_SENT:
      if (sendPacketRdy == 1'b1)
        NextState_hstCntrl <= `OUT0_CHK_ISO;
    `OUT0_WAIT_OUT_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    `OUT0_WAIT_SP_RDY1:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    `OUT0_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
    end
    `OUT0_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
    end
    `OUT0_CHK_ISO:
      if (isoEn == 1'b0)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
      else
        NextState_hstCntrl <= `FLAG;
    `OUT1_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    end
    `OUT1_WAIT_OUT_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    `OUT1_WAIT_DATA1_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    `OUT1_WAIT_SP_RDY1:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    `OUT1_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
    end
    `OUT1_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : hstCntrl_CurrentState
  if (rst)
    CurrState_hstCntrl <= `START_HC;
  else
    CurrState_hstCntrl <= NextState_hstCntrl;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : hstCntrl_RegOutput
  if (rst)
  begin
    transDone <= 1'b0;
    clearTXReq <= 1'b0;
    getPacketREn <= 1'b0;
    sendPacketArbiterReq <= 1'b0;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
  end
  else
  begin
    transDone <= next_transDone;
    clearTXReq <= next_clearTXReq;
    getPacketREn <= next_getPacketREn;
    sendPacketArbiterReq <= next_sendPacketArbiterReq;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2	22	sfielding	`// File : ../RTL/hostController/hostcontroller.v`
3	34	sfielding	`// Generated : 10/15/06 20:31:18`
4	22	sfielding	`// From : ../RTL/hostController/hostcontroller.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7	5	sfielding	`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// hostController`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50	22	sfielding	`include "timescale.v"
51	5	sfielding	`include "usbHostControl_h.v"
52			`include "usbConstants_h.v"
53
54
55	22	sfielding	`module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);`
56			`input [7:0] RXStatus;`
57	5	sfielding	`input clk;`
58			`input getPacketRdy;`
59	14	sfielding	`input isoEn;`
60	5	sfielding	`input rst;`
61			`input sendPacketArbiterGnt;`
62			`input sendPacketRdy;`
63			`input transReq;`
64	22	sfielding	`input [1:0] transType;`
65	5	sfielding	`output clearTXReq;`
66			`output getPacketREn;`
67			`output sendPacketArbiterReq;`
68	22	sfielding	`output [3:0] sendPacketPID;`
69	5	sfielding	`output sendPacketWEn;`
70			`output transDone;`
71
72	22	sfielding	`wire [7:0] RXStatus;`
73	5	sfielding	`reg clearTXReq, next_clearTXReq;`
74			`wire clk;`
75	22	sfielding	`reg getPacketREn, next_getPacketREn;`
76	5	sfielding	`wire getPacketRdy;`
77	14	sfielding	`wire isoEn;`
78	5	sfielding	`wire rst;`
79			`wire sendPacketArbiterGnt;`
80			`reg sendPacketArbiterReq, next_sendPacketArbiterReq;`
81	22	sfielding	`reg [3:0] sendPacketPID, next_sendPacketPID;`
82	5	sfielding	`wire sendPacketRdy;`
83			`reg sendPacketWEn, next_sendPacketWEn;`
84			`reg transDone, next_transDone;`
85			`wire transReq;`
86	22	sfielding	`wire [1:0] transType;`
87	5	sfielding
88			`// BINARY ENCODED state machine: hstCntrl`
89			`// State codes definitions:`
90	14	sfielding	`define START_HC 6'b000000
91			`define TX_REQ 6'b000001
92			`define CHK_TYPE 6'b000010
93			`define FLAG 6'b000011
94			`define IN_WAIT_DATA_RXED 6'b000100
95			`define IN_CHK_FOR_ERROR 6'b000101
96			`define IN_CLR_SP_WEN2 6'b000110
97			`define SETUP_CLR_SP_WEN1 6'b000111
98			`define SETUP_CLR_SP_WEN2 6'b001000
99			`define FIN 6'b001001
100			`define WAIT_GNT 6'b001010
101			`define SETUP_WAIT_PKT_RXED 6'b001011
102			`define IN_WAIT_IN_SENT 6'b001100
103			`define OUT0_WAIT_RX_DATA 6'b001101
104			`define OUT0_WAIT_DATA0_SENT 6'b001110
105			`define OUT0_WAIT_OUT_SENT 6'b001111
106			`define SETUP_HC_WAIT_RDY 6'b010000
107			`define IN_WAIT_SP_RDY1 6'b010001
108			`define IN_WAIT_SP_RDY2 6'b010010
109			`define OUT0_WAIT_SP_RDY1 6'b010011
110			`define SETUP_WAIT_SETUP_SENT 6'b010100
111			`define SETUP_WAIT_DATA_SENT 6'b010101
112			`define IN_CLR_SP_WEN1 6'b010110
113			`define IN_WAIT_ACK_SENT 6'b010111
114			`define OUT0_CLR_WEN1 6'b011000
115			`define OUT0_CLR_WEN2 6'b011001
116			`define OUT1_WAIT_RX_DATA 6'b011010
117			`define OUT1_WAIT_OUT_SENT 6'b011011
118			`define OUT1_WAIT_DATA1_SENT 6'b011100
119			`define OUT1_WAIT_SP_RDY1 6'b011101
120			`define OUT1_CLR_WEN1 6'b011110
121			`define OUT1_CLR_WEN2 6'b011111
122			`define OUT0_CHK_ISO 6'b100000
123	18	sfielding	`define DEL1 6'b100001
124			`define DEL2 6'b100010
125	5	sfielding
126	22	sfielding	`reg [5:0] CurrState_hstCntrl;`
127			`reg [5:0] NextState_hstCntrl;`
128	5	sfielding
129
130	22	sfielding	`//--------------------------------------------------------------------`
131	5	sfielding	`// Machine: hstCntrl`
132	22	sfielding	`//--------------------------------------------------------------------`
133			`//----------------------------------`
134			`// Next State Logic (combinatorial)`
135			`//----------------------------------`
136			`always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)`
137			`begin : hstCntrl_NextState`
138	34	sfielding	`NextState_hstCntrl <= CurrState_hstCntrl;`
139			`// Set default values for outputs and signals`
140			`next_sendPacketArbiterReq <= sendPacketArbiterReq;`
141			`next_transDone <= transDone;`
142			`next_clearTXReq <= clearTXReq;`
143			`next_sendPacketWEn <= sendPacketWEn;`
144			`next_getPacketREn <= getPacketREn;`
145			`next_sendPacketPID <= sendPacketPID;`
146			`case (CurrState_hstCntrl)`
147			`START_HC:
148			NextState_hstCntrl <= `TX_REQ;
149			`TX_REQ:
150			`if (transReq == 1'b1)`
151			`begin`
152			NextState_hstCntrl <= `WAIT_GNT;
153			`next_sendPacketArbiterReq <= 1'b1;`
154			`end`
155			`CHK_TYPE:
156			if (transType == `IN_TRANS)
157			NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
158			else if (transType == `OUTDATA0_TRANS)
159			NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
160			else if (transType == `OUTDATA1_TRANS)
161			NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
162			else if (transType == `SETUP_TRANS)
163			NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
164			`FLAG:
165			`begin`
166			`next_transDone <= 1'b1;`
167			`next_clearTXReq <= 1'b1;`
168			`next_sendPacketArbiterReq <= 1'b0;`
169			NextState_hstCntrl <= `FIN;
170			`end`
171			`FIN:
172			`begin`
173			`next_clearTXReq <= 1'b0;`
174			`next_transDone <= 1'b0;`
175			`//now wait for 'transReq' to clear`
176			NextState_hstCntrl <= `DEL1;
177			`end`
178			`WAIT_GNT:
179			`if (sendPacketArbiterGnt == 1'b1)`
180			NextState_hstCntrl <= `CHK_TYPE;
181			`DEL1:
182			NextState_hstCntrl <= `DEL2;
183			`DEL2:
184			NextState_hstCntrl <= `TX_REQ;
185			`SETUP_CLR_SP_WEN1:
186			`begin`
187			`next_sendPacketWEn <= 1'b0;`
188			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
189			`end`
190			`SETUP_CLR_SP_WEN2:
191			`begin`
192			`next_sendPacketWEn <= 1'b0;`
193			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
194			`end`
195			`SETUP_WAIT_PKT_RXED:
196			`begin`
197			`next_getPacketREn <= 1'b0;`
198			`if (getPacketRdy == 1'b1)`
199			NextState_hstCntrl <= `FLAG;
200			`end`
201			`SETUP_HC_WAIT_RDY:
202			`if (sendPacketRdy == 1'b1)`
203			`begin`
204			NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
205			`next_sendPacketWEn <= 1'b1;`
206			next_sendPacketPID <= `SETUP;
207			`end`
208			`SETUP_WAIT_SETUP_SENT:
209			`if (sendPacketRdy == 1'b1)`
210			`begin`
211			NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
212			`next_sendPacketWEn <= 1'b1;`
213			next_sendPacketPID <= `DATA0;
214			`end`
215			`SETUP_WAIT_DATA_SENT:
216			`if (sendPacketRdy == 1'b1)`
217			`begin`
218			NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
219			`next_getPacketREn <= 1'b1;`
220			`end`
221			`IN_WAIT_DATA_RXED:
222			`begin`
223			`next_getPacketREn <= 1'b0;`
224			`if (getPacketRdy == 1'b1)`
225			NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
226			`end`
227			`IN_CHK_FOR_ERROR:
228			`if (isoEn == 1'b1)`
229			NextState_hstCntrl <= `FLAG;
230			else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
231			RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
232			RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
233			RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
234			RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
235			RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
236			NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
237			`else`
238			NextState_hstCntrl <= `FLAG;
239			`IN_CLR_SP_WEN2:
240			`begin`
241			`next_sendPacketWEn <= 1'b0;`
242			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
243			`end`
244			`IN_WAIT_IN_SENT:
245			`if (sendPacketRdy == 1'b1)`
246			`begin`
247			NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
248			`next_getPacketREn <= 1'b1;`
249			`end`
250			`IN_WAIT_SP_RDY1:
251			`if (sendPacketRdy == 1'b1)`
252			`begin`
253			NextState_hstCntrl <= `IN_CLR_SP_WEN1;
254			`next_sendPacketWEn <= 1'b1;`
255			next_sendPacketPID <= `IN;
256			`end`
257			`IN_WAIT_SP_RDY2:
258			`if (sendPacketRdy == 1'b1)`
259			`begin`
260			NextState_hstCntrl <= `IN_CLR_SP_WEN2;
261			`next_sendPacketWEn <= 1'b1;`
262			next_sendPacketPID <= `ACK;
263			`end`
264			`IN_CLR_SP_WEN1:
265			`begin`
266			`next_sendPacketWEn <= 1'b0;`
267			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
268			`end`
269			`IN_WAIT_ACK_SENT:
270			`if (sendPacketRdy == 1'b1)`
271			NextState_hstCntrl <= `FLAG;
272			`OUT0_WAIT_RX_DATA:
273			`begin`
274			`next_getPacketREn <= 1'b0;`
275			`if (getPacketRdy == 1'b1)`
276			NextState_hstCntrl <= `FLAG;
277			`end`
278			`OUT0_WAIT_DATA0_SENT:
279			`if (sendPacketRdy == 1'b1)`
280			NextState_hstCntrl <= `OUT0_CHK_ISO;
281			`OUT0_WAIT_OUT_SENT:
282			`if (sendPacketRdy == 1'b1)`
283			`begin`
284			NextState_hstCntrl <= `OUT0_CLR_WEN2;
285			`next_sendPacketWEn <= 1'b1;`
286			next_sendPacketPID <= `DATA0;
287			`end`
288			`OUT0_WAIT_SP_RDY1:
289			`if (sendPacketRdy == 1'b1)`
290			`begin`
291			NextState_hstCntrl <= `OUT0_CLR_WEN1;
292			`next_sendPacketWEn <= 1'b1;`
293			next_sendPacketPID <= `OUT;
294			`end`
295			`OUT0_CLR_WEN1:
296			`begin`
297			`next_sendPacketWEn <= 1'b0;`
298			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
299			`end`
300			`OUT0_CLR_WEN2:
301			`begin`
302			`next_sendPacketWEn <= 1'b0;`
303			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
304			`end`
305			`OUT0_CHK_ISO:
306			`if (isoEn == 1'b0)`
307			`begin`
308			NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
309			`next_getPacketREn <= 1'b1;`
310			`end`
311			`else`
312			NextState_hstCntrl <= `FLAG;
313			`OUT1_WAIT_RX_DATA:
314			`begin`
315			`next_getPacketREn <= 1'b0;`
316			`if (getPacketRdy == 1'b1)`
317			NextState_hstCntrl <= `FLAG;
318			`end`
319			`OUT1_WAIT_OUT_SENT:
320			`if (sendPacketRdy == 1'b1)`
321			`begin`
322			NextState_hstCntrl <= `OUT1_CLR_WEN2;
323			`next_sendPacketWEn <= 1'b1;`
324			next_sendPacketPID <= `DATA1;
325			`end`
326			`OUT1_WAIT_DATA1_SENT:
327			`if (sendPacketRdy == 1'b1)`
328			`begin`
329			NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
330			`next_getPacketREn <= 1'b1;`
331			`end`
332			`OUT1_WAIT_SP_RDY1:
333			`if (sendPacketRdy == 1'b1)`
334			`begin`
335			NextState_hstCntrl <= `OUT1_CLR_WEN1;
336			`next_sendPacketWEn <= 1'b1;`
337			next_sendPacketPID <= `OUT;
338			`end`
339			`OUT1_CLR_WEN1:
340			`begin`
341			`next_sendPacketWEn <= 1'b0;`
342			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
343			`end`
344			`OUT1_CLR_WEN2:
345			`begin`
346			`next_sendPacketWEn <= 1'b0;`
347			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
348			`end`
349			`endcase`
350	5	sfielding	`end`
351
352	22	sfielding	`//----------------------------------`
353	5	sfielding	`// Current State Logic (sequential)`
354	22	sfielding	`//----------------------------------`
355	5	sfielding	`always @ (posedge clk)`
356	22	sfielding	`begin : hstCntrl_CurrentState`
357	34	sfielding	`if (rst)`
358			CurrState_hstCntrl <= `START_HC;
359			`else`
360			`CurrState_hstCntrl <= NextState_hstCntrl;`
361	5	sfielding	`end`
362
363	22	sfielding	`//----------------------------------`
364	5	sfielding	`// Registered outputs logic`
365	22	sfielding	`//----------------------------------`
366	5	sfielding	`always @ (posedge clk)`
367	22	sfielding	`begin : hstCntrl_RegOutput`
368	34	sfielding	`if (rst)`
369			`begin`
370			`transDone <= 1'b0;`
371			`clearTXReq <= 1'b0;`
372			`getPacketREn <= 1'b0;`
373			`sendPacketArbiterReq <= 1'b0;`
374			`sendPacketWEn <= 1'b0;`
375			`sendPacketPID <= 4'b0;`
376			`end`
377			`else`
378			`begin`
379			`transDone <= next_transDone;`
380			`clearTXReq <= next_clearTXReq;`
381			`getPacketREn <= next_getPacketREn;`
382			`sendPacketArbiterReq <= next_sendPacketArbiterReq;`
383			`sendPacketWEn <= next_sendPacketWEn;`
384			`sendPacketPID <= next_sendPacketPID;`
385			`end`
386	5	sfielding	`end`
387
388	2	sfielding	`endmodule`

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