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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// hostController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbHostControl_h.v"
`include "usbConstants_h.v"
 
 
module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
input   clk;
input   getPacketRdy;
input   rst;
input   [7:0]RXStatus;
input   sendPacketArbiterGnt;
input   sendPacketRdy;
input   transReq;
input   [1:0]transType;
output  clearTXReq;
output  getPacketREn;
output  sendPacketArbiterReq;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  transDone;
 
reg     clearTXReq, next_clearTXReq;
wire    clk;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
wire    rst;
wire    [7:0]RXStatus;
wire    sendPacketArbiterGnt;
reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     transDone, next_transDone;
wire    transReq;
wire    [1:0]transType;
 
// BINARY ENCODED state machine: hstCntrl
// State codes definitions:
`define START_HC 5'b00000
`define TX_REQ 5'b00001
`define CHK_TYPE 5'b00010
`define FLAG 5'b00011
`define IN_WAIT_DATA_RXED 5'b00100
`define IN_CHK_FOR_ERROR 5'b00101
`define IN_CLR_SP_WEN2 5'b00110
`define SETUP_CLR_SP_WEN1 5'b00111
`define SETUP_CLR_SP_WEN2 5'b01000
`define FIN 5'b01001
`define WAIT_GNT 5'b01010
`define SETUP_WAIT_PKT_RXED 5'b01011
`define IN_WAIT_IN_SENT 5'b01100
`define OUT0_WAIT_RX_DATA 5'b01101
`define OUT0_WAIT_DATA0_SENT 5'b01110
`define OUT0_WAIT_OUT_SENT 5'b01111
`define SETUP_HC_WAIT_RDY 5'b10000
`define IN_WAIT_SP_RDY1 5'b10001
`define IN_WAIT_SP_RDY2 5'b10010
`define OUT0_WAIT_SP_RDY1 5'b10011
`define SETUP_WAIT_SETUP_SENT 5'b10100
`define SETUP_WAIT_DATA_SENT 5'b10101
`define IN_CLR_SP_WEN1 5'b10110
`define IN_WAIT_ACK_SENT 5'b10111
`define OUT0_CLR_WEN1 5'b11000
`define OUT0_CLR_WEN2 5'b11001
`define OUT1_WAIT_RX_DATA 5'b11010
`define OUT1_WAIT_OUT_SENT 5'b11011
`define OUT1_WAIT_DATA1_SENT 5'b11100
`define OUT1_WAIT_SP_RDY1 5'b11101
`define OUT1_CLR_WEN1 5'b11110
`define OUT1_CLR_WEN2 5'b11111
 
reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
 
 
// Machine: hstCntrl
 
// NextState logic (combinatorial)
always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
begin
  NextState_hstCntrl <= CurrState_hstCntrl;
  // Set default values for outputs and signals
  next_transDone <= transDone;
  next_clearTXReq <= clearTXReq;
  next_getPacketREn <= getPacketREn;
  next_sendPacketArbiterReq <= sendPacketArbiterReq;
  next_sendPacketPID <= sendPacketPID;
  next_sendPacketWEn <= sendPacketWEn;
  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
    `START_HC:
    begin
      NextState_hstCntrl <= `TX_REQ;
    end
    `TX_REQ:
    begin
      if (transReq == 1'b1)
      begin
        NextState_hstCntrl <= `WAIT_GNT;
        next_sendPacketArbiterReq <= 1'b1;
      end
    end
    `CHK_TYPE:
    begin
      if (transType == `OUTDATA0_TRANS)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
      end
      else if (transType == `IN_TRANS)
      begin
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
      end
      else if (transType == `SETUP_TRANS)
      begin
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
      end
      else if (transType == `OUTDATA1_TRANS)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
      end
    end
    `FLAG:
    begin
      next_transDone <= 1'b1;
      next_clearTXReq <= 1'b1;
      next_sendPacketArbiterReq <= 1'b0;
      NextState_hstCntrl <= `FIN;
    end
    `FIN:
    begin
      next_transDone <= 1'b0;
      next_clearTXReq <= 1'b0;
      NextState_hstCntrl <= `TX_REQ;
    end
    `WAIT_GNT:
    begin
      if (sendPacketArbiterGnt == 1'b1)
      begin
        NextState_hstCntrl <= `CHK_TYPE;
      end
    end
    `SETUP_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
    end
    `SETUP_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
    end
    `SETUP_WAIT_PKT_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `SETUP_HC_WAIT_RDY:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `SETUP;
      end
    end
    `SETUP_WAIT_SETUP_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    end
    `SETUP_WAIT_DATA_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_WAIT_DATA_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
      end
    end
    `IN_CHK_FOR_ERROR:
    begin
      if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
      begin
        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
      end
      else
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `IN_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
    end
    `IN_WAIT_IN_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `IN;
      end
    end
    `IN_WAIT_SP_RDY2:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `IN_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
    end
    `IN_WAIT_ACK_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT0_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT0_WAIT_DATA0_SENT:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    end
    `OUT0_WAIT_OUT_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    end
    `OUT0_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    end
    `OUT0_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
    end
    `OUT0_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
    end
    `OUT1_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT1_WAIT_OUT_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `OUT1_WAIT_DATA1_SENT:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    end
    `OUT1_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    end
    `OUT1_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
    end
    `OUT1_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_hstCntrl <= `START_HC;
  else
    CurrState_hstCntrl <= NextState_hstCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    transDone <= 1'b0;
    clearTXReq <= 1'b0;
    getPacketREn <= 1'b0;
    sendPacketArbiterReq <= 1'b0;
    sendPacketPID <= 4'b0;
    sendPacketWEn <= 1'b0;
  end
  else
  begin
    transDone <= next_transDone;
    clearTXReq <= next_clearTXReq;
    getPacketREn <= next_getPacketREn;
    sendPacketArbiterReq <= next_sendPacketArbiterReq;
    sendPacketPID <= next_sendPacketPID;
    sendPacketWEn <= next_sendPacketWEn;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// hostController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	7	sfielding	`// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $`
46	5	sfielding	`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbHostControl_h.v"
53			`include "usbConstants_h.v"
54
55
56			`module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);`
57			`input clk;`
58			`input getPacketRdy;`
59			`input rst;`
60			`input [7:0]RXStatus;`
61			`input sendPacketArbiterGnt;`
62			`input sendPacketRdy;`
63			`input transReq;`
64			`input [1:0]transType;`
65			`output clearTXReq;`
66			`output getPacketREn;`
67			`output sendPacketArbiterReq;`
68			`output [3:0]sendPacketPID;`
69			`output sendPacketWEn;`
70			`output transDone;`
71
72			`reg clearTXReq, next_clearTXReq;`
73			`wire clk;`
74			`wire getPacketRdy;`
75			`reg getPacketREn, next_getPacketREn;`
76			`wire rst;`
77			`wire [7:0]RXStatus;`
78			`wire sendPacketArbiterGnt;`
79			`reg sendPacketArbiterReq, next_sendPacketArbiterReq;`
80			`reg [3:0]sendPacketPID, next_sendPacketPID;`
81			`wire sendPacketRdy;`
82			`reg sendPacketWEn, next_sendPacketWEn;`
83			`reg transDone, next_transDone;`
84			`wire transReq;`
85			`wire [1:0]transType;`
86
87			`// BINARY ENCODED state machine: hstCntrl`
88			`// State codes definitions:`
89			`define START_HC 5'b00000
90			`define TX_REQ 5'b00001
91			`define CHK_TYPE 5'b00010
92			`define FLAG 5'b00011
93			`define IN_WAIT_DATA_RXED 5'b00100
94			`define IN_CHK_FOR_ERROR 5'b00101
95			`define IN_CLR_SP_WEN2 5'b00110
96			`define SETUP_CLR_SP_WEN1 5'b00111
97			`define SETUP_CLR_SP_WEN2 5'b01000
98			`define FIN 5'b01001
99			`define WAIT_GNT 5'b01010
100			`define SETUP_WAIT_PKT_RXED 5'b01011
101			`define IN_WAIT_IN_SENT 5'b01100
102			`define OUT0_WAIT_RX_DATA 5'b01101
103			`define OUT0_WAIT_DATA0_SENT 5'b01110
104			`define OUT0_WAIT_OUT_SENT 5'b01111
105			`define SETUP_HC_WAIT_RDY 5'b10000
106			`define IN_WAIT_SP_RDY1 5'b10001
107			`define IN_WAIT_SP_RDY2 5'b10010
108			`define OUT0_WAIT_SP_RDY1 5'b10011
109			`define SETUP_WAIT_SETUP_SENT 5'b10100
110			`define SETUP_WAIT_DATA_SENT 5'b10101
111			`define IN_CLR_SP_WEN1 5'b10110
112			`define IN_WAIT_ACK_SENT 5'b10111
113			`define OUT0_CLR_WEN1 5'b11000
114			`define OUT0_CLR_WEN2 5'b11001
115			`define OUT1_WAIT_RX_DATA 5'b11010
116			`define OUT1_WAIT_OUT_SENT 5'b11011
117			`define OUT1_WAIT_DATA1_SENT 5'b11100
118			`define OUT1_WAIT_SP_RDY1 5'b11101
119			`define OUT1_CLR_WEN1 5'b11110
120			`define OUT1_CLR_WEN2 5'b11111
121
122			`reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;`
123
124
125			`// Machine: hstCntrl`
126
127			`// NextState logic (combinatorial)`
128			`always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)`
129			`begin`
130			`NextState_hstCntrl <= CurrState_hstCntrl;`
131			`// Set default values for outputs and signals`
132			`next_transDone <= transDone;`
133			`next_clearTXReq <= clearTXReq;`
134			`next_getPacketREn <= getPacketREn;`
135			`next_sendPacketArbiterReq <= sendPacketArbiterReq;`
136			`next_sendPacketPID <= sendPacketPID;`
137			`next_sendPacketWEn <= sendPacketWEn;`
138			`case (CurrState_hstCntrl) // synopsys parallel_case full_case`
139			`START_HC:
140			`begin`
141			NextState_hstCntrl <= `TX_REQ;
142			`end`
143			`TX_REQ:
144			`begin`
145			`if (transReq == 1'b1)`
146			`begin`
147			NextState_hstCntrl <= `WAIT_GNT;
148			`next_sendPacketArbiterReq <= 1'b1;`
149			`end`
150			`end`
151			`CHK_TYPE:
152			`begin`
153	7	sfielding	if (transType == `OUTDATA0_TRANS)
154	5	sfielding	`begin`
155	7	sfielding	NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
156			`end`
157			else if (transType == `IN_TRANS)
158			`begin`
159	5	sfielding	NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
160			`end`
161	7	sfielding	else if (transType == `SETUP_TRANS)
162	5	sfielding	`begin`
163	7	sfielding	NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
164	5	sfielding	`end`
165			else if (transType == `OUTDATA1_TRANS)
166			`begin`
167			NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
168			`end`
169			`end`
170			`FLAG:
171			`begin`
172			`next_transDone <= 1'b1;`
173			`next_clearTXReq <= 1'b1;`
174			`next_sendPacketArbiterReq <= 1'b0;`
175			NextState_hstCntrl <= `FIN;
176			`end`
177			`FIN:
178			`begin`
179			`next_transDone <= 1'b0;`
180			`next_clearTXReq <= 1'b0;`
181			NextState_hstCntrl <= `TX_REQ;
182			`end`
183			`WAIT_GNT:
184			`begin`
185			`if (sendPacketArbiterGnt == 1'b1)`
186			`begin`
187			NextState_hstCntrl <= `CHK_TYPE;
188			`end`
189			`end`
190			`SETUP_CLR_SP_WEN1:
191			`begin`
192			`next_sendPacketWEn <= 1'b0;`
193			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
194			`end`
195			`SETUP_CLR_SP_WEN2:
196			`begin`
197			`next_sendPacketWEn <= 1'b0;`
198			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
199			`end`
200			`SETUP_WAIT_PKT_RXED:
201			`begin`
202			`next_getPacketREn <= 1'b0;`
203			`if (getPacketRdy == 1'b1)`
204			`begin`
205			NextState_hstCntrl <= `FLAG;
206			`end`
207			`end`
208			`SETUP_HC_WAIT_RDY:
209			`begin`
210			`if (sendPacketRdy == 1'b1)`
211			`begin`
212			NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
213			`next_sendPacketWEn <= 1'b1;`
214			next_sendPacketPID <= `SETUP;
215			`end`
216			`end`
217			`SETUP_WAIT_SETUP_SENT:
218			`begin`
219			`if (sendPacketRdy == 1'b1)`
220			`begin`
221			NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
222			`next_sendPacketWEn <= 1'b1;`
223			next_sendPacketPID <= `DATA0;
224			`end`
225			`end`
226			`SETUP_WAIT_DATA_SENT:
227			`begin`
228			`if (sendPacketRdy == 1'b1)`
229			`begin`
230			NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
231			`next_getPacketREn <= 1'b1;`
232			`end`
233			`end`
234			`IN_WAIT_DATA_RXED:
235			`begin`
236			`next_getPacketREn <= 1'b0;`
237			`if (getPacketRdy == 1'b1)`
238			`begin`
239			NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
240			`end`
241			`end`
242			`IN_CHK_FOR_ERROR:
243			`begin`
244			if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
245			RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
246			RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
247			RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
248			RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
249			RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
250			`begin`
251			NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
252			`end`
253			`else`
254			`begin`
255			NextState_hstCntrl <= `FLAG;
256			`end`
257			`end`
258			`IN_CLR_SP_WEN2:
259			`begin`
260			`next_sendPacketWEn <= 1'b0;`
261			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
262			`end`
263			`IN_WAIT_IN_SENT:
264			`begin`
265			`if (sendPacketRdy == 1'b1)`
266			`begin`
267			NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
268			`next_getPacketREn <= 1'b1;`
269			`end`
270			`end`
271			`IN_WAIT_SP_RDY1:
272			`begin`
273			`if (sendPacketRdy == 1'b1)`
274			`begin`
275			NextState_hstCntrl <= `IN_CLR_SP_WEN1;
276			`next_sendPacketWEn <= 1'b1;`
277			next_sendPacketPID <= `IN;
278			`end`
279			`end`
280			`IN_WAIT_SP_RDY2:
281			`begin`
282			`if (sendPacketRdy == 1'b1)`
283			`begin`
284			NextState_hstCntrl <= `IN_CLR_SP_WEN2;
285			`next_sendPacketWEn <= 1'b1;`
286			next_sendPacketPID <= `ACK;
287			`end`
288			`end`
289			`IN_CLR_SP_WEN1:
290			`begin`
291			`next_sendPacketWEn <= 1'b0;`
292			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
293			`end`
294			`IN_WAIT_ACK_SENT:
295			`begin`
296			`if (sendPacketRdy == 1'b1)`
297			`begin`
298			NextState_hstCntrl <= `FLAG;
299			`end`
300			`end`
301			`OUT0_WAIT_RX_DATA:
302			`begin`
303			`next_getPacketREn <= 1'b0;`
304			`if (getPacketRdy == 1'b1)`
305			`begin`
306			NextState_hstCntrl <= `FLAG;
307			`end`
308			`end`
309			`OUT0_WAIT_DATA0_SENT:
310			`begin`
311			`next_sendPacketWEn <= 1'b0;`
312			`if (sendPacketRdy == 1'b1)`
313			`begin`
314			NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
315			`next_getPacketREn <= 1'b1;`
316			`end`
317			`end`
318			`OUT0_WAIT_OUT_SENT:
319			`begin`
320			`if (sendPacketRdy == 1'b1)`
321			`begin`
322			NextState_hstCntrl <= `OUT0_CLR_WEN2;
323			`next_sendPacketWEn <= 1'b1;`
324			next_sendPacketPID <= `DATA0;
325			`end`
326			`end`
327			`OUT0_WAIT_SP_RDY1:
328			`begin`
329			`if (sendPacketRdy == 1'b1)`
330			`begin`
331			NextState_hstCntrl <= `OUT0_CLR_WEN1;
332			`next_sendPacketWEn <= 1'b1;`
333			next_sendPacketPID <= `OUT;
334			`end`
335			`end`
336			`OUT0_CLR_WEN1:
337			`begin`
338			`next_sendPacketWEn <= 1'b0;`
339			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
340			`end`
341			`OUT0_CLR_WEN2:
342			`begin`
343			`next_sendPacketWEn <= 1'b0;`
344			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
345			`end`
346			`OUT1_WAIT_RX_DATA:
347			`begin`
348			`next_getPacketREn <= 1'b0;`
349			`if (getPacketRdy == 1'b1)`
350			`begin`
351			NextState_hstCntrl <= `FLAG;
352			`end`
353			`end`
354			`OUT1_WAIT_OUT_SENT:
355			`begin`
356			`if (sendPacketRdy == 1'b1)`
357			`begin`
358			NextState_hstCntrl <= `OUT1_CLR_WEN2;
359			`next_sendPacketWEn <= 1'b1;`
360			next_sendPacketPID <= `DATA1;
361			`end`
362			`end`
363			`OUT1_WAIT_DATA1_SENT:
364			`begin`
365			`next_sendPacketWEn <= 1'b0;`
366			`if (sendPacketRdy == 1'b1)`
367			`begin`
368			NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
369			`next_getPacketREn <= 1'b1;`
370			`end`
371			`end`
372			`OUT1_WAIT_SP_RDY1:
373			`begin`
374			`if (sendPacketRdy == 1'b1)`
375			`begin`
376			NextState_hstCntrl <= `OUT1_CLR_WEN1;
377			`next_sendPacketWEn <= 1'b1;`
378			next_sendPacketPID <= `OUT;
379			`end`
380			`end`
381			`OUT1_CLR_WEN1:
382			`begin`
383			`next_sendPacketWEn <= 1'b0;`
384			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
385			`end`
386			`OUT1_CLR_WEN2:
387			`begin`
388			`next_sendPacketWEn <= 1'b0;`
389			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
390			`end`
391			`endcase`
392			`end`
393
394			`// Current State Logic (sequential)`
395			`always @ (posedge clk)`
396			`begin`
397			`if (rst)`
398			CurrState_hstCntrl <= `START_HC;
399			`else`
400			`CurrState_hstCntrl <= NextState_hstCntrl;`
401			`end`
402
403			`// Registered outputs logic`
404			`always @ (posedge clk)`
405			`begin`
406			`if (rst)`
407			`begin`
408			`transDone <= 1'b0;`
409			`clearTXReq <= 1'b0;`
410			`getPacketREn <= 1'b0;`
411			`sendPacketArbiterReq <= 1'b0;`
412			`sendPacketPID <= 4'b0;`
413			`sendPacketWEn <= 1'b0;`
414			`end`
415			`else`
416			`begin`
417			`transDone <= next_transDone;`
418			`clearTXReq <= next_clearTXReq;`
419			`getPacketREn <= next_getPacketREn;`
420			`sendPacketArbiterReq <= next_sendPacketArbiterReq;`
421			`sendPacketPID <= next_sendPacketPID;`
422			`sendPacketWEn <= next_sendPacketWEn;`
423			`end`
424			`end`
425
426	2	sfielding	`endmodule`

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