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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// hostController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbHostControl_h.v"
`include "usbConstants_h.v"
 
 
module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
input   clk;
input   getPacketRdy;
input   rst;
input   [7:0]RXStatus;
input   sendPacketArbiterGnt;
input   sendPacketRdy;
input   transReq;
input   [1:0]transType;
output  clearTXReq;
output  getPacketREn;
output  sendPacketArbiterReq;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  transDone;
 
reg     clearTXReq, next_clearTXReq;
wire    clk;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
wire    rst;
wire    [7:0]RXStatus;
wire    sendPacketArbiterGnt;
reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     transDone, next_transDone;
wire    transReq;
wire    [1:0]transType;
 
// BINARY ENCODED state machine: hstCntrl
// State codes definitions:
`define START_HC 5'b00000
`define TX_REQ 5'b00001
`define CHK_TYPE 5'b00010
`define FLAG 5'b00011
`define IN_WAIT_DATA_RXED 5'b00100
`define IN_CHK_FOR_ERROR 5'b00101
`define IN_CLR_SP_WEN2 5'b00110
`define SETUP_CLR_SP_WEN1 5'b00111
`define SETUP_CLR_SP_WEN2 5'b01000
`define FIN 5'b01001
`define WAIT_GNT 5'b01010
`define SETUP_WAIT_PKT_RXED 5'b01011
`define IN_WAIT_IN_SENT 5'b01100
`define OUT0_WAIT_RX_DATA 5'b01101
`define OUT0_WAIT_DATA0_SENT 5'b01110
`define OUT0_WAIT_OUT_SENT 5'b01111
`define SETUP_HC_WAIT_RDY 5'b10000
`define IN_WAIT_SP_RDY1 5'b10001
`define IN_WAIT_SP_RDY2 5'b10010
`define OUT0_WAIT_SP_RDY1 5'b10011
`define SETUP_WAIT_SETUP_SENT 5'b10100
`define SETUP_WAIT_DATA_SENT 5'b10101
`define IN_CLR_SP_WEN1 5'b10110
`define IN_WAIT_ACK_SENT 5'b10111
`define OUT0_CLR_WEN1 5'b11000
`define OUT0_CLR_WEN2 5'b11001
`define OUT1_WAIT_RX_DATA 5'b11010
`define OUT1_WAIT_OUT_SENT 5'b11011
`define OUT1_WAIT_DATA1_SENT 5'b11100
`define OUT1_WAIT_SP_RDY1 5'b11101
`define OUT1_CLR_WEN1 5'b11110
`define OUT1_CLR_WEN2 5'b11111
 
reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
 
 
// Machine: hstCntrl
 
// NextState logic (combinatorial)
always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
begin
  NextState_hstCntrl <= CurrState_hstCntrl;
  // Set default values for outputs and signals
  next_transDone <= transDone;
  next_clearTXReq <= clearTXReq;
  next_getPacketREn <= getPacketREn;
  next_sendPacketArbiterReq <= sendPacketArbiterReq;
  next_sendPacketPID <= sendPacketPID;
  next_sendPacketWEn <= sendPacketWEn;
  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
    `START_HC:
    begin
      NextState_hstCntrl <= `TX_REQ;
    end
    `TX_REQ:
    begin
      if (transReq == 1'b1)
      begin
        NextState_hstCntrl <= `WAIT_GNT;
        next_sendPacketArbiterReq <= 1'b1;
      end
    end
    `CHK_TYPE:
    begin
      if (transType == `IN_TRANS)
      begin
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
      end
      else if (transType == `OUTDATA0_TRANS)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
      end
      else if (transType == `OUTDATA1_TRANS)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
      end
      else if (transType == `SETUP_TRANS)
      begin
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
      end
    end
    `FLAG:
    begin
      next_transDone <= 1'b1;
      next_clearTXReq <= 1'b1;
      next_sendPacketArbiterReq <= 1'b0;
      NextState_hstCntrl <= `FIN;
    end
    `FIN:
    begin
      next_transDone <= 1'b0;
      next_clearTXReq <= 1'b0;
      NextState_hstCntrl <= `TX_REQ;
    end
    `WAIT_GNT:
    begin
      if (sendPacketArbiterGnt == 1'b1)
      begin
        NextState_hstCntrl <= `CHK_TYPE;
      end
    end
    `SETUP_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
    end
    `SETUP_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
    end
    `SETUP_WAIT_PKT_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `SETUP_HC_WAIT_RDY:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `SETUP;
      end
    end
    `SETUP_WAIT_SETUP_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    end
    `SETUP_WAIT_DATA_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_WAIT_DATA_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
      end
    end
    `IN_CHK_FOR_ERROR:
    begin
      if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
      begin
        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
      end
      else
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `IN_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
    end
    `IN_WAIT_IN_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `IN;
      end
    end
    `IN_WAIT_SP_RDY2:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `IN_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
    end
    `IN_WAIT_ACK_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT0_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT0_WAIT_DATA0_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    end
    `OUT0_WAIT_OUT_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    end
    `OUT0_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    end
    `OUT0_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
    end
    `OUT0_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
    end
    `OUT1_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `FLAG;
      end
    end
    `OUT1_WAIT_OUT_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `OUT1_WAIT_DATA1_SENT:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    end
    `OUT1_WAIT_SP_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    end
    `OUT1_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
    end
    `OUT1_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_hstCntrl <= `START_HC;
  else
    CurrState_hstCntrl <= NextState_hstCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    transDone <= 1'b0;
    clearTXReq <= 1'b0;
    getPacketREn <= 1'b0;
    sendPacketArbiterReq <= 1'b0;
    sendPacketPID <= 4'b0;
    sendPacketWEn <= 1'b0;
  end
  else
  begin
    transDone <= next_transDone;
    clearTXReq <= next_clearTXReq;
    getPacketREn <= next_getPacketREn;
    sendPacketArbiterReq <= next_sendPacketArbiterReq;
    sendPacketPID <= next_sendPacketPID;
    sendPacketWEn <= next_sendPacketWEn;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// hostController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbHostControl_h.v"
47			`include "usbConstants_h.v"
48
49
50			`module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);`
51			`input clk;`
52			`input getPacketRdy;`
53			`input rst;`
54			`input [7:0]RXStatus;`
55			`input sendPacketArbiterGnt;`
56			`input sendPacketRdy;`
57			`input transReq;`
58			`input [1:0]transType;`
59			`output clearTXReq;`
60			`output getPacketREn;`
61			`output sendPacketArbiterReq;`
62			`output [3:0]sendPacketPID;`
63			`output sendPacketWEn;`
64			`output transDone;`
65
66			`reg clearTXReq, next_clearTXReq;`
67			`wire clk;`
68			`wire getPacketRdy;`
69			`reg getPacketREn, next_getPacketREn;`
70			`wire rst;`
71			`wire [7:0]RXStatus;`
72			`wire sendPacketArbiterGnt;`
73			`reg sendPacketArbiterReq, next_sendPacketArbiterReq;`
74			`reg [3:0]sendPacketPID, next_sendPacketPID;`
75			`wire sendPacketRdy;`
76			`reg sendPacketWEn, next_sendPacketWEn;`
77			`reg transDone, next_transDone;`
78			`wire transReq;`
79			`wire [1:0]transType;`
80
81			`// BINARY ENCODED state machine: hstCntrl`
82			`// State codes definitions:`
83			`define START_HC 5'b00000
84			`define TX_REQ 5'b00001
85			`define CHK_TYPE 5'b00010
86			`define FLAG 5'b00011
87			`define IN_WAIT_DATA_RXED 5'b00100
88			`define IN_CHK_FOR_ERROR 5'b00101
89			`define IN_CLR_SP_WEN2 5'b00110
90			`define SETUP_CLR_SP_WEN1 5'b00111
91			`define SETUP_CLR_SP_WEN2 5'b01000
92			`define FIN 5'b01001
93			`define WAIT_GNT 5'b01010
94			`define SETUP_WAIT_PKT_RXED 5'b01011
95			`define IN_WAIT_IN_SENT 5'b01100
96			`define OUT0_WAIT_RX_DATA 5'b01101
97			`define OUT0_WAIT_DATA0_SENT 5'b01110
98			`define OUT0_WAIT_OUT_SENT 5'b01111
99			`define SETUP_HC_WAIT_RDY 5'b10000
100			`define IN_WAIT_SP_RDY1 5'b10001
101			`define IN_WAIT_SP_RDY2 5'b10010
102			`define OUT0_WAIT_SP_RDY1 5'b10011
103			`define SETUP_WAIT_SETUP_SENT 5'b10100
104			`define SETUP_WAIT_DATA_SENT 5'b10101
105			`define IN_CLR_SP_WEN1 5'b10110
106			`define IN_WAIT_ACK_SENT 5'b10111
107			`define OUT0_CLR_WEN1 5'b11000
108			`define OUT0_CLR_WEN2 5'b11001
109			`define OUT1_WAIT_RX_DATA 5'b11010
110			`define OUT1_WAIT_OUT_SENT 5'b11011
111			`define OUT1_WAIT_DATA1_SENT 5'b11100
112			`define OUT1_WAIT_SP_RDY1 5'b11101
113			`define OUT1_CLR_WEN1 5'b11110
114			`define OUT1_CLR_WEN2 5'b11111
115
116			`reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;`
117
118
119			`// Machine: hstCntrl`
120
121			`// NextState logic (combinatorial)`
122			`always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)`
123			`begin`
124			`NextState_hstCntrl <= CurrState_hstCntrl;`
125			`// Set default values for outputs and signals`
126			`next_transDone <= transDone;`
127			`next_clearTXReq <= clearTXReq;`
128			`next_getPacketREn <= getPacketREn;`
129			`next_sendPacketArbiterReq <= sendPacketArbiterReq;`
130			`next_sendPacketPID <= sendPacketPID;`
131			`next_sendPacketWEn <= sendPacketWEn;`
132			`case (CurrState_hstCntrl) // synopsys parallel_case full_case`
133			`START_HC:
134			`begin`
135			NextState_hstCntrl <= `TX_REQ;
136			`end`
137			`TX_REQ:
138			`begin`
139			`if (transReq == 1'b1)`
140			`begin`
141			NextState_hstCntrl <= `WAIT_GNT;
142			`next_sendPacketArbiterReq <= 1'b1;`
143			`end`
144			`end`
145			`CHK_TYPE:
146			`begin`
147	9	sfielding	if (transType == `IN_TRANS)
148	5	sfielding	`begin`
149	9	sfielding	NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
150			`end`
151			else if (transType == `OUTDATA0_TRANS)
152			`begin`
153	7	sfielding	NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
154			`end`
155	9	sfielding	else if (transType == `OUTDATA1_TRANS)
156	7	sfielding	`begin`
157	9	sfielding	NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
158	5	sfielding	`end`
159	7	sfielding	else if (transType == `SETUP_TRANS)
160	5	sfielding	`begin`
161	7	sfielding	NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
162	5	sfielding	`end`
163			`end`
164			`FLAG:
165			`begin`
166			`next_transDone <= 1'b1;`
167			`next_clearTXReq <= 1'b1;`
168			`next_sendPacketArbiterReq <= 1'b0;`
169			NextState_hstCntrl <= `FIN;
170			`end`
171			`FIN:
172			`begin`
173			`next_transDone <= 1'b0;`
174			`next_clearTXReq <= 1'b0;`
175			NextState_hstCntrl <= `TX_REQ;
176			`end`
177			`WAIT_GNT:
178			`begin`
179			`if (sendPacketArbiterGnt == 1'b1)`
180			`begin`
181			NextState_hstCntrl <= `CHK_TYPE;
182			`end`
183			`end`
184			`SETUP_CLR_SP_WEN1:
185			`begin`
186			`next_sendPacketWEn <= 1'b0;`
187			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
188			`end`
189			`SETUP_CLR_SP_WEN2:
190			`begin`
191			`next_sendPacketWEn <= 1'b0;`
192			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
193			`end`
194			`SETUP_WAIT_PKT_RXED:
195			`begin`
196			`next_getPacketREn <= 1'b0;`
197			`if (getPacketRdy == 1'b1)`
198			`begin`
199			NextState_hstCntrl <= `FLAG;
200			`end`
201			`end`
202			`SETUP_HC_WAIT_RDY:
203			`begin`
204			`if (sendPacketRdy == 1'b1)`
205			`begin`
206			NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
207			`next_sendPacketWEn <= 1'b1;`
208			next_sendPacketPID <= `SETUP;
209			`end`
210			`end`
211			`SETUP_WAIT_SETUP_SENT:
212			`begin`
213			`if (sendPacketRdy == 1'b1)`
214			`begin`
215			NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
216			`next_sendPacketWEn <= 1'b1;`
217			next_sendPacketPID <= `DATA0;
218			`end`
219			`end`
220			`SETUP_WAIT_DATA_SENT:
221			`begin`
222			`if (sendPacketRdy == 1'b1)`
223			`begin`
224			NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
225			`next_getPacketREn <= 1'b1;`
226			`end`
227			`end`
228			`IN_WAIT_DATA_RXED:
229			`begin`
230			`next_getPacketREn <= 1'b0;`
231			`if (getPacketRdy == 1'b1)`
232			`begin`
233			NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
234			`end`
235			`end`
236			`IN_CHK_FOR_ERROR:
237			`begin`
238			if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
239			RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
240			RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
241			RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
242			RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
243			RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
244			`begin`
245			NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
246			`end`
247			`else`
248			`begin`
249			NextState_hstCntrl <= `FLAG;
250			`end`
251			`end`
252			`IN_CLR_SP_WEN2:
253			`begin`
254			`next_sendPacketWEn <= 1'b0;`
255			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
256			`end`
257			`IN_WAIT_IN_SENT:
258			`begin`
259			`if (sendPacketRdy == 1'b1)`
260			`begin`
261			NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
262			`next_getPacketREn <= 1'b1;`
263			`end`
264			`end`
265			`IN_WAIT_SP_RDY1:
266			`begin`
267			`if (sendPacketRdy == 1'b1)`
268			`begin`
269			NextState_hstCntrl <= `IN_CLR_SP_WEN1;
270			`next_sendPacketWEn <= 1'b1;`
271			next_sendPacketPID <= `IN;
272			`end`
273			`end`
274			`IN_WAIT_SP_RDY2:
275			`begin`
276			`if (sendPacketRdy == 1'b1)`
277			`begin`
278			NextState_hstCntrl <= `IN_CLR_SP_WEN2;
279			`next_sendPacketWEn <= 1'b1;`
280			next_sendPacketPID <= `ACK;
281			`end`
282			`end`
283			`IN_CLR_SP_WEN1:
284			`begin`
285			`next_sendPacketWEn <= 1'b0;`
286			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
287			`end`
288			`IN_WAIT_ACK_SENT:
289			`begin`
290			`if (sendPacketRdy == 1'b1)`
291			`begin`
292			NextState_hstCntrl <= `FLAG;
293			`end`
294			`end`
295			`OUT0_WAIT_RX_DATA:
296			`begin`
297			`next_getPacketREn <= 1'b0;`
298			`if (getPacketRdy == 1'b1)`
299			`begin`
300			NextState_hstCntrl <= `FLAG;
301			`end`
302			`end`
303			`OUT0_WAIT_DATA0_SENT:
304			`begin`
305			`if (sendPacketRdy == 1'b1)`
306			`begin`
307			NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
308			`next_getPacketREn <= 1'b1;`
309			`end`
310			`end`
311			`OUT0_WAIT_OUT_SENT:
312			`begin`
313			`if (sendPacketRdy == 1'b1)`
314			`begin`
315			NextState_hstCntrl <= `OUT0_CLR_WEN2;
316			`next_sendPacketWEn <= 1'b1;`
317			next_sendPacketPID <= `DATA0;
318			`end`
319			`end`
320			`OUT0_WAIT_SP_RDY1:
321			`begin`
322			`if (sendPacketRdy == 1'b1)`
323			`begin`
324			NextState_hstCntrl <= `OUT0_CLR_WEN1;
325			`next_sendPacketWEn <= 1'b1;`
326			next_sendPacketPID <= `OUT;
327			`end`
328			`end`
329			`OUT0_CLR_WEN1:
330			`begin`
331			`next_sendPacketWEn <= 1'b0;`
332			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
333			`end`
334			`OUT0_CLR_WEN2:
335			`begin`
336			`next_sendPacketWEn <= 1'b0;`
337			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
338			`end`
339			`OUT1_WAIT_RX_DATA:
340			`begin`
341			`next_getPacketREn <= 1'b0;`
342			`if (getPacketRdy == 1'b1)`
343			`begin`
344			NextState_hstCntrl <= `FLAG;
345			`end`
346			`end`
347			`OUT1_WAIT_OUT_SENT:
348			`begin`
349			`if (sendPacketRdy == 1'b1)`
350			`begin`
351			NextState_hstCntrl <= `OUT1_CLR_WEN2;
352			`next_sendPacketWEn <= 1'b1;`
353			next_sendPacketPID <= `DATA1;
354			`end`
355			`end`
356			`OUT1_WAIT_DATA1_SENT:
357			`begin`
358			`if (sendPacketRdy == 1'b1)`
359			`begin`
360			NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
361			`next_getPacketREn <= 1'b1;`
362			`end`
363			`end`
364			`OUT1_WAIT_SP_RDY1:
365			`begin`
366			`if (sendPacketRdy == 1'b1)`
367			`begin`
368			NextState_hstCntrl <= `OUT1_CLR_WEN1;
369			`next_sendPacketWEn <= 1'b1;`
370			next_sendPacketPID <= `OUT;
371			`end`
372			`end`
373			`OUT1_CLR_WEN1:
374			`begin`
375			`next_sendPacketWEn <= 1'b0;`
376			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
377			`end`
378			`OUT1_CLR_WEN2:
379			`begin`
380			`next_sendPacketWEn <= 1'b0;`
381			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
382			`end`
383			`endcase`
384			`end`
385
386			`// Current State Logic (sequential)`
387			`always @ (posedge clk)`
388			`begin`
389			`if (rst)`
390			CurrState_hstCntrl <= `START_HC;
391			`else`
392			`CurrState_hstCntrl <= NextState_hstCntrl;`
393			`end`
394
395			`// Registered outputs logic`
396			`always @ (posedge clk)`
397			`begin`
398			`if (rst)`
399			`begin`
400			`transDone <= 1'b0;`
401			`clearTXReq <= 1'b0;`
402			`getPacketREn <= 1'b0;`
403			`sendPacketArbiterReq <= 1'b0;`
404			`sendPacketPID <= 4'b0;`
405			`sendPacketWEn <= 1'b0;`
406			`end`
407			`else`
408			`begin`
409			`transDone <= next_transDone;`
410			`clearTXReq <= next_clearTXReq;`
411			`getPacketREn <= next_getPacketREn;`
412			`sendPacketArbiterReq <= next_sendPacketArbiterReq;`
413			`sendPacketPID <= next_sendPacketPID;`
414			`sendPacketWEn <= next_sendPacketWEn;`
415			`end`
416			`end`
417
418	2	sfielding	`endmodule`

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